JPH09326804A - Synchronization controller and synchronization control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make channels between synchronization system terminal equipments efficient in the ATM network system. SOLUTION: An ATM cell received from an ATM network 70 is given to a cell assembly/disassembly function CLAD 4RN corresponding to header information by a cell switch 60 and converted into synchronization system terminal data and stored in each buffer BUFFN2N. A read frequency of which BUFFN2 N is to be corrected is checked through the calculation of priority and corrected by using an adaptive clock recovery method based on a capacity and an accumulated object value of each BUFFN2N and on an accumulated value of each BUFFN2N set to a control section CONT01 at setting of a channel. The read frequency of each BUFFN2N is corrected on the basis of a corrected read frequency. A data read gate RD3N is operated by the corrected read frequency of each BUFFN2N and data are shaped into synchronization system terminal data by a multiplexer/demultiplexer section MUX/DMUX 50 and the resulting data are sent to a synchronization synchronizing signal terminal equipment 80.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous control device and a synchronous control system suitable for controlling fixed-rate data transmission in an asynchronous transfer mode (ATM) network.

[0002]

2. Description of the Related Art Conventionally, this kind of synchronous control system is used to obtain a synchronous clock from an asynchronous packet flow such as an asynchronous transfer mode (ATM) cell flow, as disclosed in, for example, Japanese Unexamined Patent Publication No. 07-046257. It is used.

FIG. 8 is a network configuration diagram showing the connection of synchronous terminals using the conventional adaptive clock recovery method.
As shown in FIG. 8, TD is transmitted through the ATM network 100.
When connecting the synchronous terminals 101 and 102 such as M, A
CES IWF (CBR Emulation Service InterWorki) that terminates the TM protocol and performs TDM ← → ATM data conversion
ng Function: fixed speed data communication function) (A) and (B) are provided for the ATM network 100 and each of the synchronous terminals 101, 10.
It is provided between the two.

In the above network configuration, one communication connection (CBR V
irtual Circuit) is set. The actual data stream flows over this connection in the form of ATM cells, but it is necessary for the receiving side to recover the clock of the transmitting side in order to synchronize with the transmitting side.

FIG. 9 is a block diagram showing the operation of the adaptive clock recovery method. In FIG. 9A, a FIFO buffer (hereinafter referred to as a buffer) 10 that performs a first-in, first-out operation on the receiving side in order to absorb the delay fluctuation of the ATM cell.
3 and a MON 104 is provided as a function of monitoring data accumulation in the buffer 103. Size of buffer 103 (Max
Depth) is uniquely determined according to the adaptive clock recovery method according to the line speed of the connection. In this circuit, the clock on the transmission side uses the buffer 1 according to the deviation between the current data accumulated value and a certain target value (Target Depth).
The signal is reproduced on the receiving side by the frequency control unit 106 that controls the clock for reading data from 03 through the gate 105.

That is, as shown in FIG. 9B, the buffer 10
When the cumulative value of 3 (value of MON 104) is higher than the target value, the read frequency is increased, and when the cumulative value of the buffer 103 is lower than the target value as shown in FIG. 9 (c). Controls to lower the read frequency. As described above, the adaptive clock recovery method is shown in FIG.
A1 ← → B1 and A2 ← → in ES IWF (A) (B)
This is a method of reproducing the clock on the transmitting side at the opposite end by monitoring the increase / decrease of the data stream between B2.

[0007]

The problem of the above-mentioned conventional adaptive clock recovery method is that the line of the synchronous terminal is not used effectively. The reason is that the adaptive clock recovery method is a clock reproduction method focusing only on the increase / decrease of the data stream between the synchronous terminals, and therefore the terminal data allocated to each time slot (64 kbps) in the synchronous terminal is stored in one route. It can only be transmitted to synchronous terminals. In other words, the connection of the synchronous terminal using the adaptive clock recovery method can be only the opposite connection. Therefore, there arises a problem that the number of lines between a plurality of synchronous terminals is required as many as the number of connected terminals.

Therefore, an object of the present invention is to recognize the structure (frame) of data output from each synchronous terminal in each time slot when connecting the synchronous terminals in the ATM network using the adaptive clock recovery method. However, the number of lines of synchronous terminals is reduced by making it possible to select the route of the data for each time slot.

[0009]

A means for converting a plurality of ATM cell data received from an ATM network into synchronous terminal data for each predetermined time slot and a plurality of converted synchronous terminal data respectively. A plurality of memory means, each of which has a predetermined capacity and is set with a target value of a data amount to be accommodated, and a plurality of read means for reading the plurality of memory means at respective read frequencies; Multiplexing means for multiplexing the respective read out synchronous terminal data and transmitting to the synchronous terminal, detecting means for respectively detecting the data amount of the plurality of memory means, and a plurality of detection values of the detecting means. Selection means for preferentially selecting one reading means based on the corresponding target value and capacity and pairing with the selected reading means. Correction means for correcting the read frequency so that the data amount of the memory means becomes the target value, and the corrected read frequency is used as a reference frequency, and the number of time slots of data read at this reference frequency and other memories Correction means for correcting the read frequency of the other read means based on the ratio of the data read from the means to the number of time slots.

Further, there may be provided a transmitting means for converting the synchronous terminal data sent from the synchronous terminal into ATM cells and transmitting the ATM cells to the ATM network.

Further, in the synchronous control system according to the present invention, synchronous terminals are connected via an ATM network,
An adaptive clock recovery method is used to convert the transmitting side synchronous terminal data into ATM cells for each time slot connection between the synchronous terminals, and calculate the adaptive clock recovery method from the accumulated data in a plurality of data buffers provided for each time slot connection on the receiving side. In the synchronous control method in which the read frequency of each data buffer is reproduced, the correction priority of the read frequency is calculated from the data cumulative value, the cumulative target value, and the data buffer capacity in each data buffer, and the highest priority is calculated. The read frequency of the data buffer is corrected by using the adaptive clock recovery method, and the number of time slots of data read at the corrected read frequency and the read frequency of another data buffer are based on the corrected read frequency. Ratio of the number of time slots of data read by Et al., Corrects the read frequency of the other data buffers, multiplexes the synchronous terminal data of each time slot read from the respective data buffer,
After formatting to the data format corresponding to the receiving side synchronous terminal,
It is passed to the receiving side synchronous terminal.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows a CES IWF (CBR Emulation) as a synchronization control device according to the present invention installed between an ATM network 70 and a synchronization terminal 80.
It is a block diagram of Service InterWorking Function) 90. In FIG. 1, MUX /
The DMUX 50 accommodates synchronous terminal data and performs data conversion for each one or more time slots having a data rate of 64 kbps according to preset transmission path information.
The X section 50a and the reception data read gate RD3N (N
, 1, 2, ..., N), and multiplexes the data received through the MUX unit 50b for transmitting to the synchronous terminal 80. CLAD (Cell Assembly Deassembly:
Cell assembling / disassembling function) 4SN (N = 1, 2 ... N) and receiving side CLAD 4RN (N = 1, 2 ... N) are cell assembling / disassembling functions for converting synchronous terminal data and ATM cell data to each other. It is a department.

The cell switch 60 outputs an ATM cell output from CLAD4SN and an A output to CLAD4RN.
A cell switch that switches a TM cell according to its cell header information. BUFF2N (N = 1, 2 ...
N) is a FIFO buffer provided to absorb the fluctuation of the synchronous terminal data due to the delay fluctuation of the ATM cell. The BUFF 2N has a monitor function MN (N = 1, 2 ... N) for monitoring the cumulative value of data in each buffer.
Is provided, and the monitored value is the control unit CONT01.
Will be notified.

Next, CONT01 will be described in detail with reference to FIG. Figure 2 shows the inside of CONT01 and CO
It is a block diagram which shows the connection with the peripheral circuit of NT01.
The number of time slots used on each communication connection T
S, each B set according to the number of time slots TS
UFF2N capacity (hereinafter MDN (N = 1, 2 ... N) (Ma
xDepth)) and the data accumulation target value in BUFF2N (hereinafter referred to as TDN (N = 1, 2 ... N) (TargetDepth)) are stored in the storage unit 03 in advance. The PfN calculation unit 02 uses the cumulative amount in the BUFF 2N notified from each MN (hereinafter referred to as CDN (N = 1, 2 ... N) (CurrentDepth)) as a variable, and the correction priority PfN (N = 1, 2 ... N). )
Is calculated.

Frequency generator 05N (N = 1, 2 ... N)
Reads the data of BUFF2N from the data read gate RD
A clock frequency that determines the reading speed when reading through 3N is generated. In addition, the frequency correction unit 04 selects one of the frequency generation units 05N to apply the correction of the adaptive clock recovery method, and uses the corrected frequency as a reference to correct the data read at the corrected read frequency. The frequency of another frequency generation unit is corrected based on the ratio between the number of time slots and the number of time slots of data read at another read frequency. This frequency correction is performed at regular intervals, the period of which is based on the adaptive clock recovery method.

Next, the operation of the circuits shown in FIGS. 1 and 2 will be described. In FIG. 1, the data output from the DMUX 50a is converted into ATM cells in CLAD4SN. The converted ATM cell is switched to the destination route by the cell switch 60 according to the header information.

On the other hand, the received ATM of a plurality of channels
The cell is a CL corresponding to the header information in the cell switch 60.
Switched to AD4RN. A with CLAD4RN
Received data converted from TM cells into synchronous terminal data for each one or more time slots is input to BUFF 2N provided to absorb delay fluctuations of ATM cells. The value of the accumulated data amount CDN detected by the monitor function MN in the BUFF 2N is notified to CONT01.

Next, the operation of CONT01 of FIG. 2 will be described with reference to the flowchart of FIG. First, in step S1, the number of timeslots TS explained on each communication connection, the capacity MDN of BUFF2N and the data accumulation target value TDN in BUFF2N corresponding to the timeslot number TS are set in advance and stored in the storage unit 03. Keep it. Then, when the receiving side circuit is opened and the line is in use in step S2, the value of the cumulative amount CDN in BUFF2N notified from each MN is notified to the PfN calculation unit 02 in step S3. The PfN calculator 02 proceeds to step S4.
Execute the following formula with CDN as a variable in Pf
Find N. PfN (CDN) = | TDN-CDN | / MDN (1)

Pf for each of the N BUFF2Ns
After obtaining N, in step S5, BU having the largest PfN
The clock frequency for reading data from FF2N is
TD is added to the CDN with correction according to the adaptive clock recovery method
In order to bring the frequency closer to N, the PfN calculation unit 02 selects one of the frequency generation units 05N that is generating the frequency to be corrected and notifies the frequency correction unit 04 of this. In response to this, the frequency correction unit 04 performs the correction by performing the control by the adaptive clock recovery method shown in FIG. 9 on the frequency generated by the selected frequency generation unit 05N.

Here, it is assumed that the frequency generator 05m for N = m.
Let fm be the frequency that was generated by and the frequency that has been corrected by the adaptive clock recovery method be fm '. Next, in the frequency correction unit 04, all the frequency generation units 05N except N = m in step S6 with reference to this fm '.
Frequency fN (N = 1, 2 ... N;
= M is excluded) is corrected by performing the following calculation. The read frequency of each buffer 2N after correction is set to fN '. fN ′ = fm ′ × (TS [fN] / TS [fm ′]) (2) (excluding N = m) TS [fN]: Number of time slots of communication connection corresponding to fN TS [fm ′ ]: Fm '〃

The read speed of the data read gate RDN in FIG. 1 is changed by the fm 'corrected by the adaptive clock recovery method and the fN' generated by the equation (2) as described above, and the gate RDm is read. BUF
F2m's CDm approaches TDm.

By performing the above operation at regular intervals,
User data composed of one or more time slots can be transmitted by the adaptive clock recovery method.

FIG. 4 shows the configuration of the CES IWF 90 when N = 1, 2, 3 in FIG. FIG. 5 shows C of FIG.
The configuration of the entire system when the ES IWF 90 is used is shown.

In FIG. 5, synchronous terminals A to D (80) are arranged on both sides of the ATM network 70. Between the synchronization terminal A and the ATM network 70, the CES I of FIG.
The WF90 is installed and the conventional adaptive clock recovery method is used between the synchronization terminals B to D and the ATM network 70.
ES IWF90 is installed.

A connection for each time slot is established between the synchronous terminal A and the synchronous terminals B, C and D. The connection information for each time slot is set in the MUX / DMUX 50 and CONT01 shown in FIG. In addition, the cell switch 60 has a virtual path identifier (hereinafter referred to as VC) of the ATM cell and a virtual circuit identifier (hereinafter, referred to as VC).
VP for switching to the destination route)
A switching table to convert to VC is implemented,
The switching information corresponding to the ATM connection drawn by the dotted line shown in FIG. 5 is set.

In FIG. 5, the transmission (ATM) data of the synchronous terminals B, C and D is CLAD4R1, 4R of FIG.
Input to 2 and 4R3. Next, CLAD4R1, 4
Converted to synchronous terminal data by R2 and 4R3, and B each
It is stored in the UFFs 21, 22 and 23. The accumulated synchronous terminal data is read out by the RDs 31, 32, and 33 according to the read frequency output from the CONT01, and is multiplexed in the MUX / DMUX unit 50 with the data adapted to the synchronous terminal interface. Handed over to the system terminal.

FIGS. 6 and 7 show BUFFs 21, 22, 23.
3 shows the control operation of the read frequency for operating the RDs 31, 32, and 33 when reading data from, using quantitative numerical values. First, in FIG. 6, each B
For UFF21 to 23, Pf1,
Pf2 and Pf3 are calculated. In this case, since Pf1 is the maximum, f1 is corrected to f1 ′ as follows. In this case, CD1 of BUFF21 is larger than TD1, so f
1 '> f1.

Next, referring to FIG. 7, f2 'and f2' are corrected by the above equation (2) using f1 'and f2',
Find f3 '. That is, f2 ′ = f1 ′ × (6/2) = f1 ′ × 3 f3 ′ = f1 ′ × (12/2) = f1 ′ × 6. In this case, CD2, CD of BUFF22, 23
3 is larger than TD2 and TD3, respectively, so f2 '<
f2 and f3 ′ <f3.

Since the above-mentioned processing results in the state,
Then, the same processes as the above are performed.

As described above, in the present embodiment,
When connecting synchronous terminals via an ATM network, the data structure between the synchronous terminals is recognized, ATM cell data is transferred by each time slot by the adaptive clock recovery method, and synchronization is performed in the destination synchronous method. Reassemble to system terminal data. Specifically, multiplexing / conversion for converting synchronous terminal data and data for one or more time slots
A separating unit (50 in FIG. 1) and a cell assembling / disassembling unit (4S1 and 4S1 in FIG. 1) for converting synchronous terminal data and ATM cells.
S2 ..., 4SN, 4R1, 4R2 ..., 4SR) and AT
A cell switch (60 in FIG. 1) that switches M cells to the destination route, a data buffer (2N in FIG. 1) that absorbs delay fluctuations of received synchronous terminal data, and a read that reads synchronous terminal data from the data buffer. Gates (31, 32, ... 3N in FIG. 1) and pointers (M1, M2, ... In FIG. 1) for detecting the data accumulated value of the data buffer.
MN) and a control unit (01 in FIG. 1) that controls the cycle in which the read gate reads data from the accumulated value transmitted from the pointer.

With the above-mentioned configuration, 1
The data converted into ATM cells for every one or more time slots is reproduced as the synchronous terminal data through the ATM network by the synchronous control method on the destination side. Since a connection for each time slot is established between synchronous terminals,
When there is an empty time slot in the data frame of the synchronous terminal on the receiving side, the data from the synchronous terminal on the other path can be accommodated. Further, it becomes possible to establish a plurality of paths between the same synchronous terminals.

[0032]

As described above, according to the present invention,
Since a connection for each time slot is established between the synchronous terminals, if there is a free time slot in the data frame of the receiving synchronous terminal, the data from the other synchronous terminal can be accommodated. Further, it is possible to obtain the effect that a plurality of paths can be established between the same synchronous terminals.

Further, since a device having the function of the conventional adaptive clock recovery method can be accommodated,
The network can be expanded without wasting existing devices.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronization control device according to the present invention.

FIG. 2 is a block diagram of the inside of CONT of FIG.

FIG. 3 is a flowchart showing CONT control.

FIG. 4 is a block diagram showing a synchronization control device when N = 3 in FIG.

5 is a block diagram showing an embodiment of an ATM network configuration using the synchronization control device of FIG.

6 is a configuration diagram quantitatively showing a control operation of data reading in the BUFF in FIG.

7 is a configuration diagram quantitatively showing a control operation of data reading in the BUFF in FIG.

FIG. 8 is a block diagram of an ATM network system using a conventional adaptive clock recovery method.

FIG. 9 is a block diagram illustrating an operation of a conventional adaptive clock recovery method.

[Explanation of symbols]

 01 CONT (control unit) 02 PfN calculation unit 03 Storage unit 04 Frequency correction unit MN monitor function 2N BUFF (buffer) 3N RD (gate) 4SN, 4RN CLAD 05N Frequency generation unit 50 MUX / DMUX 70 ATM network 80 Synchronization system terminal 90 CES IWF (Synchronous controller)

Claims (3)

[Claims] 1. A conversion means for converting a plurality of ATM cell data received from an ATM network into synchronous terminal data for each predetermined time slot, and a plurality of converted synchronous terminal data. A plurality of memory means each of which has a predetermined capacity and is set with a target value of a data amount to be accommodated; a plurality of read means for reading the plurality of memory means at respective read frequencies; Multiplexing means for multiplexing each synchronous terminal data and transmitting it to the synchronous terminal, detecting means for detecting the data amount of each of the plurality of memory means, and a plurality of detection values of the detecting means respectively corresponding targets. Selecting means for preferentially selecting one reading means based on a value and a capacity; and a memory corresponding to the selected reading means Correction means for correcting the read frequency so that the data amount of the means becomes the target value, and the corrected read frequency is used as a reference frequency, and the number of time slots of data read at this reference frequency and other memory means A synchronization control device comprising: a correction unit that corrects the read frequency of the other read unit based on the ratio of the read data to the number of time slots. 2. A transmission means is provided for converting synchronous terminal data sent from the synchronous terminal into ATM cells and transmitting the ATM cells to the ATM network.
The synchronous control device described. 3. A synchronous terminal is connected via an ATM network, and transmitting side synchronous terminal data is converted into an ATM cell for each time slot connection between synchronous terminals, and is provided for each time slot connection on the receiving side. In the synchronous control method of reproducing the read frequency of each data buffer from each data accumulated value in a plurality of data buffers by using the adaptive clock recovery method, the above-mentioned data accumulated value, accumulated target value and data buffer capacity in each data buffer From this, the correction frequency correction priority is calculated, and the read frequency of the data buffer with the highest priority is corrected using the above adaptive clock recovery method,
Further, based on the corrected read frequency, the ratio of the number of time slots of data read at the corrected read frequency to the number of time slots of data read at the read frequency of another data buffer After correcting the read frequency of the, the synchronous terminal data for each time slot read from each data buffer is multiplexed and shaped into the data format corresponding to the receiving side synchronous terminal, the receiving side synchronous terminal A synchronous control method characterized by passing.