JPH09321553A - Deferential input circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To amplify an input voltage with small amplitude in a short time by decreasing a rise time of an output voltage or its fall time. SOLUTION: In this differential input circuit, 1st stage two differential circuits 1, 2 generate 1st and 2nd differential amplifier voltages V1 , V2 inverted to each other, and a 2nd stage differential circuit 3 used them alternately to amplify an input voltage Vin . In this case, NMOS transistors N6, N7 acting like a clamp circuit are produced between the 1st stage two differential circuits 1, 2 and the 2nd stage differential circuit 3 so as to limit the level of the 1st and 2nd differential amplifier voltage V1 , V2 to a prescribed level or below. For example, when the differential amplifier voltage V1 descends in response to the fall time of the input voltage Vin , the fall time is decreased to smoothly switch the 1st differential amplifier voltage V1 into the 2nd differential amplifier voltage V2 .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential input circuit, and is suitable for use in an interface portion such as SSTL-3 used in an IC circuit.

[0002]

2. Description of the Related Art In recent years, CPUs used in computers and the like
The performance of the above is dramatically improved, and there is also provided one that operates at a high frequency exceeding 100 MHz. In order to raise the operating frequency in this way, the amplitude of the signal voltage has become very small, for example, about 0.4V. Therefore, in an IC circuit that requires an operating voltage of around 3V,
A small-amplitude input voltage supplied from a system bus or the like needs to be amplified to a predetermined level, and a differential input circuit is used for that purpose.

FIG. 7 is a diagram showing a configuration example of a conventional differential input circuit. In FIG. 7, the NMOS transistor N
₁₁ and N ₁₂ have the same characteristics. A small amplitude input voltage V _in is input to the gate terminal of the NMOS transistor N ₁₁ , and a reference voltage V _ref is input to the gate terminal of the NMOS transistor N ₁₂ . The source terminals of the NMOS transistors N ₁₁ and N ₁₂ are grounded.

The drain terminals of the NMOS transistors N ₁₁ and N ₁₂ are respectively connected to the PMOS transistors P ₁₁ and
Is connected to the drain terminal of the P _12, the power supply voltage Vdd is supplied to the source terminal of the PMOS transistor P _11, P _12. The drain terminal of the NMOS transistor N ₁₁ is also connected to the gate terminals of the PMOS transistors P ₁₁ and P ₁₂ . And the output voltage V
_out is obtained from the drain terminal of the NMOS transistor N ₁₂ .

This differential input circuit is an application of a general differential amplifier circuit. As for the output voltage V _out , a difference voltage between two input voltages (input voltage V _in and reference voltage V _ref ) is amplified. It is obtained by doing. For example, as shown in FIG. 8, consider a case where the reference voltage V _ref is fixed at 1.2 V and a pulsed input voltage V _in (amplitude 0.4 V) such as a clock signal is input from a computer system bus or the like. .

In this case, the output voltage V _out is the reference voltage V
is proportional to the difference between the _ref and the input voltage V _in, but the reference voltage V
_{Since ref} is fixed, as a result, the input voltage V _in
The gain of the output voltage _Vout determines the amplitude of the output voltage _Vout . As described above, the differential input circuit of FIG.
_It is a current mirror type circuit designed to obtain an output voltage V _out proportional to _in .

In a general differential amplifier circuit, each NM
The source terminals of the OS transistors N ₁₁ and N ₁₂ are grounded via a transistor or a constant current source. However, as shown in FIG. 8, one of the two input voltages is fixed and the other only fluctuates. Is not directly operated when a transistor or constant current source is inserted, so it is directly grounded.

In the present situation where the operating speed of the CPU is increased as described above, if the corresponding speed of the IC circuit is not improved accordingly, it will be one-handed. Therefore, the output voltage V obtained by the differential input circuit of FIG.
It is desired that the level of _out reaches as much as 3V, which is the required voltage level of the IC circuit, as quickly as possible.

However, in the conventional differential input circuit shown in FIG. 7, the rising slope of the output voltage V _out is gentle as shown in FIG. 8, and it takes a long time to reach the required voltage level of the IC circuit. It will take. Therefore, the rising slope of the output voltage V _out is made steeper,
It has been desired to be able to reach the required voltage level of an IC circuit in a short time.

FIG. 9 is a diagram showing another configuration example of a conventional differential input circuit. The differential input circuit of FIG. 9 is a two-stage push-pull type using three of the configurations shown in FIG. 7, and the rise time of the output voltage V _out is shortened to some extent as compared with the differential input circuit of FIG. It was made possible. Hereinafter, the configurations shown in FIG. 7 are collectively referred to as a “differential circuit”.

In FIG. 9, the NMO of the first differential circuit 1
Although the S transistor N ₁₁ input voltage V _in is input,
The reference voltage V _ref is input to the corresponding NMOS transistor N ₂₁ of the second differential circuit 2. Further, the reference voltage V is applied to the NMOS transistor N ₁₂ of the first differential circuit 1.
_ref is input, but the second differential circuit 2 corresponding to this is input
The input voltage V _in is input to the NMOS transistor N ₂₂ .

That is, the first and second differential circuits 1 and 2 are symmetrically connected to each other with respect to the input voltage V _in and the reference voltage V _ref . Therefore, N of the first differential circuit 1
The first differential voltage V ₁ output from the drain terminal of the MOS transistor N ₁₂ and the second differential voltage V ₂ output from the drain terminal of the NMOS transistor N ₂₂ of the second differential circuit 2 are , And the signals have opposite phases.

The first differential voltage V ₁ is input to the gate terminal of the NMOS transistor N ₃₂ of the third differential circuit 3, and the second differential voltage V ₁ has the opposite phase to the _first differential voltage V _1. The dynamic voltage V ₂ is applied to the NMOS transistor N _{31 of the} third differential circuit 3.
Input to the gate terminal of. The third differential circuit 3 alternately takes out the first differential voltage V _{1 and} the second differential voltage V ₂ , and a difference voltage between them and the reference voltage V _ref is amplified and output. The voltage V _out can be obtained (see FIG. 10).

Since the first and second differential voltages V ₁ and V ₂ input to the respective NMOS transistors N ₃₁ and N ₃₂ of the third differential circuit 3 are not fixed ones, they are normal. Similar to the differential amplifier circuit, each NMOS transistor N ₃₁ , N ₃₂
It is possible to ground the source terminal of the device via a transistor or a constant current source. In the example of FIG. 9, it is grounded through the NMOS transistor N ₅ .

In the case of this example, the NMOS transistors N ₁₁ , N ₁₂ , N ₂₁ , of the first and second differential circuits 1 and 2 are
The source terminal of N ₂₂ can also be grounded via a transistor, a constant current source, or the like, and is grounded via an NMOS transistor N ₄ here.

[0016]

However, when the differential input circuit is constructed as shown in FIG. 9, the rising slope of the output voltage V _out is made a little steep as compared with the case where it is constructed as shown in FIG. I could, but it was still inadequate. That is, the output voltage V _out is obtained by alternately switching between the first differential voltage V ₁ and the second differential voltage V ₂ and amplifying the output voltage V _out. In some cases, the rising time of the output voltage V _out becomes long.

For example, at the time of switching from the _first differential voltage V ₁ to the second differential voltage V ₂ shown at 25 nsec to 26 nsec in FIG. 10, the first differential voltage V ₁ falls and at the same time,
Despite the rise of the second differential voltage V ₂ , the switching is not performed smoothly because the level of the first differential voltage V ₁ is still sufficient. Therefore, the amplification operation is not smoothly performed, and the rise time of the output voltage V _out is long.

In the above description, only the rising portion of the output voltage V _out is focused, but since the falling portion of the pulse signal is used in the clock circuit, the falling time of the output voltage V _out is shortened. It is also desired to do. However, the conventional differential input circuits shown in FIGS. 7 and 9 have a problem that the fall time also becomes long.

The present invention has been made to solve such a problem, and when amplifying an input voltage having a small amplitude, the rise time or fall time of the output voltage is shortened to shorten the time. The purpose is to enable amplification.

[0020]

A differential input circuit of the present invention is a current mirror type first input circuit which inputs an input voltage and a reference voltage, and uses them to generate and output a first differential amplified voltage. No. 1 differential circuit and the same input voltage and the same reference voltage as those input to the first differential circuit are input, and they are used to be in opposite phase with respect to the first differential amplified voltage. Second
Second differential circuit of the current mirror type which generates and outputs the differential amplified voltage of the first differential amplifier and the first and second differential amplifiers of the opposite phases output from the first and second differential circuits. A differential input circuit comprising: a third differential circuit that performs amplification by alternately using a voltage, between the first differential circuit and the third differential circuit, and the third differential circuit. A clamp circuit is provided between the second differential circuit and the third differential circuit so as to prevent the first and second differential amplified voltages from exceeding a predetermined level.

Another feature of the present invention is that the clamp circuit is grounded via an NMOS transistor, and the gate terminal of the NMOS transistor is connected to at least one of the first and second differential circuits. It is characterized in that a voltage for the mirror is inputted.

Another feature of the present invention is that a first differential circuit of a current mirror type, which inputs an input voltage and a reference voltage, generates a differential amplified voltage using them and outputs the differential amplified voltage, Inverter means for generating and outputting a voltage having a phase opposite to that of the differential amplified voltage output from the first differential circuit, and mutually opposite phases output from the first differential circuit and the inverter means. Between the first differential circuit and the second differential circuit, and between the inverter means and the second differential circuit, the second differential circuit performing amplification by alternately using the voltage And a clamp circuit for suppressing the output voltage of the first differential circuit and the output voltage of the inverter means from exceeding a predetermined level.

Another feature of the present invention is that the inverter means inputs PM to a gate terminal of a voltage for the mirror made in the first differential circuit.
An OS transistor and an NMOS transistor for inputting a differential amplified voltage generated in the first differential circuit to its gate terminal are provided, and the PMOS transistor and the drain terminal of the NMOS transistor are connected to each other,
The voltage output from the drain terminal is input to the second differential circuit.

Another feature of the present invention is that the clamp circuit is composed of an NMOS transistor.

According to the present invention configured as described above, the levels of the first and second differential amplification voltages generated based on the input voltage and the reference voltage do not rise above a certain level by the clamp circuit. Thus, when the differential amplified voltage falls in response to a change in the input voltage, it takes a short time to fall to a sufficiently low level. As a result, when one differential amplification voltage rises to a sufficient level, the other differential amplification voltage already falls to a sufficiently low level.
Switching between the first differential amplified voltage and the second differential amplified voltage can be smoothly performed.

According to another feature of the present invention, the clamp circuit inputs the voltage for the mirror in at least one of the first and second differential circuits provided in the first stage to the gate terminal. Since it is grounded via the above-mentioned NMOS transistor, the threshold level of the clamp circuit is variable according to the voltage for the mirror that fluctuates due to variations in the characteristics of the first and second differential circuits, and is always optimal. Clamping will be performed at various threshold levels.

According to another feature of the present invention, the first and second differential amplified voltages having mutually opposite phases are generated by the first differential circuit and the inverter means.
It is possible to simplify the circuit configuration at the first stage.
It is possible to reduce the load when generating the second differential amplified voltage.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the configuration of the differential input circuit according to the first embodiment. In FIG. 1, the same circuit parts as those of the conventional differential input circuit shown in FIG. 9 are designated by the same reference numerals.

The first differential circuit 1 shown in FIG. 1 inputs the input voltage V _in and the reference voltage V _ref to the NMOS transistors N ₁₁ and N ₁₂ , respectively, and uses them to output the first differential voltage. V ₁ is generated and output. As described in the conventional example, the first differential circuit 1 is a current mirror type circuit configured to obtain the first differential voltage V ₁ proportional to the input voltage V _in .

The second differential circuit 2 inputs the same input voltage V _in and the reference voltage V _ref , which are the same as those input to the first differential circuit 1, to the NMOS transistors N ₂₂ and N ₂₁ , respectively. And using them, the first differential voltage V ₁
Is a current mirror type circuit that generates and outputs a _second differential voltage V ₂ that is in anti-phase with respect to.

The third differential circuit 3 outputs the first and second differential circuits 1 and 2 having opposite phases to each other.
The differential voltages V ₁ and V ₂ are input to the NMOS transistors N ₃₂ and N ₃₁ , respectively, and they are alternately used for amplification to generate and output the output voltage V _out .

In the present embodiment, in addition to the above configuration, between the first differential circuit 1 and the third differential circuit 3 and between the second differential circuit 2 and the third differential circuit. Between the first differential voltage V ₁ and the second differential voltage V ₁ .
A clamp circuit is provided to prevent ₂ from exceeding the specified level.

In the example of FIG. 1, as a clamp circuit for preventing the first differential voltage V ₁ generated by the first differential circuit 1 from becoming larger than the first threshold value V _th1 , The NMOS transistor N ₆ is provided in parallel between the first differential circuit 1 and the third differential circuit 3.

Further, the second differential voltage V ₂ generated by the second differential circuit ₂ is the second threshold value V
_An NMOS transistor N ₇ is provided in parallel between the second differential circuit 2 and the third differential circuit 3 as a clamp circuit for preventing the voltage from becoming larger than _th2 .

The gate terminals and drain terminals of the NMOS transistors N ₆ and N ₇ as the clamp circuit are connected to each other, and the drain terminals are connected to the differential voltage output terminals (NMOS transistors N ₁₂ , Drain terminal of N ₂₂ ). The source terminals are both grounded.

When the clamp circuit is provided in this way, FIG.
As shown in, for example, if the first level of the differential voltages V ₁ generated by the first differential circuit 1 began to increase in proportion to the input voltage V _in, the first threshold value V _th1
After reaching, the voltage level is controlled so that it does not rise further. That is, the voltage level of the first differential voltage V ₁ is maintained at the first threshold value V _th1 .

After that, when the input voltage V _in falls, the first differential voltage V ₁ also falls accordingly, but the level of the first differential voltage V ₁ at the time of the fall of the input voltage V _in Is much smaller than that in the conventional case shown in FIG. 10, so that the time t required for the first differential voltage V ₁ to be turned off with respect to the reference voltage V _ref is significantly shorter than in the conventional case. . Therefore, at the time when the second differential voltage V ₂ rises and is turned on, the first differential voltage V ₁ is already off, and the first differential voltage V ₁ to the second differential voltage V ₁ Switching to V ₂ will be performed smoothly.

Similarly, at the time of switching from the _second differential voltage V ₂ to the first differential voltage V ₁ , the second differential voltage V ₁ becomes the second voltage when the first differential voltage V ₁ rises and turns on. the differential voltage V ₂ is already turned off, so that switching from the second differential voltage V ₂ to the first differential voltages V ₁ can be performed smoothly.

As described above, in this embodiment, 2
By setting the threshold values V _th1 and V _th2 of the two clamp circuits to appropriate values (preferably values around the amplitude level of the input voltage V _in ), the first differential voltage V ₁ and the second differential voltage are set. Switching to the voltage V ₂ can be performed smoothly, and the rise time of the output voltage V _out can be shortened as compared with the conventional case.

When the output voltage V _out is supplied to the IC circuit which operates in response to the falling edge, the falling portion is more important than the rising portion of the output voltage V _out . Therefore, in this case, the output voltage V
_If the fall time of _out can be made as short as possible, the rise time does not have to be so short.

In the present embodiment, the clamp voltage (first and second threshold values V _th1 and V _{th 2} ) is appropriately adjusted to shorten the rise time or fall time of the output voltage V _out. It can be shortened or shortened freely. Then, such adjustment can be realized by changing the gate widths of the NMOS transistors N ₆ and N ₇ as the clamp circuit.

That is, the NMOS transistors N ₆ and N
_Increasing the gate width of ₇ results in clamping from a lower voltage, and decreasing the gate width results in clamping from a higher voltage. As described above, the present embodiment also has an advantage that by changing the gate widths of the NMOS transistors N ₆ and N ₇ , it is possible to easily perform the fine adjustment from which voltage level the clamping is performed.

However, in the first embodiment, the first and second
The threshold values V _th1 and V _th2 that determine the upper limits of the differential voltages V ₁ and V ₂ are fixed, and if they remain fixed, the following inconvenience may occur. That is, C that constitutes the first differential circuit 1 and the second differential circuit 2 of the first stage
When manufacturing a MOS transistor, variations in characteristics may occur, or variations in the power supply voltage Vdd may occur. Further, the reference voltage V _ref supplied from the outside such as the computer system bus may fluctuate. Such variations and fluctuations are caused by the voltage for the mirror made from the reference voltage V _ref (hereinafter, mirror voltage V _mi
Called)) influences the size.

In such a case, the threshold value V
_th1, Leaving the V _th2 to the fixed, would be the first differential voltages V ₁ and second differential voltage V ₂ where not appropriate is clamped, the first differential voltages V ₁ and the second difference Dynamic voltage V ₂
Switching between and may not be performed smoothly. Therefore, it is desirable that the level of the clamp voltage also fluctuates with the fluctuation of the mirror voltage V _mi in the first differential circuit 1 and the second differential circuit 2.

The differential input circuit according to the second embodiment of the present invention described below is designed to satisfy such requirements, and FIG. 3 shows an example of the configuration. 3, differs from the first embodiment shown in FIG. 1, the NMOS transistor N _6, N ₇ of the clamping circuit is grounded through the NMOS transistor N _8, the gate terminal of the NMOS transistor N ₈ That is, the mirror voltage V _{mi generated} from the reference voltage V _ref is input to the second differential circuit 2.

That is, NM as the clamp circuit
The source terminals of the OS transistors N ₆ and N ₇ are both NM
NM connected to the drain terminal of the OS transistor N _8.
The source terminal of the OS transistor N ₈ is grounded.
Further, the gate terminal of the NMOS transistor N ₈ has a second
Of the differential circuit 2 is connected to the drain terminal of the NMOS transistor N ₂₁ .

With this configuration, the second differential circuit 2
When the mirror voltage V _mi of increases, the drain voltage of the NMOS transistor N _8, i.e. N as clamping circuit
Since the source voltages of the MOS transistors N ₆ and N ₇ also become high, the clamp voltage is lowered. Also, the second
When the mirror voltage V _mi of the differential circuit 2 becomes low, the source voltages of the NMOS transistors N ₆ and N ₇ as the clamp circuit also become low, so that the clamp voltage is increased.

Therefore, in the second differential circuit 2, C
Variations in MOS transistor characteristics and power supply voltage Vdd
4 or the reference voltage V _ref fluctuates, the clamp voltages of the NMOS transistors N ₆ and N ₇ have threshold values V _th1 ′ and V _th2 ′ shown in FIG. fluctuate. As a result, the clamp operation is always performed under an appropriate threshold value, and the rise time or the rise time of the output voltage V _out is not affected by the variation of the first stage differential circuit as described above. The fall time can always be shortened.

Although the mirror voltage V _mi of the second differential circuit 2 is input to the gate terminal of the NMOS transistor N _{8 in} the embodiment of FIG. 3, the mirror voltage of the first differential circuit 1 is changed. The voltage V _mi may be input to the gate terminal of the NMOS transistor N ₈ .

FIG. 5 is a diagram showing the configuration of a differential input circuit according to the third embodiment of the present invention. In FIG. 5, FIG.
The difference from the first embodiment shown in FIG. 9 is that a PMOS transistor P ₉₁ and an NMOS transistor N ₉₂ are provided instead of the first differential circuit 1 in the first stage. The mirror voltage V _{mi generated} from the reference voltage V _ref in the second differential circuit 2 is input to the gate terminal of the PMOS transistor P ₉₁ , and the power supply voltage Vdd is input to the source terminal thereof. .

The NMOS transistor N ₉₂ has its gate terminal to which the second differential voltage V ₂ generated from the input voltage V _{in in} the second differential circuit ₂ is input, and the source The terminal is grounded via the NMOS transistor N ₄ . Further, the drain terminals of the PMOS transistor P ₉₁ and the NMOS transistor N ₉₂ are connected to each other.

With this configuration, the PMOS
The transistor P ₉₁ and the NMOS transistor N ₉₂ are
The second differential circuit 2 functions as an inverter circuit that generates a voltage having a phase opposite to that of the second differential voltage V ₂ output from the second differential circuit 2. Therefore, the voltage output from the drain terminals of the PMOS transistor P ₉₁ and the NMOS transistor N ₉₂ has a phase opposite to that of the second differential voltage V _2, and the first differential voltage shown in FIG. 1 or FIG. It is the same as the voltage V ₁ .

Also in the case of this embodiment, as shown in FIG.
Switching between the first differential voltage V ₁ and the second differential voltage V ₂ can be smoothly performed, and the output voltage V 1
The rise time or fall time of _out can be made shorter than before.

In the first and second embodiments shown in FIGS. 1 and 3, a differential circuit composed of a large number of CMOS transistors in order to obtain differential voltages V ₁ and V ₂ having mutually opposite phases. Since two are provided, the load is heavy. However, if a too large load is applied, the output waveform is delayed with respect to the input waveform, making it difficult to speed up the amplification operation.

On the other hand, in the third embodiment, the differential voltages V ₁ and V ₂ having opposite phases can be generated with a simple structure, and the load can be reduced. This allows
The delay of the output waveform with respect to the input waveform can be reduced, and the amplification operation can be made even faster.

In the example of FIG. 5, a PMOS transistor P ₉₁ and an NMOS transistor N ₉₂ are provided instead of the first differential circuit 1 shown in FIGS. 1 and 3, and the second differential circuit 2 is provided. Based on the generated second differential voltage V ₂ , a first differential voltage V ₁ having a phase opposite to that of the second differential voltage V ₁ is generated, but conversely, instead of the second differential circuit 2, a PMOS is used. A transistor P ₉₁ and an NMOS transistor N ₉₂ are provided, and the first
The first differential voltage V ₁ generated by the differential circuit 1 may be used to generate the second differential voltage V ₂ having a phase opposite to that of the first differential voltage V ₁ .

Also in this embodiment, as shown in FIG. 3, the NMOS transistor N ₆ , serving as a clamp circuit,
N ₇ may be grounded via the NMOS transistor N ₈ . In the present embodiment, as compared with the differential input circuit of FIG. 1 and FIG. 3, the symmetry of the circuit is lost, the operation of the first-stage portion for generating a differential voltage V _1, V ₂ of the opposite phase However, there is a possibility that it becomes unstable as compared with the case of FIGS. Therefore, it can be said that the significance of providing the NMOS transistor N ₈ in the present embodiment is greater than that in the first and second embodiments.

In the above first to third embodiments, the CMOS transistor is used as an example of the clamp circuit.
The present invention is not limited to this as long as it performs a clamp operation, and can be applied. For example, it is possible to use a bipolar diode or a Zener diode instead of the CMOS transistor.

[0059]

As described above, according to the present invention, the three differential circuits are connected in a push-pull type, and the first and second differential amplifiers having opposite phases in the two differential circuits in the first stage. In a differential input circuit that generates a voltage and amplifies a small-amplitude input voltage by alternately using the differential amplified voltages in the second-stage differential circuit, A clamp circuit for suppressing the above first and second differential amplified voltages from exceeding a predetermined level is provided between the differential circuit of the second stage and the differential circuit according to the change of the input voltage. The fall start voltage level when the amplified voltage falls decreases, and the time required to fall from there to a sufficiently low level can be shortened. As a result, the switching between the first differential amplified voltage and the second differential amplified voltage can be smoothly performed, and the rise time or fall time of the output voltage can be made much shorter than in the past. Amplification can be performed in a short time.

According to another feature of the present invention, the clamp circuit is grounded via an NMOS transistor,
Since the voltage for the mirror in at least one of the first and second differential circuits provided in the first stage is input to the gate terminal of the transistor, the first and second differential circuits are provided.
It is possible to change the threshold level of the clamp circuit according to the variation in the characteristics of the differential circuit, and by performing the clamp processing at the optimum threshold level at all times, it is possible to reduce the variation in the first stage differential circuit. The rise time and fall time of the output voltage can be always shortened without being affected.

According to another feature of the present invention, the first and second differential amplified voltages having opposite phases are generated by the first differential circuit and the inverter means.
It is possible to simplify the circuit configuration at the first stage.
The load when generating the second differential amplified voltage can be reduced. Thereby, the delay of the output waveform with respect to the input waveform can be reduced, and the amplification operation can be further speeded up.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a differential input circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the differential input circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a differential input circuit according to a second embodiment of the present invention.

FIG. 4 is a waveform diagram for explaining the operation of the differential input circuit according to the second embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a differential input circuit according to a third embodiment of the present invention.

FIG. 6 is a waveform diagram for explaining the operation of the differential input circuit according to the third embodiment of the present invention.

FIG. 7 is a diagram showing a configuration example of a conventional differential input circuit.

8 is a waveform diagram for explaining the operation of the conventional differential input circuit shown in FIG.

FIG. 9 is a diagram showing another configuration example of a conventional differential input circuit.

10 is a waveform chart for explaining the operation of the conventional differential input circuit shown in FIG.

[Explanation of symbols]

N _6, N ₇ clamp circuit (NMOS transistor) N ₈ NMOS transistors P ₉₁ PMOS transistor N ₉₂ NMOS transistor

Claims (6)

[Claims] 1. A current mirror type first differential circuit for inputting an input voltage and a reference voltage, and using the input voltage and a reference voltage to generate and output a first differential amplified voltage, and the first differential circuit. Input the same input voltage and reference voltage that are input to the circuit,
A second differential circuit of a current mirror type that uses them to generate and output a second differential amplified voltage having a phase opposite to that of the first differential amplified voltage, and the first and second differential circuits. A differential input circuit comprising: a third differential circuit that performs amplification by alternately using first and second differential amplified voltages of opposite phases output from the differential circuit of Between the first differential circuit and the third differential circuit, and between the second differential circuit and the third differential circuit,
A differential input circuit comprising a clamp circuit for suppressing the first and second differential amplified voltages from exceeding a predetermined level. 2. The clamp circuit is grounded via an NMOS transistor, and a gate terminal of the NMOS transistor is supplied with a voltage for a mirror in at least one of the first and second differential circuits. The differential input circuit according to claim 1, wherein: 3. A current mirror type first differential circuit which inputs an input voltage and a reference voltage, generates a differential amplified voltage using them and outputs the differential amplified voltage, and outputs from said first differential circuit. Inverter means for generating a voltage having a phase opposite to that of the differential amplified voltage generated and outputting the voltage and amplifying the voltage having mutually opposite phases outputted from the first differential circuit and the inverter means alternately. Is provided between the first differential circuit and the second differential circuit, and between the inverter means and the second differential circuit. 1. A differential input circuit comprising: a clamp circuit for suppressing the output voltage of the differential circuit 1 and the output voltage of the inverter means from exceeding a predetermined level. 4. The inverter means includes a PMOS transistor for inputting a voltage for a mirror made in the first differential circuit to a gate terminal, and a differential amplifier made in the first differential circuit. An NMOS transistor for inputting a voltage to a gate terminal is provided, the drain terminals of the PMOS transistor and the NMOS transistor are connected to each other, and the voltage output from the drain terminal is input to the second differential circuit. The differential input circuit according to claim 3, wherein: 5. The clamp circuit is grounded via an NMOS transistor, and a voltage for the mirror made in the first differential circuit is input to the gate terminal of the NMOS transistor. The differential input circuit according to claim 3 or 4. 6. The differential input circuit according to claim 1, wherein the clamp circuit is composed of an NMOS transistor.