JPH09319722A - Parallel compiling method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To fast run a compiled object program by extracting correctly the reduction, i.e., a loop pattern that frequently appears in a source program out of this source program. SOLUTION: The reduction is detected out of a loop (Step 21) and then converted into a loop that can be carried out effectively and in parallel (Step 22). Finally, the reduction communication is generated based on the converted loop and optimized (Step 23). The detection of reduction consists of three sub- steps. That is, a model is first produced in regard to the mask expression masking every substitute sentence in the loop. In other words, an expression tree concerning the execution condition of every substitute sentence is generated. Then it's decided whether the reduction consists of an expression tree of merged substitute sentences based on the expression tree of a prescribed conditional expression and also the data dependence relation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compiler for a parallel computer, and more particularly to detection of reduction in a source program and its processing.

[0002]

2. Description of the Related Art In recent years, parallel computers having a plurality of processors have been put into practical use. This computer realizes high processing capability by operating the respective processors at the same time. As shown in FIG. 1, the parallel computer has a plurality of processor elements including a processor, a local memory, and a data transfer device, and each processor element is connected via a bus. C language and FORTR
In order to efficiently execute a source program written in a high-level language such as AN on a parallel computer, a parallelizing compiler that translates the source program into a target program for the parallel computer is required. The important role of this parallelizing compiler is to be able to accurately detect the parallel executable description in the source program and to efficiently distribute this execution to the respective processor elements.

By the way, reduction is one of the frequently appearing syntaxes in a numerical calculation program or the like. The reduction is an operator that satisfies the exchange law and the associative law, and is an operation that obtains a single result from certain array data based on the same kind of operators. For example, the operation of obtaining the maximum value, the minimum value, or the index value from a large number of array data is a typical reduction operation. Here, the operator that satisfies the exchange law and the associative law means "+", "*", "max", "min", or the like. Further, since they are operators of the same kind, operations including different operators are not reductions, but operations that are composed of only the same operator, for example, the operator “+”.

Reduction is a computational loop that is executed serially when it is executed on a single processor. However, in a parallel computer, it is a description that can be executed in parallel. Therefore, when reduction can be detected, first, local calculation is performed for each processor element based on the array data stored in its own local memory. These local results are then transferred to a processor element, which aggregates these local results into the final result. Finally, the determined final result is transferred again to the respective processor element in order to guarantee the identity of the data stored in the respective processor element. As described above, the execution time is significantly shorter when the distributed processing is performed for each processor element than when the reduction calculation is sequentially executed. Therefore, it is very important for the parallelizing compiler to correctly detect the reduction syntax in the source program in order to generate the target program that the parallel computer can execute at high speed.

Conventionally, this reduction is based on the idiom
It was detected by recognition. The idiom recognition is a pattern matching method, that is, a method of checking whether a certain description in a source program matches a preliminarily assumed pattern and detecting it as a reduction only when it matches. This pattern is expressed by a specific assignment statement, a loop, and a conditional statement in the loop. If a loop existing in the actual source program is recognized by this idiom recognition as, for example, a reduction for obtaining the maximum value of array data, the parallelizing compiler executes the loop in parallel for obtaining the maximum value. Convert to a call to a runtime routine that shows the procedure of. Then, at run time, this reduction is executed in parallel based on this routine.

In idiom recognition, which is a conventional method, only a pattern that exactly matches a pattern assumed by a parallelizing compiler developer as a general expression frequently used in a program is detected as a reduction. . Therefore, if the expression of the reduction is slightly different from the expected pattern, this expression is not detected as the reduction. However, the reductions that exist in actual programs are often expressed by complexly entangled conditional expressions in the loop, and there are also many variations. Therefore, in the conventional method, it is not possible to recognize a reduction having a complicated expression other than the assumed pattern, although it is essentially a reduction.

[0007]

As described above, in the parallelizing compiler using the conventional reduction detection method,
The reduction could not be detected effectively at compile time. Therefore, there is a case where an operation which is originally capable of parallel execution is generated as a target program to be sequentially executed without being compiled as such. Therefore, it has been difficult for the parallel computer to efficiently execute this operation.

[0008] Therefore, an object of the present invention is to provide a parallelizing compiler capable of generating a target program that can be efficiently executed in parallel.

Another object of the present invention is to correctly detect a reduction expression in a source program.

Still another object of the present invention is to effectively reduce the execution time of the reduction thus detected.

[0011]

In view of the above problems, the first invention is a parallel compiling method for translating a source program to generate an object program for a parallel computer having a plurality of processors. The step of analyzing the structure of the conditional expression that masks the assignment statement existing in the loop inside, the step of analyzing the structure of this assignment statement, the step of merging the structure of the assignment statement from the data dependency of variables, and the condition And detecting the reduction by referring to the data dependency of the variable and the operator in the assignment statement based on the structure of the expression and the structure of the merged assignment statement.

The step of detecting the reduction is
Depending on the state of the expression on the right side of the assignment statement, it is divided into the following cases. First, when the expression on the right side of the assignment statement is an expression, the data dependency of the recurrence variable among the variables is referenced, and the assignment statement is an operator that satisfies the exchange law and the associative law, and the same kind of operation Determine reduction by referring to being a child. If the expression on the right side of the assignment statement is a single variable, reduction is determined based on the structure of the conditional statement.

In order to analyze the structure of the conditional expression, an expression tree in which each conditional expression is associated with a node and each assignment statement is associated with a leaf is generated. Based on the model of the conditional expression, the compiler analyzes whether the structure of the entire loop can constitute the reduction.

In order to analyze the structure of the assignment statement, each element (eg, variable, operator, etc.) that constitutes the assignment statement
An expression tree corresponding to a node is generated for each leaf of the expression tree showing the structure of the conditional expression existing in the loop. Based on the model of the assignment statement, the compiler analyzes whether the structure of the assignment statement can constitute reduction.

A second aspect of the present invention is a parallelized compiling method for translating a source program to generate an object program for a parallel computer having a plurality of processor elements, and detecting a reduction controlled by a certain reduction variable. To convert the reduction variable to a private variable for each processor, in order to calculate the intermediate intermediate results in parallel for each processor, and for aggregating the local results calculated in parallel for each processor And a step of generating reduction communication.

The step of generating the reduction communication according to the second aspect of the present invention includes the step of summing up local results relating to the plurality of reductions calculated by the respective processors when there are a plurality of reductions in a single loop. , The local results regarding a plurality of reductions may be vectorized and communicated.

A third aspect of the present invention provides a storage medium storing a compile program using the parallelizing compile method having the above configuration.

Further, a fourth invention provides a parallel computer which executes an object program compiled by the parallelizing compilation method having the above-mentioned generation.

[0019]

In the reduction, it is necessary to analyze this structure because the assignment statement itself has structural characteristics. However, it is also necessary to analyze what kind of data dependency the variable of the assignment statement has with other assignment statements. According to the first aspect of the present invention, it is determined whether or not reduction is performed by grasping the relation between the conditional expressions in the loop and grasping the relation between the assignment statements. Since the structure of the assignment statement is merged while paying attention to the data dependency, it is possible to generate a structural model that does not depend on the expression of the assignment statement.

In the second aspect of the invention, the reduction variable is replaced with a private variable local to each processor, paying attention to the fact that the reduction can be originally executed in parallel.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below. The parallelizing compiler in this embodiment is intended for a system having a local memory for each processor element as shown in FIG. The purpose of this compiler is to generate a target program that can be efficiently executed on such a system.

FIG. 2 is a diagram showing a basic operation flow from reduction detection to optimization of reduction communication of the parallelizing compiler in this embodiment. First, reduction is detected in the loop (step 21). Next, the detected reduction is converted into a loop that can be efficiently executed in parallel (step 22). Finally, a reduction communication based on this conversion is generated and optimized (step 23).

In the following description, the process from detection of reduction to optimization of communication will be described using the following sample programs as appropriate. This program finds the minimum absolute value of the array rxm.

[Equation 1] do 200 j = 1, m do 200 i = 1, n if (mod (i, 2) = 1) then sum = sum + rm (i, j) ・ ・ ・ ・ ・ ・ (a) if ((abs (rx (i, j)) <abs (rxm)) .and. (mod (j, 2) = 1)) then rxm = rx (i, j) ・ ・ ・ ・ ・ ・ (b) irxm = i ・ ・ ・ ・ ・ ・ (c) sum = sum + rx (i, j) ・ ・ ・ ・ ・ ・ (d) endif endif 200 continue

Reduction Detection (Step 21) Reduction detection is made up of three sub steps, as shown in FIG. First, create a model for the mask expression that masks each assignment statement in the loop. That is, for each assignment statement, an expression tree relating to the condition for executing it is generated (step 3
1).

Here, the mask expression refers to a condition that is a prerequisite for executing a certain assignment statement, such as a conditional statement such as an if statement. The node of this expression tree is expressed by each term of the logical product. In the expression tree generation, if, elseif, els
Each time you traverse each control statement such as "e",
Create new nodes.

FIG. 4 is a diagram showing the relationship between the assignment statement of the loop body and the expression tree of the conditional expression generated from this. Each node of the expression tree corresponds to a conditional expression (for example, condition C1 and its negation C1) as a mask expression, and each leaf of the expression tree corresponds to an assignment statement (S1, S2, etc.). When the expression tree is traversed from the root (C1 or ^ C1) to a leaf, the product of the conditional expressions of the intermediate nodes becomes a mask expression that binds the execution of each assignment statement of the leaf. For example, leaves {S2,
The mask expression for S3} is as follows.

[Equation 2] C1 and ^ C2 and C3

With respect to the above sample program, if an expression tree of conditional expressions is generated based on such rules, FIG.
become that way.

Next, the expression tree of the assignment statement in the loop is generated (step 32). For each leaf of the mask expression expression tree generated in step 31, an expression tree of an assignment statement corresponding to the leaf is generated. In the expression tree of the assignment statement, the node is associated with each element forming the assignment statement.

Here, the elements of the assignment statement refer to variables, operators, etc. that form the assignment statement. For example, s = s * a (i)
In the assignment statement, "s", "s", "*",
“A (i)” is an element of the assignment statement. For example, FIG.
The expression tree of the assignment statement of the program shown in FIG.
It becomes like (b). The conditional expression C, which is a mask of the assignment statements S ₁ and S ₂ , is used as the root of the expression, and each node is associated with an element of the assignment statement.

With respect to the above sample program, the expression tree of the assignment statement is created based on such a rule as shown in FIG.

The expression trees of the assignment statement obtained in step 32 are merged on the basis of the data dependence of the variables (step 33). In the example of FIG. 6, the variable s with respect to the two assignment statements S ₁ and S ₂ has a data dependency relationship of true (from def to use) such as arrows δ ₀ and δ ₁ shown by dotted lines in FIG. 6B. are doing. Therefore, this data dependence graph forms a strongly connected graph as shown in FIG.

Such a data dependency is called a strongly connected component,
This is the unit for detecting reduction. If each assignment statement forming the strongly connected component shares the same conditional expression tree node, the loop-independent data dependency (arrow of δ _{0 in} FIG. 5B) is deleted. Merge expression trees of assignment statements. Thus, FIG.
The expression trees of (b) are merged to obtain the expression tree of FIG. 6 (c). Note that such merge is not performed between assignment statements with different mask expressions. Perform this operation on all assignment statements.

FIG. 8 shows an expression tree showing the data dependency relationship of the assignment statement of the sample program generated under such a rule. Note that in this figure, the assignment statement
Descriptions of (b) and (c) are omitted. As this figure shows, the assignment statements (a), (b), (c), (d) in the sample program
Check the data dependency in the expression tree for (see FIG. 7). Although the assignment statements (a) and (d) form a strongly connected component from the data dependency between them, the expression trees are not merged because they do not share the conditional expression expressions.

What is important here is that the reduction essentially has a data dependency relationship (see FIG. 6 (c)) such that it becomes a strongly connected component between the assignment statements constituting it. . Focusing on this property, this algorithm focuses on the strongly connected components and merges the expression trees of these assignment statements. Since the structure of the assignment statement is merged while paying attention to the data dependency, the reduction can be judged based on the structural model that does not depend on the expression of the assignment statement.

Even if the assignment statement forms a strongly connected component, it cannot be uniformly determined as reduction. Besides that, it is necessary to analyze the entire loop. However, in this step, reduction detection candidates can be generated by finding strongly connected components.

It is judged whether or not reduction is constructed from the expression tree of the assignment statement merged based on the expression tree of the conditional expression and the data dependency (step 34).
That is, it is determined in the above steps whether or not the description that can be a candidate for reduction actually constitutes a reduction. What is important in this judgment is that the data dependence of variables and the description of the operator in the assignment statement are referenced.

This judgment can be divided into the following two cases depending on the state of the right side expression of the data dependence graph. That is, whether the right side in the expression tree of the merged assignment statement is an expression or a single variable reference.

Case A. The right-hand side expression is a single variable reference
When there is no expression, for example, as shown in FIG. 6D , there is a case where the right side of the route (=) is an expression. In this case, reduction is determined when all of the following four requirements are met.

(1) Recurrence variable (recurrenc) of the graph
e valiable) must be on the right side of the graph. Here, the recurrence variable means a reference variable on the right side having a true data dependency in the positive direction from the variable on the left side of the graph. In the example of FIG. 6, the reference variable s which is the tip of the arrow of δ ₁ corresponds.

(2) In the graph, when the node of the recurrence variable (variable s at the arrow tip of δ ₁ ) is traversed from its root (=), all the operators of the nodes in the middle are exchanged. It is necessary for the operator to satisfy the laws of law and associative law and to be closed as an operator of the same kind. Here, the operators that satisfy the exchange law and the associative law are operators such as “+, *, max, min”. Also, since there are operators of the same type, different operators must not exist in intermediate nodes. In FIG. 6D, since the intermediate nodes have different operators “*” and “+”, this requirement is not satisfied. Therefore, it is understood that the expression in FIG. 6A is not reduction.

(3) When the graph G ₀ corresponding to a certain leaf in the expression tree of the conditional expression is a part of the strongly connected component, the condition (2) also applies to the other graph G ₁ belonging to the strongly connected component. It needs to be closed with the same kind of operator obtained in. That is, since the graph G ₀ and the graph G ₁ belong to the same strongly connected component and do not share the node of the expression tree of the logical condition,
If they are not merged in step 33, the same operator must exist in the intermediate nodes of both graphs. When G ₁ exists, a plurality of assignment statements guarded by different conditional expressions constitute reduction.

(4) It is necessary that the node of the above-mentioned recurrence variable has no data dependency relationship with the external node of the strongly connected component of the graph.

Case B. The expression on the right side of the graph is loop invariant
In this case, the node of the expression tree of the corresponding logical conditional expression of the graph is traced to its root, and each logical expression C of the node and the shape of the graph are checked. Specifically, if all of the following six requirements are satisfied, it is judged as reduction. These requirements are for detecting reductions of MAXVAL, MINVAL, MACLOC, and MINLOC expressed by using conditional statements, among the reductions. Therefore, the following requirements are derived from the respective meanings. In other words, z =
For an assignment statement in the form of E, it is examined whether or not there is a conditional statement having a logical expression in the following form.

## EQU00003 ## f (z) relop f (E) where f is an elemental function relop: comparison operator such as <, ≤,>, ≥

(1) For the variable node on the left side of the graph,
There is no data dependency with external nodes.

(2) The logical expression C of the node is not a logical expression connected by "or".

(3) Logical expression C is a logical expression expressed by an inequality sign.

(4) Both sides of the inequality sign of the logical expression C are a reference to a single variable or a term in which the element is subjected to an elemental operation. When an elemental operation is performed, the same operator is applied to both sides. Here, the elementary operation is an operation that returns a scalar result with respect to a scalar argument. For arrays, this operation is applied to each of its array elements. For example, "abs", "sqr
Examples include "t", "sin", and "cos".

(5) The variable (including the index variable) on either side of the inequality sign of the logical expression C is the same as the right side variable of the graph. If the variables do not match, the right side of the assignment statement that is the same as the right side variable of the graph exists by tracing back the data dependence of the variable in the inequality sign of the logical expression C.

(6) The variable (including the index variable) on the other side of the inequality sign of the logical expression C is the same as the left side variable of the graph. Alternatively, by tracing back the data dependence, there is a right side of the assignment statement that is the same as the left side variable of the graph. At this time, by referring to the direction of the inequality sign and whether it was an index variable, "maxval", "minval",
It is judged to be reduction such as "maxloc" or "minloc". Alternatively, if the index variable and the right-hand side variable of the graph are the same in condition (5), there is another graph that shares the same conditional expression and is determined to be “maxval” or “minval” at the node C. To do. In this case, according to this determination, “maxloc” and “minloc” are determined.

It is checked whether the reduction candidates in the sample program actually constitute the reduction. That is, the determination is performed by applying either of the two types of cases to each expression tree. Assignment statement
For the expression tree of (a), the right-hand side expression is not a single variable reference, but the expression form. Therefore, case A applies. In this case, as shown in FIG. 8, when starting from the recurrence variable sum on the right side of the expression tree (a) and tracing to the root (=), the operator of the intermediate node is only “+”. Therefore, it can be seen that the operators are closed by the exchange law and the associative law. Also, the expression
There is an expression tree (d) that does not share the conditional expression node with (a) but belongs to the same strongly connected component. Therefore, this expression tree
It is also necessary to investigate (d). In this case, it can be seen that the operator is closed by the above operator as well. Therefore, the expression tree
It is recognized that (a) and (d) constitute the reduction of the sum.

For the expression tree of the assignment statement (b), case B above applies because the right-hand side expression is a single variable reference. In this case, the node of the conditional expression expression tree is traced back to its root, and C3, C2, and C1 are traversed. C2
Abs (rxm) ≧ abs (rx (i, j for the assignment statement rxm = rx (i, j)
The expression j) shows that the above requirements are satisfied. Therefore, this is recognized as a reduction for finding the value whose absolute value is the minimum for the array vx. Since the variable on the right side of the assignment statement (c) is the index variable of the array variable rx in the conditional expression C2, and there is a reduction for finding the minimum absolute value, this is the index variable at that time. Is recognized as a reduction that seeks.

By the above steps, the above sample
In the loop shown by the program, the assignment statement (b) finds the minimum absolute value for the array rx, the assignment statement (c) finds the loop index at that time, and the assignment statements (a) and (d) find the sum of the arrays rm and rx. Reduction is detected.

Conversion of Reduction into Parallelizable Loop (Step 22) Next, the reduction loop is converted into a parallelizable loop so that it can be executed by a plurality of processors at high speed. Here, the reduction syntax detected in step 21 is generally expressed by an imperfect loop having at least one assignment statement, and the reduction itself does not necessarily form a single reduction loop. Not necessarily. In consideration of such a general expression, it is necessary to determine the conversion procedure of the loop including the reduction in order to efficiently execute the reduction calculation by a plurality of processors. For this purpose, it is necessary to perform communication analysis for each array operand to be reduced.

FIG. 9 is an operation flow chart for loop conversion of reduction. First, reduction communication analysis is performed (step 91). Here, the communication that occurs between the processors is analyzed based on the dependency of the data in the loop and the designation of the method of dividing the data of the array.

Based on this communication analysis (step 91),
It is determined whether communication is necessary and the array operand can be prefetched (step 92).

If the determination in step 91 is "Yes", all reductions that target this array and reductions that have an array as a conditional expression operand of the runtime mask A new loop is generated (step 93). This new loop
At the nesting level of the prefetchable loop, reductions for these operands are included as assignment statements. This loop is a loop that executes a local calculation for each processor by making all the reduction variables private, that is, by making them private, so that parallel execution is possible.
This loop is streamlined by communicating only the local results sought by individual processors, as it detects reduction semantics instead of sending and receiving individual elements of array data as communications for prefetching. You can think that you made it.

Here, the private variable means that its definition and reference are closed during the iteration of the loop.

(Equation 4)

In the above equation, the variable x is a private variable defined in each iteration of the loop and referenced only in that same iteration. When a source program is parallelized, it is divided for each iteration and given to different processors, but private variables can be handled as local variables for each processor, so interprocessor communication is used in the calculation. Does not occur. In this way, by temporarily treating the variables used in the loop as private variables for each processor, it is possible to ensure that parallel computation between iterations is executed correctly, and the communication overhead is reduced. It is important because it can be done.

If the determination in step 91 is "No", that is, if communication is not necessary or the array operand cannot be prefetched, the reduction variable of the original loop is made private (step 94). In this way, the reduction operation does not impair the parallelism of the loop.
Therefore, when the loop cannot be parallelized, the cause is the data dependency in other assignment statements in the loop. Such cases occur only when the loop itself has no parallelism. If the loop can be parallelized, insert a communication call for the global calculation of reduction outside the nesting level of the loop.

Explaining the sample program, since the reduction target arrays rx and rm do not have array variables on the left side in the loop, it can be understood from the analysis of the communication with respect to these array operands that communication is not necessary. Therefore, conversion is performed so that all the reduction variables rxm, irxm, and sum in the original loop are privatized without generating a new loop, and the loop becomes parallelizable. In this case, the calculation division of the loop is performed based on the variable rx or the variable rm that is the reduction target array.

It should be particularly noted that privatization of reduction variables and subsequent parallelization of loops is possible only when it is detected as reduction. By privateizing this variable, the above sample program is converted as follows. Variables with an underscore (for example, _rxm) in this program all represent private reduction variables. Also, the first three lines are initial value settings of the privateized reduction variables. Furthermore, the loop is already in parallel form, and the iteration range of the loop is divided.

[0062]

[Formula 5] _rxm = largest_val _irxm = 0 _sum = 0 do 200 j = lb1, ub1 do 200 i = lb2, ub2 if (mod (i, 2) = 1) then _sum = _sum + rm (i, j) ・・ ・ ・ ・ ・ (A) if ((abs (rx (i, j)) <abs (_rxm)) .and. (Mod (j, 2) = 1)) then _rxm = rx (i, j) ・・ ・ ・ ・ ・ (B) _irxm = i ・ ・ ・ ・ ・ ・ (c) _sum = _sum + rx (i, j) ・ ・ ・ ・ ・ ・ (d) endif endif 200 continue

Generation of reduction communication and its optimization (step 23) Generation of communication is performed for the parallelized reduction loop. The case where a single loop contains multiple reduction operations is very common in actual source programs. In such a case, it is not efficient to execute inter-processor communication independently for each reduction. Rather, it is more preferable to collectively vectorize the local intermediate results obtained by the respective processors for a plurality of reductions and transmit / receive them in one communication event. This is because it is possible to reduce the synchronization points of the entire system at the time of execution.

Reduction communication is executed in three steps. That is, (1) a step of determining a participating processor group based on division information (local iteration set: LIS) of a local calculation loop of reduction, (2) communication between processors that are members of the processor group, and Aggregating the results to the processor, and (3) transferring the final result calculated by this processor to the members of the processor group.

The above three steps can be described as a program as the following equation. Here,
The gid indicates a processor group.

[Equation 6] gid = lis2gid (LIS) call reduce (gid, & reduce_function, reduction_variable) call broadcast (gid, reduction_variable)

Generally, when merging a plurality of reduction communications, the division method of the processor differs for each reduction. Therefore, each processor group gid
It suffices to calculate the union of 1 and gid2 and execute communication with the processor group of this union.

[Equation 7] gid = gid1 ∪ gid2

Further, not only a set of local variables and global variables for reduction but also a processor group and reduction operator for each reduction are vectorized. In this case, the aggregation of this vector triggers the multi-reduction function. That is, different designated reduction operations are executed for each of the vectorized variables in a certain processor group, thereby reducing the number of times of communication and executing efficiently.

FIG. 10 is an example of a program list of a multi-reduction function. This program list shows only the case of integer type variables, but it can easily correspond to the case of variables of other types. Here, in1 is local input data and in2 is global input data. As shown here, the reduction operation for each vectorized element first performs the member check for the specified processor group, and only the processors that satisfy this check perform the operation. The processor that does not satisfy the check outputs the input data as it is without executing the operation. As described above, the execution rate of the parallel computer is improved by improving the data usage rate in the packet of the communication event for reduction and reducing the number of communication events.

The effect of merging a plurality of reduction communications existing in the same loop can be explained as follows. Two
Gi processor groups for one reduction communication
If d1 and gid2 are used and the union is gid0, the reduction communication is performed separately without merging the two reductions.

[0070]

[Equation 8] call reduce (gid1, SUM, s1, ・ ・ ・) call broadcast (gid1, s1, ・ ・ ・) call reduce (gid2, MAXVAL, s2, ・ ・ ・) call broadcast (gid2, s2, ・ ・・)

On the other hand, reduction communication when the reductions are merged is as follows. #d

[Equation 9] call reduce (gid0, (gid1, gid2), (SUM, MAXVAL), (s1, s2), ・ ・ ・) call broadcast (gid0, (gid1, gid2), (s1, s2) ・ ・ ・)

In the merged communication, a set of processor groups, a set of reduction operations, and a set of reduction variables are passed as arguments, and the union of processor groups gi
Communication is performed between d0. Each processor performs a member check on gid1 and gid2 passed as arguments, and determines whether to participate in each reduction and communication. "Reduce" and "broadcast" in the above formula
Can communicate with n processors by log (n), and if each processor is a leaf,
It can be thought of as height reduction.

Here, assuming that the numbers of processors of gid0, gid1, and gid2 are p, n, and m, p ≦ n + m. Therefore, when p, m, and n> 1, the following results.

(10) log (p) ≦ log (n + m) ≦ log (nm) = log (n) + log (m)

Therefore, comparing the communication times,

[Equation 11] reduce (gid0) ≦ reduce (gid1) + reduce (gid2) holds.

The merged reduction communication is gid1,
In the case where gid2 is disjoint with each other, there is at least one less broadcast communication to all processors. If gid1 and gid2 exist in the same processor group, the communication time will be halved. In general,
gid1 and gid2 partially share a processor with each other, and this relationship can be considered as shown in FIG. FIG.
When the reduction operation shares the processor, the height reduction of the tree structure having the processor as a leaf (height redu
FIG.

The loop of the above sample program is
If the communication is generated without optimizing the communication, the communication is generated for each of the three reductions.
There is a synchronization point for one communication. However, by taking the union of the processor groups obtained from the calculation divisions of the respective reductions and communicating with the group of processors of this expanded union, they can be merged into one communication. Reductions are grouped into one loop, and there is only one type of calculation division. Therefore, it is not necessary to take the union in this example. A processor group is obtained from this calculation division at runtime, and information for executing a plurality of reductions is passed as a vector to the runtime routine. This optimizes so that a plurality of reductions can be processed by one communication among the processors belonging to this processor group.

The following program shows the final form of the above sample program. The last 3 lines are the processor group (gid) from the calculation division at the time of execution.
Among the processors belonging to this group
Performs the reduction passed as a vector of kind,
Then, it is a call to a runtime routine that broadcasts the collected reduction results to all the processors.

[0078]

(Equation 12) _rxm = largest_val _irxm = 0 _sum = 0 do 200 j = lb1, ub1 do 200 i = lb2, ub2 if (mod (i, 2) = 1) then _sum = _sum + rm (i, j) ・・ ・ ・ ・ ・ (A) if ((abs (rx (i, j)) <abs (_rxm)) .and. (Mod (j, 2) = 1)) then _rxm = rx (i, j) ・・ ・ ・ ・ ・ (B) _irxm = i ・ ・ ・ ・ ・ ・ (c) _sum = _sum + rx (i, j) ・ ・ ・ ・ ・ ・ (d) endif endif 200 continue gid = lis2gid (LIS) call reduce (gid, 3, (abs-minval, abs-minloc, sum), (rxm, irxm, sum), (_rxm, _irxm, _sum)) call broadcast (gid, (rxm, irxm, sum))

In the present embodiment, even a reduction of a complicated expression that cannot be detected by the conventional method can be accurately detected as a reduction because many conditional expressions are present in the reduction loop. Also, by privateizing the reduction variable, it can be transformed so that parallel execution is possible, or even if it is not possible, it can be transformed so that the existence of reduction does not become a requirement that hinders loop parallelization. Become. Furthermore, even when there are multiple reductions in the loop, the number of communication events can be reduced by vectorizing the communication call.
Efficient communication has become possible. The method shown in this example is
It is very effective in numerical calculation programs, especially in algorithms for obtaining approximate solutions by the iterative method.

Finally, the parallelizing compiling method in this embodiment may be stored in the storage medium as a compiling program.

[0081]

[Effect] A parallelizing compiler using the present invention can accurately extract a reduction, which is a loop pattern that frequently appears in a source program, from the source program, and efficiently generate a target program that can be executed in parallel. . Therefore, the parallel computer can execute the target program thus compiled at high speed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a parallel computer.

FIG. 2 is a basic operation flow diagram from detection of reduction to optimization of reduction communication.

FIG. 3 is an operation flow chart in detection of reduction.

FIG. 4 is a diagram showing a relationship between an assignment statement of a loop body and an expression tree of a conditional expression generated from the assignment statement.

FIG. 5 is an expression tree related to a conditional expression of a sample program.

FIG. 6 is an example of an expression tree of an assignment statement.

FIG. 7 is an expression tree regarding an assignment statement of a sample program.

FIG. 8 is an expression tree showing a data dependency of a sample program.

FIG. 9 is an operation flow diagram for loop conversion of reduction.

FIG. 10 is an example of a program list of a multi-reduction function.

FIG. 11 is a diagram showing a height reduction of a tree structure having a processor as a leaf when the reduction operation shares the processor.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideaki Komatsu 1623-14 Shimotsuruma, Yamato-shi, Kanagawa Japan IBM Japan, Ltd. Tokyo Research Laboratory

Claims (11)

[Claims] 1. A parallelizing compiling method for translating a source program to generate an object program for a parallel computer having a plurality of processors, wherein the structure of a conditional expression masks an assignment statement existing in a loop in the source program. Analyzing the structure of the assignment statement existing in the loop, merging the structure of the assignment statement from the variable data dependency, the structure of the conditional expression and the merged And a step of referring to the data dependency of the variable and the operator in the assignment statement to detect reduction based on the structure of the assignment statement. 2. The parallelizing compiling method according to claim 1, further comprising the step of converting the reduction into a loop in which a plurality of the processors can execute in parallel. 3. In the step of detecting the reduction, when the right-hand side expression of the assignment statement is an expression, the data dependency of a recurrence variable among the variables is referred to, and the assignment statement is an exchange law and The parallelization compiling method according to claim 1 or 2, wherein the reduction is determined with reference to the operators that satisfy the associative law and that they are the same type of operator. 4. The step of detecting the reduction, wherein when the right-hand side expression of the assignment statement is a single variable, the reduction is judged based on the structure of the conditional statement. The parallelizing compilation method described in 2. 5. The step of analyzing the structure of the conditional expression generates an expression tree in which each of the conditional expressions is associated with a node and each of the assignment statements is associated with a leaf. The parallelized compiling method described in 1, 2, 3 or 4. 6. The step of analyzing the structure of the assignment statement is an expression in which each element forming the assignment statement is associated with a node for each leaf of the expression tree generated in the step of analyzing the structure of the conditional expression. The parallelizing compiling method according to claim 5, wherein a tree is generated. 7. The parallelized compiling method according to claim 1, further comprising the step of converting a reduction variable for controlling the detected reduction into a private variable for each processor. 8. A parallelization compiling method for translating a source program to generate an object program for a parallel computer having a plurality of processors, the method comprising: detecting a reduction controlled by a reduction variable; Converting the reduction variable into a private variable for each processor in order to perform parallel calculation for each processor to obtain a local result; and to aggregate the local results calculated in parallel for each processor And a step of generating reduction communication. 9. The step of generating the reduction communication to aggregate local results for the plurality of reductions calculated by each processor when the plurality of reductions are present in a single loop, The parallelized compiling method according to claim 8, wherein local results regarding a plurality of the reductions are vectorized and communicated. 10. A medium storing a compile program using the parallelizing compiling method according to any one of claims 1 to 9. 11. A parallel computer that executes an object program compiled by the parallelizing compilation method according to any one of claims 1 to 9.