JPH09307747A - Resolution converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain a high speed reduction processing by approximating an area discriminated to be a very small area among areas in a way of including the very small area to its adjacent area to extend a setting range of a reduction rate up to a range in excess of the reduction rate depending on a given picture element number or a line memory number. SOLUTION: A high-order 8-bit as a result of product sum result being an output of a projection filter 9 (assuming 256 gradation herein) is obtained from an adder 14. In the binarization processing, when the filter output is higher than a threshold level, a comparator 15 provides an output of '1' as a black level picture element and when not, the comparator 15 provides an output of '0' as a white level picture element. Contents of reference shift registers 10-12 are shifted left by an X-shift bit and a content of a counter is decremented simultaneously and when the count of the counter reaches 0, image data are given to low-order bytes of the reference shift registers. The processing above is repeated for several number of times, then one byte of reduced image data is generated and written in an image memory 13. Then 0-bits are filled to reduced image data less than one byte at the end of each line and the resulting byte data are written in the memory 13. Thus, one line of the reduced image is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resolution conversion device used for reducing an image in a facsimile machine, a digital copying machine or the like.

[0002]

2. Description of the Related Art In a facsimile machine, image data is input from a scanner, binarized and compressed, and temporarily stored in a memory. The image may be reduced to the plate. Further, in a facsimile machine using a standard size recording paper, the size of the recording paper may be reduced in order to fit the recording image within the range of the recording paper.

Conventionally, a projection method has been used as one of methods for reducing an image for such an application. The projection method is
As shown in FIG. 7, the area of a lattice (hereinafter, referred to as an original lattice and a nominal wavy line) representing an original image projected on a lattice that represents a converted image (hereinafter, referred to as a generation lattice and a solid line) is generated as a filter coefficient. It is a two-dimensional filter that outputs pixels. At this time, the reduction ratio in the main scanning direction is represented by the width of the original grid with respect to the width of the generation grid. X_rati in the figure
o represents the main scanning conversion rate. The same applies to the sub-scanning direction.

For example, the filter output for the shaded pixels in the figure is FilOut = (P2,2 × S00 + P2,3 × S01
+ P3,2 × S10 + P3,3 × S11)

Here, P2, 2 and the like represent original pixels, and black pixels have a value of "255" and white pixels have a value of "0". S00 is the area occupied by the lattice of P2, 2 inside the generation lattice. The same applies to other areas. FilOu
Since t is obtained as a multivalued signal, it is set as a threshold value T
A binary image is obtained compared to h. That is, FilOut ≧ Th → “black pixel” FilOut <Th → “white pixel” The threshold value is a predetermined constant and the original pixel is 25
If there are 6 gradations, the intermediate value is set to "128".

[0006]

However, in the resolution conversion apparatus configured as described above, the range of reference pixels expands as the degree of reduction increases, so the number of line memories increases, especially in the sub-scanning direction, and the circuit scale increases. Will increase. Further, when the line memory increases, there is a problem that the number of times of reading from the image memory and the divided area of the generation grid increase and the processing time increases.

The present invention provides a resolution converter suitable for speeding up, which can widen the setting range of the reduction ratio without increasing the circuit scale and can reduce the number of product-sum operations. With the goal.

[0008]

According to the present invention, there is provided a resolution conversion device for calculating a value of a conversion pixel by using a size of an area projected by a grid representing an original image on the grid formed by the conversion image as a weight of the original pixel. A region that can be judged to be minute among the regions is approximated to be included in the adjacent region, and the operation range of the resolution conversion device is expanded to a range exceeding the reduction ratio determined by the given number of pixels or the number of line memories.

[0009]

The present invention is based on the following theory.

That is, the reduction ratio is 1 / where n is an integer.
In the range up to (n-1), it is sufficient to have n reference lines. For example, if the reduction ratio is 1/2, three reference lines are sufficient, and if the reduction ratio is slightly less than 1/2, four line memories are required depending on the phase states of the generation grating and the original grating. . However, if the difference between the set reduction ratio and 1/2 is small, the initial grid width or the final grid width created by the original grid in the generated grid is small when four line memories are required, It is considered that the influence of the pixels corresponding to those grids is small.

Therefore, in the present invention, in the case of the above example, the first or last small grid area in the generation grid is included in the adjacent grid area, and approximately four lines are required while referring to the image of three lines. It is configured so that it can operate up to the reduction range. Since the image has a strong two-dimensional correlation, even if such an approximation is performed, a large image quality deterioration can be avoided if the approximation range is small.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a resolution converting apparatus showing an embodiment of the present invention. In this embodiment, the reduction ratio in the sub-scanning direction is 1.0 to 0.5. The range of the reduction ratio in the main scanning direction is 1.0 to 0.33. Therefore,
The maximum number of original grids in the generated grid is four in the main scanning direction (hereinafter, X direction), and the sub scanning direction (hereinafter, Y direction).
It is assumed that the maximum is 3.

First, the components of this embodiment will be described, and then the operation will be described with reference to the process flow diagram. Reference numeral 1 denotes a control unit that controls the entire resolution conversion apparatus, and includes a sequence control circuit 1a, an arithmetic logic operation circuit 1b (ALU), and a parameter register 1c that stores various control parameters. Registers 2 to 5 are registers that store the grid width in the X direction. Similarly, the registers 6 to 8 are registers for storing the lattice width in the Y direction. The projection filter 9 is composed of three product-sum operation circuits 9a to 9c. Inputs to the projection filter 9 are a grid width in the X and Y directions and a reference pixel. The reference pixel has a configuration capable of simultaneously referring to image data of three lines. They are the reference pixel shift registers 10
12 is stored. 10 receives the reference image data of the j-th line from the image memory 13. The image data is input to the lower side of this register. The same configuration is applied to 11 and 12. Reference numeral 14 is an adder that adds the outputs of the product-sum operation circuits. The output of the adder 14 is the output of the filter. A comparator 15 binarizes the filter output by comparing it with the output of the register 16 which is a threshold value. The shift register 17 is set to 1 every time a binarized pixel is generated.
This is a circuit for bit shifting and packing into byte data. Every time 8 pixels are generated, they are transferred to the image memory 13 through the image data bus 18.

FIG. 2 shows a configuration example of the product-sum calculation circuit 9a. The constituent element has four combinations of the multiplier 21 and the selector 22. The selector 22 outputs "ff" if the reference pixel is a black pixel, and outputs "0" if it is a white pixel.

FIG. 3 shows the contents of the arithmetic logic operation circuit 1b and the parameter register 1c. The meaning of the register will be described in the operation description as necessary.

4 to 6 are explanatory views of the approximation processing according to the present invention. In this embodiment, the approximation processing is targeted only in the sub-scanning direction. If the reduction ratio is set to 0.5 or less, depending on the phase relationship between the generation lattice and the original lattice, as shown in FIG.
The state of referring to the image data of the line appears. But,
Areas S00 and S0 if the difference from the reduction ratio of 0.5 is small
1, S02, S03 are divided areas S1 created by the next line
It is smaller than 0 and S11. FIG. 5 shows an approximation method in the initial grid width of the generation grid. Compared with FIG. 4, S00 is included in S10. From another point of view, the place where the j-th line should be referred to is substituted with the next line, the (j + 1) -th line. The narrow portion shown in FIG. 4 appears at the beginning or end of the generator grid.
Similar to FIG. 5, FIG. 6 shows a state in which the last part of the generation grid is approximated by the line before it. By approximating in this way, the 4-line memory can process the required area with 3 lines. In particular, in a document image, the correlation is strong, and the j-th line and the (j + 1) -th line often have similar pixel arrangements, and if the degree of approximation is small, large image quality deterioration can be avoided. Next, the operation will be described with reference to FIG. First, the symbols appearing in the flow chart will be described with reference to FIG. X_initial is the initial grid width in the generation grid, X_ratio is the reduction ratio, and Rx is the final grid width. A symbol is similarly defined for the Y direction. The reference line is the j-th line from the top, the (j + 1) -th line
The line is the (j + 2) th line. The area of the region in which the generation grid is divided by the original grid is represented by S00 with a subscript. Other symbols will be explained as necessary.

In FIG. 7, it is assumed that addition and subtraction are executed by the arithmetic logic operation circuit 1b.

In FIG. 9, a process 101 is a Ylatti which is a register for calculating an address of an original lattice in the Y direction as initialization of a register at the head of a page.
Clear ceReg and Y_initial. These registers are parameter registers 1 as shown in FIG.
It is included in c.

Process 102 is the reference pixel shift register 1
Reference image data is input to 0, 11, and 12. First, in the lower byte of the shift register 10, the first line (j = 1)
The byte data at the head of is input from the image memory 13 and is shifted to the left by 8 bits. For the shift operation, the shift signal Sf1 is input eight times. The shift signal Sf1 is a part of the control signal output from the sequence control circuit 1a. After that, the next 1 byte is input to the lower byte again. The shift register 11 stores the reference image data of the second line in 1
The reference image data of the third line is similarly input to 2.

The process 103 is similar to the process 101, and is a register Xlat for calculating the address of the original lattice in the X direction.
Clear theiceReg and X_initial. C
T is a counter value, and 8 is set as the initial value.

In process 104, the lattice address in the Y direction is calculated, and the lattice width is calculated from the calculated value and set in the registers 6-8.

11 and 12 show details of the process 104.
The process 300 clears Y_shift and Y_num. Y_shift is the number of original grids included in the generation grid, and Y_num is the number of reference lines applied to the generation grid. Taking FIG. 8 as an example, Y_shift = 2, Y
_Num = 3.

Y_initial is determined in the processing 301.
Is not “0”, the work register is set to Y_ in process 302.
The initial value is written, and in step 303 Y_sh
Increment ift, Y_num. At the beginning of the page, Y_initial is "0", so these processes are not performed.

In process 304, the addition of Y_initia and the reduction ratio Y_ratio in the Y direction is performed by the arithmetic logic operation circuit 1b, and the operation result is temporarily stored in the accumulator (acca). The width of the generation grid is normalized to 10000H, and the reduction ratio is defined as the width of the original grid with respect to the width of the generation grid. For example, if the reduction ratio is 0.9, 6
Since 5536 × 0.9 = 58982 = E666H, E666H is set in advance in the parameter register Y_ratio. The same applies to the X direction. As a result of the process 304, it is determined whether or not the carry signal indicating the overflow is turned on in the process 305. The carry signal is turned on when the addition result is equal to or exceeds 10000H. This is a part of the status signal output from the arithmetic logic operation circuit 1b (FIGS. 1 and 3). While the carry signal is OFF, it indicates that the original lattice is inside the generation lattice. In process 306, process 3
The result of 04 is stored in YlatticeReg. In process 307, Y_ratio is written in the work register. In process 308, Y_shift and Y_num are incremented.

It is assumed that the process shifts to the process 309 by the determination of the process 305. Process 309 determines whether the generated grid and the original grid overlap. If they do not overlap with each other, the final grid width Ry is obtained in step 311 and written in the work register. When the grids overlap, the final width is equal to Y_ratio, so in step 314, this is written in the work register. In process 312 and process 315, the value of Y_shift is "
1 ". When the lattices overlap, Y_shift
= Y_num, but normally Y_num = Y_shi
ft + 1. In process 316, the initial value Y_initial of the calculation in the next generation grid is updated. This completes the calculation of the lattice address. For example, if the reduction ratio is 0.9,
On the first line, these values are as follows.

Y_ratio = E666H Ywork # [0] = E666H Ywork # [1] = 199aH Ywork # [2] = 0 Y_initial = ccccH Y_shift = 1 Y_num = 2 The widths of the processing 319 to the processing 321 are the widths of the grids 319 to 321. Set in registers 6, 7, and 8. In process 318, the Y of the generated grid
When the number of divisions in the direction is 2, the grid width register 8
0 "is written.

When Y_num is 4 in the judgment of the process 322, the first grid width (Ywor) in the generated grid is calculated in the process 323.
k # [0]) and the last grid width (Ywork # [3]) are compared to determine which side is to perform the approximation process. Processes 324 to 327 are a case where the initial grid width is approximated, and correspond to FIG. Processes 328 to 331 are for approximating the final grid width and correspond to FIG. The above is the contents of the process 704 of FIG.

In FIG. 9, processing 105 to processing 111 is 1
This is line processing. In process 105, as in process 104, the grid width in the X direction is calculated and set in the grid width registers 2-5. For details, refer to FIG.
It is almost the same as

Process 106 is filter calculation, threshold value process, and binarization process. For the filter calculation, the sum of products operation described in the conventional example is performed. The components of FIG. 2 are as described above. The filter output here is 256 gradations (8
Since the upper 8 bits of the product-sum operation result are obtained from the adder 14 of FIG. For binarization, if the filter output by the comparator 15 is larger than the threshold value, it is set to "1" as a black pixel, and otherwise set to a white pixel "0".

In the process 107, the shift signal Sf2 is turned on and one bit of the binarized pixel is written in the shift register 17. This completes the filtering process for one pixel.

In process 108, the reference pixel shift registers 10 to 12 are shifted to the left by X_shift bits,
At the same time, the counter CT is subtracted, and when it becomes "0", the image data is input to the lower byte of the reference pixel shift register. The details are as shown in processes 200 to 208 of FIG.

By repeating the processes 105 to 108 eight times, one byte of reduced image data is generated. This is written in the image memory 13 in process 110. The processes 105 to 110 are repeated for one line. In process 112, the reduced image data of less than 1 byte at the line end is padded with "0" bits and written in the memory 13 as byte data. As described above, one line of the reduced image is generated.

The reference line needs to be updated to generate the next line. Since the number of lines corresponding to Y_shift is not used for the processing of the next line, the address of the image memory 13 to be read may be updated based on it. If the above process is repeated for the number of lines of the original image, 1
Processing of the page ends. In this embodiment, the approximation processing is performed only in the sub-scanning direction, but the same idea can be applied to the processing in the main scanning direction. Further, although the present embodiment is a conversion from a binary image to a binary image, the approximation processing itself can be similarly applied to the resolution conversion from a multivalued image to a multivalued image.

A supplementary explanation will be given on the setting range of the reduction ratio and the number of line memories. It is assumed that the number of line memories is n and the reduction ratio Y_ratio in the sub-scanning direction is a value of 0 to 1.0. In this case, the minimum value of the reduction ratio that can be set by the conventional projection filter is determined in the following situation. That is,
This is the case where one generation grid matches the original grid and the next generation grid slightly covers the nth original image. If this slightly applied width is ε, and the width of the generation grid is 1.0, the relationship at this time is expressed by an equation: (n−1) × Y_ratio + ε = 1.0. When the reduction rate is expressed by 16 bits, the minimum value of ε is 2 minus 16. This is a constant determined by the arithmetic precision of the arithmetic logic unit. Therefore, Y_ratio ≧ (1.0−2 ⁻¹⁶ ) / (n−1) is the conventional operating range. In the present invention, when n is replaced with (n + 1), the image quality deterioration is acceptable, and the operation range is smaller than (1.0-2 ⁻¹⁶ ) / (n−1).
It can be expanded to a range larger than (1.0-2 ^-16 ) / n.

[0036]

As is apparent from the above description, the setting range of the reduction ratio can be expanded by approximating the first or last grid width of the generation grid to be included in the area of the adjacent line, and By doing so, the number of divided regions is reduced and the number of product-sum operations is reduced, so that there is an effect that the reduction processing can be speeded up.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a detailed block diagram of a product-sum calculation circuit.

FIG. 3 shows a parameter register 1c and an arithmetic logic operation circuit 1
Block diagram showing the vicinity of b

FIG. 4 is an explanatory diagram of an approximation process of the present invention.

FIG. 5 is an explanatory diagram of an approximation process of the present invention.

FIG. 6 is an explanatory diagram of an approximation process of the present invention.

FIG. 7 is an explanatory diagram of reduction processing by a projection method.

FIG. 8 is an explanatory diagram showing the definition of symbols.

FIG. 9 is a process flow chart for explaining the operation of the present invention.

FIG. 10 is a detailed process flow chart for explaining the operation of the present invention.

FIG. 11 is a detailed process flow chart for explaining the operation of the present invention.

FIG. 12 is a detailed process flow diagram (continuation) illustrating the operation of the present invention.

[Explanation of symbols]

 1 control unit 1a sequence control circuit 1b arithmetic logic operation circuit 1c parameter register 2 register 3 register 4 register 5 register 6 register 7 register 8 register 9 projection filter 9a product sum operation circuit 9b product sum operation circuit 9c product sum operation circuit 10 reference pixel Shift register 11 reference pixel shift register 12 reference pixel shift register 13 image memory 14 adder 15 comparator 16 register 17 shift register 18 image data bus

Claims (4)

[Claims] 1. A resolution conversion device that calculates the value of a conversion pixel by using the size of the area of the grid formed by the conversion image onto which the grid representing the original image is projected, as the weight of the original pixel, and determines that the area is minute. A resolution conversion device characterized by approximating a region to be included in an adjacent region. 2. A value of a conversion pixel is calculated by using a size of a region of a grid formed by a conversion image onto which a grid representing the original image is projected, as a weight of the original pixel, and the value of the conversion pixel is compared with a predetermined threshold value. In a resolution conversion device for obtaining a binarized image by means of the above, when the number of pixels of the original image in the grid of the converted image is larger than a predetermined value, the area determined to be minute in the grid of the converted image is adjacent to the adjacent area. A resolution conversion method characterized by approximating to include in the area. 3. A value of a conversion pixel is calculated using the size of a region of a grid formed by a conversion image onto which a grid representing the original image is projected, as a weight of the original pixel, and the value is compared with a predetermined threshold value. In a resolution conversion device for obtaining a binarized image by means of the above, when the number of lines of the original image in the grid of the converted image is larger than a predetermined value, the first or last division width in the grid of the converted image is adjacent to the adjacent division width. A resolution conversion device characterized by approximating to include in a region. 4. A resolution conversion device for calculating a value of a conversion pixel by using a size of a region of a grid formed by a conversion image in which a grid representing an original image is converted, as a weight of the original pixel, and n in the number of line memories, When ε is the minimum precision of the reduction rate that can be expressed, the range of reduction operation is (1.0−ε) / (n−1)
Resolution conversion device characterized by being smaller than.