JPH09307056A - Semiconductor device and method of manufacturing it - Google Patents
Semiconductor device and method of manufacturing itInfo
- Publication number
- JPH09307056A JPH09307056A JP8120658A JP12065896A JPH09307056A JP H09307056 A JPH09307056 A JP H09307056A JP 8120658 A JP8120658 A JP 8120658A JP 12065896 A JP12065896 A JP 12065896A JP H09307056 A JPH09307056 A JP H09307056A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor chip
- semiconductor
- mounting
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、同一の半導体チッ
プを複数個用いて基板に直接実装した半導体装置及びそ
の製造方法に関し、例えばカード型電子機器のような特
に薄型、高密度化が要求される半導体装置及びその製造
方法に好適のものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a plurality of identical semiconductor chips are directly mounted on a substrate and a method of manufacturing the same, and is required to be particularly thin and high in density such as card type electronic equipment. It is suitable for a semiconductor device and a manufacturing method thereof.
【0002】[0002]
【従来の技術】従来より、半導体装置のベアチップ実装
方法としてワイヤーボンディング技術、フリップチップ
技術、TAB技術が採用されている。従来同一基板上に
ベアチップ実装をする場合、これらそれぞれの技術が単
独で採用されていた。特に部品実装上の制約、例えばワ
イヤーボンディング技術ではベアチップの端子ピッチが
100μm以下、端子数200以上になると実装が困難
になるため、そのようなべアチップ実装にはTAB技術
のみを採用している、というようなものであった。2. Description of the Related Art Conventionally, wire bonding technology, flip chip technology, and TAB technology have been adopted as bare chip mounting methods for semiconductor devices. Conventionally, in the case of bare chip mounting on the same substrate, each of these technologies has been adopted independently. In particular, restrictions on component mounting, for example, in the wire bonding technique, when the bare chip has a terminal pitch of 100 μm or less and the number of terminals is 200 or more, it becomes difficult to mount. Therefore, only the TAB technique is adopted for such bare chip mounting. It was like that.
【0003】また一方、例えばメモリーICのように特
に端子数、端子ピッチに制約のないベアチップを複数個
同一基板上に実装する場合では、製造コストを押さえる
ため、主としてワイヤーボンディング技術が単独で採用
されている。On the other hand, in the case of mounting a plurality of bare chips which are not particularly limited in the number of terminals and the terminal pitch on the same substrate such as a memory IC, the wire bonding technique is mainly adopted in order to suppress the manufacturing cost. ing.
【0004】図2は同一パッド配列のベアチップを複数
個前記ワイヤーボンディング技術で基板上に実装する場
合の基板実装図の一例を示している。第1半導体チップ
1は実装厚を薄くするため基板を削って設けられた凹部
4に接着材10により固定され、第1半導体チップのパ
ッド2と基板上に設けられた基板端子6はワイヤーボン
ディング技術により金属細線5により接続される。そし
て、基板端子6は基板上に設けられた金属配線7により
バイアホール8に接続している。また、第2半導体チッ
プ1aは第1半導体チップ1と同様の方法で基板上に実
装され、パッド3の信号がバイアホール8aに接続され
た構造になっている。各半導体チップは同一の方向に配
置されていることになる。バイアホール8及び8aは基
板裏面または内層面に配線された金属配線7bにより接
続されている。これにより第1半導体チップ1のパッド
2,2a,2b,2cはそれぞれ第2半導体チップ1a
の同一パット3,3a,3b,3cと接続することがで
きる。FIG. 2 shows an example of a board mounting diagram when a plurality of bare chips having the same pad arrangement are mounted on the board by the wire bonding technique. The first semiconductor chip 1 is fixed by an adhesive material 10 to a recess 4 formed by cutting the substrate to reduce the mounting thickness, and the pad 2 of the first semiconductor chip and the substrate terminal 6 provided on the substrate are wire-bonding technology. Are connected by the thin metal wire 5. The substrate terminal 6 is connected to the via hole 8 by the metal wiring 7 provided on the substrate. The second semiconductor chip 1a is mounted on the substrate in the same manner as the first semiconductor chip 1, and the signal of the pad 3 is connected to the via hole 8a. The respective semiconductor chips are arranged in the same direction. The via holes 8 and 8a are connected by a metal wiring 7b arranged on the back surface of the substrate or the inner layer surface. As a result, the pads 2, 2a, 2b, 2c of the first semiconductor chip 1 are respectively connected to the second semiconductor chip 1a.
Can be connected to the same pads 3, 3a, 3b, 3c.
【0005】[0005]
【発明が解決しようとする課題】しかしながら、近年ま
すます薄型、高密度実装化が要求される中で、限られた
基板面積および実装厚の中により多くの半導体チップを
実装しようとした場合、図2のように同一の実装技術で
しかも同一の実装方向にて全ての半導体チップをベアチ
ップ実装していると、特に半導体チップのパッド数が多
くなれば同一基板面だけでの配線の引き回しができなく
なり、基板内に設けるバイアホールの数を増やさなけれ
ばならず、その結果、基板裏面または内層面にも多くの
金属配線を引きまわすことになり、その分高密度化、薄
型化の妨げとなっている。However, as more and more thin and high-density mounting is required in recent years, when more semiconductor chips are mounted in a limited board area and mounting thickness, If all the semiconductor chips are bare-chip mounted in the same mounting technique and in the same mounting direction as in 2, it becomes impossible to route the wiring only on the same substrate surface especially when the number of pads of the semiconductor chip increases. , It is necessary to increase the number of via holes provided in the board, and as a result, many metal wirings are also routed to the back surface of the board or the inner layer surface, which hinders high density and thinness. There is.
【0006】そこで本発明の半導体実装方法は上述した
問題点に鑑みてなされたものであり、その目的とすると
ころは、限られた基板面積および基板厚のなかでより多
くの半導体チップを実装し、無理のない基板設計を容易
に可能にすることにある。Therefore, the semiconductor mounting method of the present invention has been made in view of the above-mentioned problems, and an object thereof is to mount a larger number of semiconductor chips in a limited board area and board thickness. The purpose is to easily enable easy board design.
【0007】[0007]
【課題を解決するための手段】上記課題を解決するため
に本発明の半導体装置は、基板と、能動面の反対となる
面を前記基板の実装面と相対向するよう直接前記基板に
実装した第1の半導体チップと、能動面を前記基板の実
装面と相対向するよう直接前記基板に実装した第2の半
導体チップと、を有してなることを特徴とする。In order to solve the above-mentioned problems, the semiconductor device of the present invention is mounted directly on the substrate so that the surface opposite to the active surface faces the mounting surface of the substrate. It is characterized by comprising a first semiconductor chip and a second semiconductor chip directly mounted on the substrate so that the active surface of the substrate faces the mounting surface of the substrate.
【0008】また上記半導体装置において前記第1およ
び前記第2の半導体チップは、同一の半導体チップから
なることを特徴とする。Further, in the above semiconductor device, the first and second semiconductor chips are made of the same semiconductor chip.
【0009】更に上記半導体装置において前記第1の半
導体チップは前記基板と金属細線にて接続され、前記第
2の半導体チップは前記基板とバンプを介して接続され
てなることを特徴とする。Further, in the above semiconductor device, the first semiconductor chip is connected to the substrate by a fine metal wire, and the second semiconductor chip is connected to the substrate via a bump.
【0010】または前記第1の半導体チップは前記基板
と金属細線にて接続され、前記第2の半導体チップは前
記基板と表TAB実装にて接続されてなることを特徴と
する。Alternatively, the first semiconductor chip is connected to the substrate by a thin metal wire, and the second semiconductor chip is connected to the substrate by front TAB mounting.
【0011】または前記第1の半導体チップは前記基板
と裏TAB実装にて接続され、前記第2の半導体チップ
は前記基板とバンプを介して接続されてなることを特徴
とする。Alternatively, the first semiconductor chip is connected to the substrate by back TAB mounting, and the second semiconductor chip is connected to the substrate via bumps.
【0012】もしくは前記第1の半導体チップは前記基
板と裏TAB実装にて接続され、前記第2の半導体チッ
プは前記基板と表TAB実装にて接続されてなることを
特徴とする。Alternatively, the first semiconductor chip is connected to the substrate by back TAB mounting, and the second semiconductor chip is connected to the substrate by front TAB mounting.
【0013】従って上記記載の各々の半導体装置によれ
ば、同一パッド配列の半導体チップを複数個実装する場
合、基板に余分なバイアホールを形成することなくかつ
同一基板層上での金属配線が容易になるため、基板裏面
または内層面への余分な金属配線を削除できる。このた
め薄型かつ高密度な基板設計が容易に可能になる。Therefore, according to each of the semiconductor devices described above, when a plurality of semiconductor chips having the same pad arrangement are mounted, it is easy to form metal wiring on the same substrate layer without forming extra via holes in the substrate. Therefore, it is possible to remove extra metal wiring on the back surface or the inner layer surface of the substrate. Therefore, it is possible to easily design a thin and high-density substrate.
【0014】一方、本発明の半導体装置の製造方法は少
なくとも第1、第2の同一の半導体チップを基板に直接
実装する半導体装置の製造方法であって、前記第1の半
導体チップは能動面の反対となる面を前記基板の実装面
と相対向するよう直接前記基板に実装される工程と、前
記第2の半導体チップは能動面を前記基板の実装面と相
対向するよう直接前記基板に実装される工程と、を含ん
でなることを特徴とする。On the other hand, a method of manufacturing a semiconductor device of the present invention is a method of manufacturing a semiconductor device in which at least first and second identical semiconductor chips are directly mounted on a substrate, and the first semiconductor chip is an active surface. Directly mounting on the substrate so that the opposite surface faces the mounting surface of the substrate, and the second semiconductor chip directly mounts on the substrate so that the active surface faces the mounting surface of the substrate. And a step of:
【0015】更に上記半導体装置の製造方法において、
前記第1の半導体チップは前記基板にワイヤボンディン
グにて接続され、前記第2の半導体チップはフリップチ
ップ実装にて接続されてなることを特徴とする。Further, in the method of manufacturing a semiconductor device described above,
The first semiconductor chip is connected to the substrate by wire bonding, and the second semiconductor chip is connected by flip chip mounting.
【0016】更に上記半導体装置の製造方法において、
前記第1の半導体チップは前記基板にワイヤボンディン
グにて接続され、前記第2の半導体チップは前記基板と
表TAB実装にて接続されてなることを特徴とする。Further, in the method of manufacturing a semiconductor device described above,
The first semiconductor chip is connected to the substrate by wire bonding, and the second semiconductor chip is connected to the substrate by table TAB mounting.
【0017】また前記ワイヤーボンディングにより前記
第1の半導体チップを実装し樹脂封止した後、フリップ
チップ実装または表TAB実装を行うことを特徴とす
る。Further, the first semiconductor chip is mounted by the wire bonding and resin-sealed, and then flip-chip mounting or front TAB mounting is performed.
【0018】上記実装方法によれば、ワイヤーボンディ
ング実装を行う際必要になる高温下での樹脂封止工程を
先に行うことにより、以後に行うフリップチップ実装お
よび表TAB実装の半田付け品質に影響を与えることな
く行うことが可能になる。According to the above-mentioned mounting method, the resin sealing step at a high temperature, which is necessary for the wire bonding mounting, is performed first, so that the soldering quality of the flip chip mounting and the table TAB mounting performed thereafter is affected. Can be done without giving.
【0019】[0019]
【発明の実施の形態】図1(a)は、本発明による半導
体装置の一実施例を説明するための図であって、概略的
に示している。1は第1半導体チップ、1aは第2半導
体チップであり、同一の半導体チップである。第1半導
体チップ1は基板実装厚を薄くするため基板を削って設
けられた凹部4に接着材10により能動面が基板の実装
面と同一方向(上向き)に固定され、一方第2半導体チ
ップ1aは能動面が基板の実装面と対向方向(下向き)
に固定される。本実施例では、第1半導体チップ1のパ
ッド2と基板上に設けられた基板端子6は図3に示すよ
うなワイヤーボンディング技術による金属細線5によっ
て接続されている。基板端子6は基板上に設けた金属配
線7に接続されている。また、第2半導体チップ1aは
図4に示すようなフリップチップ技術により、パッド3
上に形成されたバンプ12を介して、基板端子6に接続
される。基板端子6は金属配線7に接続されている。こ
れにより第1半導体チップ1のパッド2,2a,2b,
2cと第2半導体チップ1aの同一パッド3,3a,3
b,3cとを接続する金属配線7はそれぞれ基板にバイ
アホールを用いて多層に形成される必要がなく、金属配
線7は基板の同一面(層)上に形成可能であり、半導体
装置の薄型が可能となる。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1A is a diagram for explaining an embodiment of a semiconductor device according to the present invention and is a schematic view. Reference numeral 1 is a first semiconductor chip and 1a is a second semiconductor chip, which are the same semiconductor chip. The first semiconductor chip 1 has an active surface fixed in the same direction (upward) as the mounting surface of the substrate by an adhesive 10 in a recess 4 formed by cutting the substrate in order to reduce the mounting thickness of the substrate, while the second semiconductor chip 1a is formed. Indicates that the active surface faces the mounting surface of the board (downward)
Fixed to. In this embodiment, the pad 2 of the first semiconductor chip 1 and the substrate terminal 6 provided on the substrate are connected by the metal thin wire 5 by the wire bonding technique as shown in FIG. The substrate terminal 6 is connected to the metal wiring 7 provided on the substrate. In addition, the second semiconductor chip 1a is formed on the pad 3 by the flip chip technique as shown in FIG.
It is connected to the substrate terminal 6 via the bump 12 formed above. The substrate terminal 6 is connected to the metal wiring 7. As a result, the pads 2, 2a, 2b of the first semiconductor chip 1,
2c and the same pad 3, 3a, 3 of the second semiconductor chip 1a
The metal wirings 7 for connecting b and 3c do not have to be formed in multiple layers by using via holes in the substrate, and the metal wirings 7 can be formed on the same surface (layer) of the substrate, which is a thin semiconductor device. Is possible.
【0020】また、図1(b)は本発明による半導体装
置の別の一実施例を説明するための図であって、概略的
に示している。上述同様、第1半導体チップ1はワイヤ
ーボンディング技術により基板上に能動面を上にして実
装される。そして第2半導体チップ1aも上述同様、フ
リップチップ技術により第1半導体チップ1と同一パッ
ドが向かい合う位置に実装される。これにより、第1半
導体チップ1と第2半導体チップ1aの同一パッド同士
は基板上に配線された金属配線7により、基板上に余分
なバイアホールまたは金属配線を施すことなく、薄型の
基板を用いることが可能で、しかも最短距離にて各パッ
ド間を接続することができる。Further, FIG. 1B is a diagram for explaining another embodiment of the semiconductor device according to the present invention, and is schematically shown. Similarly to the above, the first semiconductor chip 1 is mounted on the substrate with the active surface upward by the wire bonding technique. Similarly to the above, the second semiconductor chip 1a is also mounted by the flip chip technique at the same pad as the first semiconductor chip 1 at a position facing each other. As a result, the same pads of the first semiconductor chip 1 and the second semiconductor chip 1a use the thin substrate without forming extra via holes or metal wiring on the substrate due to the metal wiring 7 wired on the substrate. It is possible to connect each pad with the shortest distance.
【0021】上記半導体装置の製造方法の例を以下に示
す。An example of a method of manufacturing the above semiconductor device will be shown below.
【0022】まず第1半導体チップ1を基板凹部4に接
着剤10により能動面が基板の実装面と同一方向に固定
した後、ワイヤボンディング技術により金属細線5によ
ってパッド2と基板端子6を接続する。その後熱硬化性
の樹脂11により100℃〜150℃の高温下で2〜4
時間熱硬化させて第1半導体チップ1及び金属細線5,
基板端子6を封止する。次に第2半導体チップ1aをフ
リップチップ技術により能動面が基板実装面と対向方向
に、パッド3上に形成されたバンプ12を介して基板端
子6に接続する。First, the first semiconductor chip 1 is fixed in the recess 4 of the substrate with the adhesive 10 in the same direction as the mounting surface of the substrate, and then the pad 2 and the substrate terminal 6 are connected by the metal wire 5 by the wire bonding technique. . After that, the thermosetting resin 11 is used for 2 to 4 at a high temperature of 100 ° C to 150 ° C.
The first semiconductor chip 1 and the thin metal wires 5, which are thermally cured for a time,
The board terminal 6 is sealed. Next, the second semiconductor chip 1a is connected to the substrate terminal 6 by the flip-chip technique with the active surface facing the substrate mounting surface via the bumps 12 formed on the pads 3.
【0023】また、他の実施例として例えば上述の第1
半導体チップ1をワイヤーボンディング技術にて実装
し、上述第2半導体チップ1aを図6に示すように表T
AB技術にて実装する。ここで表TABとは、チップに
TABリード13を一括ボンディングする際、TAB基
材14がリード13に対しチップ能動面反対側になるよ
うボンディングしたTABを表TABと定義する。この
ような構造を採ることにより、基板上に余分なバイアホ
ールまたは金属配線を施すことなく容易に両半導体チッ
プの同一パッドどうしを接続することができる。この場
合の製造方法としては、まず第1半導体チップ1を前記
手順に従いワイヤボンディング技術で基板に実装後、樹
脂封止する。次に表TAB技術により実装された第2半
導体チップ1aを能動面が基板実装面と対向方向に基板
上に設置し、リード13を基板端子6に半田付け接続す
る。As another embodiment, for example, the above-mentioned first
The semiconductor chip 1 is mounted by the wire bonding technique, and the second semiconductor chip 1a is mounted on the table T as shown in FIG.
Implemented with AB technology. Here, the table TAB is defined as a table TAB in which the TAB substrate 14 is bonded so that the TAB substrate 14 is on the side opposite to the chip active surface when the TAB leads 13 are collectively bonded to the chip. By adopting such a structure, the same pads of both semiconductor chips can be easily connected without providing an extra via hole or metal wiring on the substrate. As a manufacturing method in this case, first, the first semiconductor chip 1 is mounted on a substrate by a wire bonding technique according to the above procedure, and then sealed with resin. Next, the second semiconductor chip 1a mounted by the table TAB technique is placed on the substrate with the active surface facing the substrate mounting surface, and the leads 13 are soldered to the substrate terminals 6.
【0024】また、例えば上述の第1半導体チップ1を
図5に示すような裏TAB技術にて実装し、上述第2半
導体チップ1aをフリップチップ技術にて実装する。こ
こで裏TABとは、チップにTABリード13を一括ボ
ンディングする際、TAB基材14がリード13に対し
チップ能動面側になるようボンディングしたTABを裏
TABと定義する。このような構造を採ることにより、
基板上に余分なバイアホールまたは金属配線を施すこと
なく容易に両半導体チップの同一パッドどうしを接続す
ることができる。Further, for example, the above-mentioned first semiconductor chip 1 is mounted by the back TAB technique as shown in FIG. 5, and the above-mentioned second semiconductor chip 1a is mounted by the flip-chip technique. Here, the back TAB is defined as the back TAB when the TAB lead 13 is bonded to the chip at a time so that the TAB substrate 14 is bonded to the lead 13 on the chip active surface side. By adopting such a structure,
It is possible to easily connect the same pads of both semiconductor chips to each other without providing an extra via hole or metal wiring on the substrate.
【0025】また、他の例として例えば上述の第1半導
体チップ1を表TAB技術にて実装し、上述第2半導体
チップ1aを裏TAB技術にて実装することにより基板
上に余分なバイアホールまたは金属配線を施すことなく
容易に両半導体チップの同一パッドどうしを接続するこ
とができる。この場合の製造方法としては、まず裏TA
B技術により実装された第1半導体チップ1を能動面が
基板実装面と同一方向に基板上に設置し、リード13を
基板端子6に半田付け接続する。次に表TAB技術によ
り実装された第2半導体チップ1aを能動面が基板実装
面と対向方向に基板上に設置し、リード13を基板端子
6に半田付け接続する。なお、実装手順は逆でも行うこ
とが可能である。As another example, for example, by mounting the first semiconductor chip 1 described above by the front TAB technique and mounting the second semiconductor chip 1a by the back TAB technique, an extra via hole or The same pads of both semiconductor chips can be easily connected without providing metal wiring. As the manufacturing method in this case, first, the back TA
The first semiconductor chip 1 mounted by the B technology is placed on the substrate with the active surface in the same direction as the substrate mounting surface, and the leads 13 are connected to the substrate terminals 6 by soldering. Next, the second semiconductor chip 1a mounted by the table TAB technique is placed on the substrate with the active surface facing the substrate mounting surface, and the leads 13 are soldered to the substrate terminals 6. The mounting procedure can be reversed.
【0026】以上、各実施例について説明したが、本実
施例の半導体装置を例えばカード形状のメモリー装置の
ように、同一の半導体チップを複数個基板上に実装する
半導体装置に用いるのが最も好適である。Although the respective embodiments have been described above, it is most preferable to use the semiconductor device of this embodiment for a semiconductor device in which a plurality of identical semiconductor chips are mounted on a substrate, such as a card-shaped memory device. Is.
【0027】[0027]
【発明の効果】本発明の半導体装置によれば、基板上に
余分なバイアホールまたは金属配線を施すことなく基板
設計を行うことができるため、高密度かつ薄型の半導体
チップ実装ができる。According to the semiconductor device of the present invention, since it is possible to design a substrate without providing an extra via hole or metal wiring on the substrate, a high-density and thin semiconductor chip can be mounted.
【図1】本発明による半導体装置の第1実施例の基板配
線概略図である。FIG. 1 is a schematic view of substrate wiring of a first embodiment of a semiconductor device according to the present invention.
【図2】従来の半導体装置における基板配線概略図であ
る。FIG. 2 is a schematic diagram of substrate wiring in a conventional semiconductor device.
【図3】ワイヤーボンディング技術による基板実装断面
概略図である。FIG. 3 is a schematic cross-sectional view of mounting on a substrate by a wire bonding technique.
【図4】フリップチップ技術による基板実装断面概略図
である。FIG. 4 is a schematic cross-sectional view of substrate mounting by flip chip technology.
【図5】裏TAB技術による基板実装断面概略図であ
る。FIG. 5 is a schematic cross-sectional view of mounting on a substrate by a back TAB technique.
【図6】表TAB技術による基板実装断面概略図であ
る。FIG. 6 is a schematic cross-sectional view of board mounting according to the table TAB technique.
1 第1半導体チップ 1a 第2半導体チップ 2、2a、2b、2c 第1半導体チップパッド 3、3a、3b、3c 第2半導体チップパッド 4 基板凹部 5、5a 金属細線 6 基板端子 7、7a、7b 金属配線 8、8a バイアホール 9 基板 10 接着材 11 樹脂 12 バンプ 13 リード 14 TAB基材 15 半田 1 1st semiconductor chip 1a 2nd semiconductor chip 2, 2a, 2b, 2c 1st semiconductor chip pad 3, 3a, 3b, 3c 2nd semiconductor chip pad 4 substrate recess 5, 5a metal thin wire 6 substrate terminal 7, 7a, 7b Metal wiring 8, 8a Via hole 9 Substrate 10 Adhesive material 11 Resin 12 Bump 13 Lead 14 TAB base material 15 Solder
Claims (10)
板の実装面と相対向するよう直接前記基板に実装した第
1の半導体チップと、能動面を前記基板の実装面と相対
向するよう直接前記基板に実装した第2の半導体チップ
と、を有してなることを特徴とする半導体装置。1. A substrate, a first semiconductor chip directly mounted on the substrate so that a surface opposite to the active surface faces the mounting surface of the substrate, and an active surface faces the mounting surface of the substrate. And a second semiconductor chip directly mounted on the substrate so as to provide a semiconductor device.
は、同一の半導体チップからなることを特徴とする請求
項1記載の半導体装置。2. The semiconductor device according to claim 1, wherein the first and second semiconductor chips are made of the same semiconductor chip.
属細線にて接続され、前記第2の半導体チップは前記基
板とバンプを介して接続されてなることを特徴とする請
求項1または2記載の半導体装置。3. The first semiconductor chip is connected to the substrate by a thin metal wire, and the second semiconductor chip is connected to the substrate via a bump. The semiconductor device described.
属細線にて接続され、前記第2の半導体チップは前記基
板と表TAB実装にて接続されてなることを特徴とする
請求項1または2記載の半導体装置。4. The first semiconductor chip is connected to the substrate by a fine metal wire, and the second semiconductor chip is connected to the substrate by front-side TAB mounting. 2. The semiconductor device according to 2.
TAB実装にて接続され、前記第2の半導体チップは前
記基板とバンプを介して接続されてなることを特徴とす
る請求項1または2記載の半導体装置。5. The first semiconductor chip is connected to the substrate by back TAB mounting, and the second semiconductor chip is connected to the substrate via bumps. 2. The semiconductor device according to 2.
TAB実装にて接続され、前記第2の半導体チップは前
記基板と表TAB実装にて接続されてなることを特徴と
する請求項1または2記載の半導体装置。6. The first semiconductor chip is connected to the substrate by back TAB mounting, and the second semiconductor chip is connected to the substrate by front TAB mounting. Alternatively, the semiconductor device according to item 2.
ップを基板に直接実装する半導体装置の製造方法であっ
て、 前記第1の半導体チップは能動面の反対となる面を前記
基板の実装面と相対向するよう直接前記基板に実装され
る工程と、 前記第2の半導体チップは能動面を前記基板の実装面と
相対向するよう直接前記基板に実装される工程と、 を含んでなることを特徴とする半導体装置の製造方法。7. A method of manufacturing a semiconductor device in which at least first and second identical semiconductor chips are directly mounted on a substrate, wherein the first semiconductor chip has a surface opposite to an active surface mounted on the substrate. Mounting directly on the substrate so as to face the surface, and mounting the second semiconductor chip directly on the substrate so that the active surface faces the mounting surface of the substrate. A method of manufacturing a semiconductor device, comprising:
イヤボンディングにて接続され、前記第2の半導体チッ
プはフリップチップ実装にて接続されてなることを特徴
とする請求項7記載の半導体装置の製造方法。8. The semiconductor device according to claim 7, wherein the first semiconductor chip is connected to the substrate by wire bonding, and the second semiconductor chip is connected by flip chip mounting. Manufacturing method.
イヤボンディングにて接続され、前記第2の半導体チッ
プは前記基板と表TAB実装にて接続されてなることを
特徴とする請求項7記載の半導体装置の製造方法。9. The method according to claim 7, wherein the first semiconductor chip is connected to the substrate by wire bonding, and the second semiconductor chip is connected to the substrate by table TAB mounting. Of manufacturing a semiconductor device of.
第1の半導体チップを実装し樹脂封止した後、フリップ
チップ実装または表TAB実装を行うことを特徴とした
請求項8および請求項9記載の半導体装置の実装方法。10. The semiconductor device according to claim 8, wherein the first semiconductor chip is mounted by the wire bonding and resin-sealed, and then flip-chip mounting or table TAB mounting is performed. How to implement.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8120658A JPH09307056A (en) | 1996-05-15 | 1996-05-15 | Semiconductor device and method of manufacturing it |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8120658A JPH09307056A (en) | 1996-05-15 | 1996-05-15 | Semiconductor device and method of manufacturing it |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH09307056A true JPH09307056A (en) | 1997-11-28 |
Family
ID=14791696
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8120658A Pending JPH09307056A (en) | 1996-05-15 | 1996-05-15 | Semiconductor device and method of manufacturing it |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH09307056A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100354463B1 (en) * | 1998-03-26 | 2002-09-30 | 가부시끼가이샤 도시바 | Storage device, card-type storage device, and electronic device |
-
1996
- 1996-05-15 JP JP8120658A patent/JPH09307056A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100354463B1 (en) * | 1998-03-26 | 2002-09-30 | 가부시끼가이샤 도시바 | Storage device, card-type storage device, and electronic device |
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