JPH09306161A - Dynamic ram and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a new format DRAM (dynamic RAM) capable of coexisting with a conventional DRAM and high speed operation by clock control after the coexistence is ended. SOLUTION: A circuit generating an intra-bank XRAS becoming active for a prescribed period from a row address strode (XRAS) inputted from the outside by intra-bank controllers 111-114 of the DRAM having a plurality of banks A-D is provided. Memory access in its bank is performed independently of the external row address strobe by output enable (XOE), column address strobe (XCAS), etc., occurring between occurrence and stoppage of internal XRAS. Thus, pipe line control is made possible while making the coexistence with the conventional DRAM possible. At the point of time when the coexistence with the conventional DRAM is ended, the XCAS is used as a clock, and the DRAM is accelerated.

Description

Detailed Description of the Invention

[0001]

[0001] The present invention relates to a dynamic RA.
Regarding M (hereinafter referred to as DRAM) and its control method,
More specifically, the present invention relates to a DRAM that can be used together with a current-generation DRAM on a personal computer, and can be easily increased in speed when used alone, and a control method thereof.

[0002]

2. Description of the Related Art In a DRAM, the read / read
In order to increase the throughput at the time of writing (writing), the number of cases of adopting the burst transfer mode is increasing, and further, a DRAM having a plurality of banks has been proposed. Synchronous DRAM (hereinafter referred to as SDRAM) and Rambus D proposed as next-generation DRAM
A RAM or the like is given as an example having a plurality of banks. These require memory-only clock pulses to pipeline control multiple banks.

By the way, current generation DRAMs, for example,
In the fast mode DRAM, EDO mode DRAM, burst EDO mode DRAM, etc., the burst transfer mode is increasingly adopted, but unlike the SDRAM etc., it does not have a plurality of banks and is controlled by a clock. It does not read / write.
Therefore, for example, SDRAM and EDO mode DRAM cannot coexist as a main memory or an expansion memory on one personal computer.

[0004]

As described above, the fact that the current-generation DRAM and the next-generation DRAM cannot coexist on a personal computer means that the system and the DRAM are not compatible with each other.
Considering the combination of, it becomes a big problem for the semiconductor industry. For example, in order to mass-produce next-generation SDRAM capable of speeding up, this SDRAM is the supplier.
It is premised that a large number of personal computers that support the above are produced, but the production of a large number of personal computers of this type is premised on the supply of a large amount of SDRAM that meets the demand. And in general,
Commercial production of DRAM requires a large amount of capital investment and construction period, and it is extremely difficult from a business and time point of view to rapidly launch commercial production of SDRAM.

Therefore, in the process of migrating the DRAM to the next-generation format, the new-generation DRAM which can coexist with the current-generation DRAM on the personal computer and which has a plurality of banks and which can be speeded up easily. Appearance is desired. In this case, this new type of DRAM
In the future, where coexistence with current generation DRAMs has effectively ended, it is important that the product can be used alone on a personal computer that supports this type of DRAM to meet the required speedups.

In view of the above, the present invention is capable of coexisting with a current-generation DRAM on a personal computer and, when used alone, is a new type DRAM and its control which is easy to operate at high speed. The purpose is to provide a method.

[0007]

In order to achieve the above object, the dynamic RAM of the present invention has a plurality of memory cell arrays each including a plurality of memory cells designated by a set address including a first address and a second address. In a dynamic RAM formed in a bank, a bank decoder that detects one bank having a memory cell specified by the set address from an input set address, and an output of the bank decoder and an active first latch signal In-bank active signal generation section that generates an internal active signal for each bank in response to the transition of the first latch signal and stops the internal active signal after a lapse of a predetermined period after the transition of the first latch signal to inactive. A first latching a first address in response to the transition of the first latch signal to the active A dress latch circuit, a second address latch circuit for latching a second address in response to the activation of a second latch signal generated between generation and stop of the internal active signal, and generation of the internal active signal Detecting the transition to the active state of the second latch signal or the transition to the inactive state after the transition to the active state, which occurs between the stop and the stop.
An internal output enable signal generation unit for generating an enable signal, and a memory designated by the group address in response to transition of an active third latch signal generated after the generation of the internal output enable signal. And a data read circuit for reading data from the cell.

In the dynamic RAM of the present invention, the memory in a predetermined bank is preferably responsive to the transition of the first latch signal to active that occurs after the transition of the second latch signal to active. A refresh circuit for refreshing cells is further provided.

According to another aspect of the present invention, there is provided a method of controlling a dynamic RAM, wherein a dynamic RAM of the above type and a second dynamic RAM having a memory cell array forming a single bank are controlled by a common memory controller. The second dynamic R by the latch signal of 3
It is characterized in that the AM column address is latched.

Alternatively, the dynamic RAM control method of the present invention is characterized in that the third latch signal is supplied as a clock signal.

According to the dynamic RAM and the control method thereof of the present invention, it is possible to coexist with the DRAM of the present generation on a personal computer, and further, when the dynamic RAM of the present invention operates independently, the third latch signal is used as a clock. As a result, higher speed operation becomes possible as compared with the current generation DRAM.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the drawings, a DRAM of the present invention will be described.
Will be further described. FIG. 1 is a diagram illustrating a DR according to an embodiment of the present invention.
It is a block diagram of AM. The DRAM of this embodiment is
It has four banks, bank A, bank B, bank C, and bank D. Although the number of banks is four in this example, the number of banks is not limited to this example, and can be arbitrarily selected.
For example, the larger the number of banks is 8 or 16, the higher the performance in high-speed operation is.

In the DRAM 10 of this embodiment, first,
As a circuit common to banks A to D, a column address buffer 101 and a row address
It has a buffer 102 and a bank decoder 103,
Further, it has a control signal generation unit 104 that receives a control signal from the outside and generates an internal control signal. Further, a read driver 105 and a write receiver 106, which are connected to a data bus and exchange data with the data bus,
It has a read buffer 107 and a write buffer 108 for exchanging data between these and each bank. Each bank further includes in-bank controllers 111 to 114 for controlling each bank, column address decoders 121 to 124, and row address decoder 1 for each bank.
31 to 134, memory cell arrays 141 to 144, sense amplifiers 151 to 154, bit switches 161 to 16
4 and data latch & selectors 171 to 174 are provided. Although the above configuration itself is similar to that of the SDRAM, for example, the DRAM of the present embodiment has an SDR
The control signal generated by the control signal generation unit 104 and the in-bank controllers 111 to 114 is different from that of the AM.

The control signal generator 104 is a signal of the same type as the signal used in the conventional EDO mode DRAM, XRAS (row address strobe. Here, XRA).
S indicates that it is a RAS with an upper bar, and the symbol X will be used in the same manner hereinafter), XCAS (column address strobe), XWE (write enable), and XOE.
(Output enable) is received as an input signal. In the control signal generation unit 104 and the in-bank controllers 111 to 114 of the present embodiment, in particular, each time XRAS becomes active, the bank corresponding to the input address is operated based on the output of the bank decoder 103. Internal row address strobes (XRASA, XRASB, XRASC, XRAS
D) is activated, and read / write data is transmitted / received to / from the data bus after a lapse of a predetermined period after XOE becomes inactive.
Unlike a RAM or the like, a signal for refresh operation is different.

FIG. 2 shows a signal timing chart in the read operation of the DRAM of the above embodiment. In the figure, each burst signal having a burst length of 4 is output seamlessly as read data from the bank A, the bank B, the bank C, and the bank C, respectively. The occurrence time of each event is shown corresponding to T0 to T22. A read operation in the DRAM of the present embodiment will be described with reference to FIG.

First, the row address of the x-th row and the column address of the m-th column, which are the addresses (group addresses) in the bank A, are input from before time T0 to time T2, and externally at time T0. XRAS falls (becomes active, and so on). The in-bank controller in bank A learns that the address in bank A has been input by the output of the bank decoder which decodes the input address, and latches the output of this bank decoder in response to the fall of external XRAS. To do. That is, the row address strobe XRASA inside the bank A is activated for a predetermined period for the burst read operation. Subsequently, at time T2, the output enable XOE from the memory controller falls, and then immediately rises.

The input row address (x row) is XR
It is latched at time T0 at the fall of AS, and the column address (m columns) is latched at time T2 at the fall of XOE. Subsequently, XOE rises, and this rise is stored in the bank A controller. next,
At time T4, the column address strobe XCAS from the memory controller falls and the XOE
Is in the output enable state, data is read from the memory cell in the bank A designated by the address in response to this and is stored in the read buffer. Instead of the above, XOE
The output enable signal may be output at the falling edge of. The external XRAS is still under access at the bank A at time T3, but once rises to read the next address. The controller 111 in the bank A (FIG. 1) stores this rising edge of XRAS, and precharges the bank A when all the data of the burst length 4 is read into the read buffer 107.

After the address input in the bank A, the row address of the y-th row and the column address of the n-th column, which are the addresses in the bank B, are input from time T3 to time T6. At time T4, the external row address strobe XRAS falls again, and in response to this, the row address (y row) is latched, and at the same time, the row address strobe XRASB in bank B becomes active for a predetermined period. Furthermore, at time T6, output enable XO
E falls, and in response thereto, the column address of the nth column is latched. Then XOE rises and this rise is stored in the Bank B controller. Furthermore, when XCAS becomes active at time T8,
Since XOE has already risen and is in the output enable state, the data from the memory cell in bank B is read out and stored in the read buffer. Then, the bank B is precharged.

XRAS once becomes inactive at time T7 and becomes active again at next time T8. Between times T7 and T10, the row address of the z-th row and the column address of the p-th column, which are the addresses in the bank C, are input. These addresses are latched at the falling edges of XRAS and XOE as in the previous case. Further, when XOE rises and the subsequent XCAS falls, the data in the memory cell designated by the address in bank C is read out and read out to the read buffer.

Since the next address is the same row address in the same bank C as the preceding address, XRAS is not inactivated, and XRAS remains active from time T8 to T14. Become. As a result, the row address strobe X in the bank C is
The RASC is continuously active from time T8 to T16. As the input address signal, only the column address of the qth column is input, and this is latched at the falling edge of XOE. The data from the memory cell specified by this address is the XCA that follows the rising edge of XOE.
It is latched in the read buffer at the falling edge of S. Then, the precharge in the bank C is performed.

From the rising edge of XCAS following the falling edge of XCAS from which the data in bank A was read at time T4, the data latched in the read buffer is the continuous rising edge and rising edge of this XCAS corresponding to the clock. In response to the falling, it is sequentially output to the outside via the data bus. This is shown by the DQ signal. That is, four consecutive burst data x from bank A
Similar burst data yn including m1 to xm4
1 to yn4, zp1 to zp4, and zq1 to zq4 are sequentially output as the respective data from the bank B, the bank C, and the bank C. Note that in the present embodiment example, XCAS
Although the example in which the data is output by using both the falling edge and the rising edge of the above is given, a method of using only one of the falling edge and the rising edge is also possible instead.

As described above, the row address is latched at the falling edge of XRAS and the column address is latched at the falling edge of XOE in each bank controller. Conventional D
In the RAM, the column address is latched at the fall of XCAS, but in the above embodiment, the column address is latched at the fall of XOE. That is, the XCAS used in the EDO mode DRAM or the like corresponds to the XOE in this embodiment. This is the DR of this embodiment.
This is because in AM, it is considered that a memory controller supporting coexistence with a conventional DRAM can be easily manufactured by using XCAS as a clock. Instead of this, the address can be latched by a combination of XOE and XCAS.

FIG. 3 is a timing chart of read / write operations in the DRAM of this embodiment. In the figure, data is continuously written to banks A and B, then data is read from bank C, and then,
The case where data is written to the bank A is shown.
The write operation of the DRAM of this embodiment will be described with reference to FIG.

The row address of the X-th row in the bank A is input before the time T0, and the column address of the m-th column in the bank A is input between the times T1 and T2. XRAS at time T0
When is dropped, based on the input address,
Internal row address strobe XRASA in bank A
Becomes active. Until the time T8 when the writing of the bank A is completed, the bank A operates independently of the other banks due to the activation of XRASA. In this case, first, the row address of the Xth row is latched at time T0 at the falling edge of the external row address strobe XRAS, and then the column address of the m-th column is latched at time T2 at the falling edge of XOE. Then, since XWE falls, it can be seen that the memory operation is in the write mode. Furthermore,
XCAS falls, four consecutive burst data are sequentially output from the write buffer of bank A, and in response to consecutive rising and falling of XCAS,
The burst data is written to the addressed memory cell in bank A between times T5 and T8.

The external XRAS is accessing the bank A when the latching of the address in the bank A is completed.
It rises once at time T3 and then falls again at time T4. The addresses in row y and column n, which are the addresses in bank B, are input from time T3 to time T6. When XRAS falls again at time T4, internal XRASB
Becomes active based on the input address and the fall of XRAS, and remains in that state until time T12 when the write operation of bank B ends. Subsequently, burst data for bank B is written between the times T9 and T12 following the data writing of bank A in response to the rising and falling edges of XCAS.

After the address input in the bank B for writing, the row address of the z-th row and the column address of the p-th column, which are the addresses in the bank C, are for data read between the times T7 and T10. Entered in. The fact that the read mode has been entered is notified by the inactive state of the XWE, and the DRAM switches from the write mode to the read mode. When the mode changes like this, the next XC
Data from the bank C is sequentially read out from the fall of AS.

As shown in the timing charts of FIGS. 2 and 3, according to this embodiment, the pipeline operation is enabled by the fact that two or more banks are activated at the same time. In this case, the latency for the DRAM and the period for the precharge are hidden from the outside, thereby improving the throughput in the read / write operation. For this purpose, the in-bank controller creates an internal row address strobe in each bank from the external row address strobe, and the in-bank controller precharges the bank. By generating the internal row address strobe in the bank, the external row address strobe immediately rises immediately for the next operation and can be used for the next address latch. As shown in FIGS. 2 and 3, the active periods of XRASA, XRASB, and XRASC are different between the read time and the write time, respectively. This is because at the time of reading, precharge can be performed at the time when data is read to the read buffer.

FIG. 4 shows a timing chart of CBR (CAS Before RAS) refresh in the DRAM of the above embodiment. The output enable XOE is activated first, and then the row address strobe XRAS is activated. If XOE is already active and write enable XWE is inactive when XRAS falls, the row address of all banks indicated by the refresh counter inside the DRAM is refreshed. At the time of CBR refresh, the XOE and XCA are set on the system side in this way.
By causing S and SRAS to fall before the fall of XRAS, compatibility with the conventional DRAM for CBR refresh can be ensured.

FIGS. 5 and 6 respectively show the configuration of the bank decoder 103 and the internal row address / strobe generating circuit 20 of the in-bank controller and the signal timing chart thereof in the above embodiment. The input address ADRS is output by the bank decoder 103.
Which bank the address is in is detected, and the external row address strobe XRAS has its falling P
1 is detected by the first AND gate 23, and the rising edge P2 is detected by the second AND gate 24. When the AND gates 23 and 24 receive the rising or falling of XRAS, the pulse P3, which is turned on for a short time by the action of the delay gate 22 and the inverters 35 and 36,
P4 is generated respectively.

For example, when bank A is selected and XRAS falls (P1), the output of the first AND gate 23 becomes "1" for a short time (P3), and the third AN in bank A is output.
The output of the D gate 25 becomes "1" and the first flip-flop 26 is set. As a result, the output of XRASA becomes "0", that is, it becomes active. When the external row address strobe XRAS rises again (P
2), that fact is detected by the second AND gate 24 (P4), and the Q output of the first flip-flop 26 is "1".
Therefore, the second flip-flop 28 in the bank A is set via the AND gate 27 in the bank A. The output of the flip-flop 28 resets the first flip-flop 26 via the AND gate 29 when the burst operation period end signal BOEA is turned on (P8), so that the output of XRASA becomes "1". That is, it returns to inactive.

As described above, bank A responds to the fall (P1) of external row address strobe XRAS.
Internal row address strobe XRASA falls (P5), and then XRAS rises (P2).
Then, XRASA starts up after a predetermined period has elapsed (P6). Continuing, an example in which bank B is selected is shown in FIG. The same applies when another bank is selected. Burst operation period end signals BOEA (P8) and B
OEB (P9) is the falling edge of XRAS P1 and P, respectively.
It is a signal that is turned on for a short time after the elapse of a predetermined period T1, T2 from 7.

FIG. 7 shows a DRAM module (hereinafter referred to as MBED) of the above embodiment in a personal computer.
FIG. 3 is a system block diagram showing an example of coexistence of an O (MUlti Bank EDO) module) and a conventional burst EDO-DRAM module (hereinafter referred to as BEDO module). In the example of the figure, the MB is stored in the first slot 42.
The EDO module has a BEDO in the second slot 43.
Each module is mounted and the third slot 44 is empty. For example, the MBEDO module has a capacity of 16 megabytes (MB) and the BEDO module has 8
It has a capacity of MB. MBEDO module and BEDO
The presence of the memory controller 41 that supports the coexistence allows the module to coexist in this way.

DRAM modules are generally provided with an ID code indicating the attributes of the module. In the above example, the CPU (not shown) reads the ID code immediately after turning on the power and sets the information in the register in the memory controller 41. Memory controller 4
1 corresponds to each slot 42, 4 depending on the contents of this register.
It outputs the timing pulse necessary for the DRAM module mounted in No. 3. Data DQ is transmitted / received from / to the slots 42 to 44 from the memory controller 41 via the data bus 45, and external row address strobes XRAS1 to XRAS3 are individually provided to the slots.
A memory address ADRS, a column address strobe XCAS, an output enable XOE, and a write enable XWE common to all slots are supplied. Further, the ID signals ID1 to ID3 are individually input from the respective slots 42 to 44 to the CPU via the memory controller 41.

FIG. 8 is a timing chart showing an example of the read operation in the above system. The figure shows an example in which the MBEDO module is selected first and then the BEDO module is selected respectively, and subsequently, both CBR refreshes are simultaneously performed. The clock of the CPU is, for example, 50 MHz, and the time is displayed for each cycle on the drawing. Also, bank 1 (and XRAS1)
To the MBEDO module, bank 2 (and XRAS
2) corresponds to the BEDO module, respectively.

From the CPU, when the address strobe (XADS) falls at time T0, the time T0
, And the address is sent at T1. The address in the MBEDO module means that the address Ad is 0MB ≦ Ad <16MB in the decoder in the memory controller.
To be detected. As a result, MBEDO
External row address strobe XR for module
AS1 falls for a predetermined period. The entered address is
The row address X row is latched by the fall of XRAS1, and the column address m column is latched by the fall of XOE. The data from the memory cell addressed by the address in the MBEDO module is latched in the read buffer on the first falling edge of XCAS and then responds to the four consecutive rising and falling edges of XCAS following this falling edge. And sequentially read out.

At time T10, the CPU again returns to XA.
Since the falling edge of DS and the next address are output, and the output address Ad is 16 MB ≦ Ad <24 MB in the decoder in the memory controller,
It is detected that the address is in the BEDO module. This causes the external row address strobe XRAS2 for the BEDO module to fall. Subsequently, XOE falls, and further, the fall and rise of XCAS having a half cycle of the previous XCAS are output from the memory controller. The row address y row is latched by the fall of XRAS2, and the column address n column is latched by the fall of XCAS following the fall of XRAS2. The burst data from the memory cell specified by this address in the BEDO module is XCAS following the falling edge of XRAS2.
Are read out in response to four consecutive falling edges of XCAS following the falling edges of.

The memory controller periodically performs a CBR refresh operation within its module. First, M
XOE for refreshing the BEDO module,
XCAS is turned off to refresh the BEDO module. Then, by simultaneously deactivating XRAS1 and XRAS2, CBR refresh is performed in both the MBEDO module and the BEDO module. Thus, first, XCAS and X
Since CBR refresh is performed when the external row address strobes XRAS1 and XRAS2 are activated after OE is activated,
Both the MBEDO module and the BEDO module can be controlled by a common memory controller.

9 and 10 respectively show D of the above-mentioned embodiment.
C for controlling RAM (MBEDO module)
7 shows a timing chart of a read operation optimized by the frequency of the PU clock.

In FIG. 9, the clock frequency is 100, for example.
In MHz, therefore the frequency of XCAS is 50 MHz and the active period of XOE is one clock period. First, the row address x row in bank A is latched by the fall of XRAS at time T1, and the column address m column in bank A is latched by the fall of XOE at time T3. Continuously, time T5
The row address y row in the bank B is latched by the fall of XRAS, and the column address n column in the bank B is latched by the fall of XOE at time T7.

Data from the addressed memory cell in bank A is read into the read buffer on the falling edge of XCAS following the first falling of XOE and then on the rising and falling edges of XCAS. Output from the read buffer to the outside. Further, the data from the addressed memory cell in bank B is first read to the read buffer at the falling edge of XCAS following the falling edge of XOE for the second time, and then to the consecutive XCAS subsequent thereto. It is output to the outside at the rising and falling edges of. In this example, the first X
As the elapsed time from the fall of RAS to the start of data output to the outside of the memory, so-called access time t _RAC , t _RAC = 60 ns is obtained.

The timing chart of FIG. 10 shows that the XOE active period is 3 clock cycles.
Different from the example. In this example, for example, the clock cycle is 1
50MHz, therefore the period of XCAS is 75MH
z. According to this control method, the access time t _RAC
As a result, 53 ns is obtained. Other points are the same as those in FIG. 9, and detailed description thereof will be omitted.

Generally, the DRAM access time t _RAC is determined by the design rule regarding the wiring width. In the example of FIGS. 9 and 10, as described above, the output of the read data is started from the pulse following the first fall of XCAS after the rise of XOE. For example, in FIG.
In this example, this DR is based on the 0.5 μm design rule.
If an AM is manufactured and the access time is 60 ns, 10
Operation up to 0 MHz is possible. Further, in the example of FIG. 10, the access time is set to 50 ns, and further, by extending XOE up to 3 clock cycles, high speed operation of about 150 MHz becomes possible. Since it is possible for the system side to extend the XOE up to 3 clock cycles, the DRAM of the above-described embodiment can be provided with 15 options without adding any options.
Supports up to 0MHz.

FIG. 11 shows the DR of the above embodiment of the present invention.
The timing chart of the read operation at the time of controlling only AM at high speed is shown. In this figure, an example is shown in which clock operation is performed like the SDRAM proposed in the past. XCAS constitutes a clock for controlling the DRAM of the present embodiment, and is supplied from the system at a frequency of 100 MHz, for example. This corresponds to a CPU clock frequency of 200 MHz. In this embodiment, the CAS latency is 2 clock cycles. X
RAS becomes active during time T1 to T3 and time T5 to T7, respectively, and XOE indicates time T3 to
It becomes active during T5 and between times T7 and T9.

Row address x row in bank A is XRAS
The first falling edge of the column address m is latched at time T1, and the column m of the column address is latched at the first falling edge of XOE at time T3. Next, row address y in bank B
The row is at time T5 due to the next fall of XRAS, and the column address n is at time T5 due to the next fall of XOE.
7 are latched respectively.

Data from the memory cell in the addressed DRAMA follows the rising edge of XOE 2
In response to the falling edge of XCAS for the second time, it is latched in the read buffer at time T9 and continues from time T10.
During the clock cycle, it is output from the read buffer to the outside in response to four consecutive rising and falling edges of XCAS. Subsequently, the data from the memory cells in bank B are similarly output. In this case, the first XRA
The first data is output after t _RAC = 50 ns after the fall of S. Thus, in the present embodiment example, X
By using CAS as a memory-dedicated clock, high-speed operation similar to that of the next-generation SDRAM currently proposed is possible.

FIG. 12 shows another timing chart in the read operation of the DRAM of the above embodiment. 12 differs from the example of FIG. 11 in that the CAS latency is set to 3. In this case, the data from the addressed memory cell is read into the read buffer in response to the third falling edge of XCAS following the first rising edge of XOE (time T6), then the next It is output to the outside from the rising edge of XCAS. According to this control method, the clock frequency of the CPU can be up to 250 MHz, so that X
As a CAS frequency, high-speed operation of 125 MHz becomes possible. In this case, the access time t _RAC = 48 ns is obtained.

In the example of FIGS. 11 and 12, the option of counting XCAS is required in the DRAM of the above embodiment. For example, the SDRAM proposed so far requires five options of CAS latency of 0, 1, 2, 3, 4 with a clock up to 150 MHz. Therefore, the necessity of the option in the above embodiment does not cause a big problem. And one
Up to 50MHz can be supported without options.

In FIG. 11, since the read data is output to the outside from the pulse next to the fall of the second XCAS after the rise of XOE, the access time t _{RAC is set} to 50 ns as described above. It is possible to operate up to a clock frequency of 200 MHz. Also,
In FIG. 12, the third XCA after XOE has started up.
Since the read data is output to the outside from the pulse next to the falling edge of S, the access time t _RAC is 45 ns, and the operation up to the clock frequency of 250 MHz is possible.

Although the present invention has been described based on its preferred embodiment, the DRAM of the present invention is not limited to the configuration of the above-described embodiment, and various configurations from the above-described embodiment are provided. DRAM that has been modified and changed,
It is included in the scope of the present invention.

[0050]

As described above, the DRAM of the present invention
According to the above, the coexistence with the conventional DRAM is possible, and at the time when the coexistence is practically completed, high-speed operation is possible according to the characteristics, which is a remarkable effect of facilitating the start of commercial production of the DRAM. Play.

[Brief description of drawings]

FIG. 1 is a block diagram of a DRAM according to an embodiment of the present invention.

FIG. 2 is a timing chart in a read operation of the DRAM of FIG.

3 is a timing chart in a read / write operation of the DRAM of FIG.

FIG. 4 is a timing chart in CBR refresh of the DRAM of FIG.

5 is a block diagram of a row address / strobe generation circuit in a bank of the DRAM of FIG.

6 is a timing chart of signals in the row address / strobe generation circuit of FIG.

FIG. 7 is a block diagram of a system for controlling the DRAM of the embodiment of FIG. 1 and a conventional burst EDO mode DRAM module.

8 is a timing chart of signals in a read operation of the system of FIG.

9 is an example of a timing chart in a read operation of the DRAM of the embodiment example of FIG. 1;

10 is another example of a timing chart in the read operation of the DRAM of the embodiment example of FIG.

11 is an example of a signal timing chart showing an example of high-speed operation of the DRAM of the embodiment example of FIG. 1;

12 is another example of a signal timing chart showing an example of high-speed operation of the DRAM of the embodiment example of FIG.

[Explanation of symbols]

10 DRAM 101 Column address buffer 102 Row address buffer 103 Bank decoder 104 Control signal generation unit 105 Driver 106 Receiver 107 Read buffer 108 Write buffer 111 to 114 In-bank controller 121 to 124 Column address decoder 131 to 134 Row address decoder 141 to 144 Memory array 151 to 154 Sense amplifier 161 to 164 Bit switch 171 to 174 Data latch & selector 20 Bank internal row address / strobe generator 22 Delay gate 23, 24, 25, 27, 29, 30, 32, 34 A
ND gate 26, 28, 31, 33 Flip-flop 35, 36 Inverter 41 Memory controller 42-44 Slot 45 Data bus

Claims (4)

[Claims] 1. A dynamic memory system comprising: a memory cell array comprising a plurality of memory cells each comprising a plurality of memory cells each designated by a set address comprising a first address and a second address;
In AM, in response to a bank decoder that detects a bank having a memory cell specified by the group address from an input group address, and an output of the bank decoder and a transition of the first latch signal to active. An internal active signal generator for generating an internal active signal for each bank, and stopping the internal active signal after a lapse of a predetermined period after the transition of the first latch signal to inactive; and the first latch. A first address latch circuit that latches a first address in response to the transition of the signal to the active state; and an active state of a second latch signal that occurs between generation and stop of the internal active signal. A second address latch circuit for latching a second address, and before the generation of the internal active signal between generation and stop An internal output enable signal generation unit for generating an internal output enable signal by detecting a transition of the second latch signal to active or a transition to inactive after the transition to active, and the internal output And a data read circuit for reading data from the memory cell designated by the group address in response to the transition of the third latch signal to the active state after the generation of the enable signal. . 2. A refresh circuit for refreshing memory cells in a predetermined bank in response to a transition of the first latch signal to an active state, which occurs after the transition of the second latch signal to an active state. The dynamic DRAM according to claim 1, further comprising: 3. The dynamic R according to claim 1 or 2.
AM and a second dynamic RAM having a memory cell array forming a single bank are controlled by a common memory controller, and a column address of the second dynamic RAM is latched by the third latch signal. A characteristic dynamic RAM control method. 4. The dynamic R according to claim 1 or 2.
A method for controlling an AM, wherein the third latch signal is supplied as a clock signal, which is a method for controlling a dynamic RAM.