JPH09305564A - Inter-arithmetic unit synchronizing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inter-arithmetic unit synchronizing system by which any arbitrary arithmetic units can be synchronized at high speed among plural arithmetic units connected with a multistage network. SOLUTION: When a synchronizing packet is issued, arithmetic units 11-14 set values at positions corresponding to synchronizing numbers inside tables. Corresponding to this synchronizing packet, synchronizing processing is performed on cross bar switches 16-19 consisting of a multistage network 15, and the synchronizing packet arrives at the arithmetic units related with that synchronizing processing. The cross bar switches 16-19 have tables in a certain size as well. In the case of performing the synchronizing processing among J pieces of ports at a certain switch, each time the synchronizing packet having the same synchronizing number arrives from any one of J pieces of ports, the value of the table at that switch is updated and when the final synchronizing packet arrives and the value of the table is updated, the switch copies out this packet to L pieces of output ports designated inside the packet (arbitrary L pieces of output ports among M pieces of outputs).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization system between arithmetic devices, and more particularly to a synchronization system between arbitrary arithmetic devices among a plurality of arithmetic devices connected by a network.

[0002]

2. Description of the Related Art Conventionally, only the synchronous processing between all the arithmetic units constituting a system connected by a network or a group of certain arithmetic units determined by the shape of the network was supported by hardware.

For example, in Japanese Unexamined Patent Publication No. 4-236657, a plurality of arithmetic units (processors) are divided into a number of subgroups, which are connected in a tree structure, and synchronization is performed in subgroup units and the entire system. The method of taking is described.

Further, in Japanese Patent Application Laid-Open No. 2-90357,
A method for connecting a processor to a tree structure and performing high-speed synchronization within a range according to the structure is described. JP-A-2-1
Japanese Patent No. 10742 describes a method of using an AND gate to achieve high-speed synchronization among all processors.

Further, in Japanese Unexamined Patent Publication No. 1-241662, when the highest-level processor detects the output of a synchronization point arrival signal with a specific synchronization point identifier, the standby release signal with the synchronization point identifier is sent to all lower processors. A high-speed synchronization method among all processors using a broadcasting function is described, which enables inter-processor synchronization with respect to a plurality of synchronization points by broadcasting. Further, Japanese Laid-Open Patent Publication No. 62-232065 describes a method in which processors are divided into groups and an open collector is used to connect them to perform synchronization between the groups.

[0006]

However, all of the above-mentioned conventional inter-arithmetic-device synchronization methods are synchronization methods between specific processors (arithmetic devices), and synchronization between arbitrary arithmetic devices cannot be performed at high speed. There is a problem.

[0007] The present invention has been made in view of the above points,
An object of the present invention is to provide an inter-arithmetic-device synchronization method capable of realizing high-speed synchronization among arbitrary arithmetic devices among a plurality of arithmetic devices connected by a multistage network.

It is another object of the present invention to provide an inter-arithmetic-device synchronization method in which each arithmetic device completes a synchronization process by transmitting a synchronization packet at most once.

[0009]

In order to achieve the above object, the present invention provides a transmitting / receiving unit for a synchronization packet having a synchronization number, a plurality of arithmetic units having at least a selection unit for selecting a received synchronization packet, and N units each. It consists of K stages of crossbar switches having N input ports and M output ports (N, M, and K are integers of 2 or more), and each input port of the first stage crossbar switch is connected to a plurality of arithmetic units. The final stage crossbar switch is provided with a multistage network that outputs packets to a designated arithmetic device among the plurality of arithmetic devices, and the plural arithmetic devices pass through which crossbar switch of the K stage crossbar switch. A synchronization packet including information specifying whether to transmit is issued, and the received synchronization packet is selected from the value by the selection means, and the K-stage of the multistage network is selected. Each crossbar switch has a table, refers to the table from the synchronization number value of the input synchronization packet, updates the table value from the reference value, and discards the synchronization packet input from the updated value. Alternatively, it is configured to output to the next stage.

According to the present invention, in a parallel computer in which a plurality of arithmetic units connected by a multi-stage network are connected, each crossbar switch forming the multi-stage network performs a synchronization process.
It is assumed that each arithmetic device issues a synchronization packet in synchronization processing and knows that synchronization has been established by receiving the synchronization packet.

The crossbar switches that make up the multistage network are N
It has M input ports and M output ports. Each sync packet determines which of the N input ports in each crossbar switch performs the synchronization process, and which of the M output ports outputs the sync packet when the synchronization is established. The output is specified.
Also, a synchronization number is specified for each synchronization packet,
In each crossbar switch, synchronization processing is performed only between packets having the same number. For this reason, each crossbar switch has a table of a size corresponding to the number of synchronization numbers.

Of the N input ports of a switch, J
Consider a case in which synchronization processing is performed between the input ports. Sync packets arriving from J input ports must have the same sync number. In the processing of the packet that first arrives at the switch among the J input ports, the table is set to which input port the synchronization packet will arrive from. The information for this is specified in the sync packet. This sync packet is discarded at this switch.

Thereafter, every time a sync packet having the same sync number arrives from any of the J input ports,
The value in the table is changed (updated). These sync packets are also discarded at this switch. When the last sync packet arrives and the value in the table is updated, it knows that the sync packet has arrived from all J input ports, so the switch sends this packet to the L output ports specified in the packet. Duplicate (output any L in M output) and output. By repeating this process at each stage of the multistage network, the synchronization process is realized by the network.

The arithmetic unit that issues the synchronization packet also has a table of a size corresponding to the number of synchronization numbers.
Each arithmetic unit sets the value of the position corresponding to the synchronization number in this table when the synchronization packet is issued. The synchronization packet is used to perform the synchronization processing as described above on the switches forming the multistage network, and the synchronization packet arrives at the arithmetic unit associated with the synchronization processing.

Depending on the designation of the input port for the synchronization processing in the synchronization packet and the output port for duplicating and outputting the synchronization packet, the arithmetic units not participating in the synchronization processing (not issuing the synchronization packet) may also be used. Sync packets may arrive. When the synchronization packet arrives, the arithmetic unit refers to the value at the position corresponding to the synchronization number in the table, and if it is set, receives it as a synchronization packet and resets the value in the table. If the table value is not set, the synchronization packet that arrived is discarded.

As described above, according to the present invention, by designating the synchronization number of the arrived synchronization packet in each crossbar switch that constitutes the multistage network, the synchronization packet can be waited for and duplicated in the crossbar switch. . Further, according to the present invention, each arithmetic unit discards the synchronization packet having the synchronization number which is not issued by itself by the discarding means.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an overall configuration diagram of an embodiment of the method of the present invention. Four arithmetic units (arithmetic units 11, 12,
13, 14) are connected by a multistage network 15. The multistage network 15 has two input ports (N = 2) and four output ports (M = 2), four crossbar switches 16, 17, 18, and 19 to form a two-stage (K = 2) switch. It is configured. In FIG. 1, data lines 100, 101, 102, 103 which are outputs from the multistage network 15
Are connected to the input ports (IN) of the arithmetic units 11, 12, 13, and 14, respectively.

FIG. 2 shows an example of the format of a packet transmitted / received between arithmetic units. Packet has header 2
1 and a data field 22. One is used for data transfer between arithmetic devices and the other is used for synchronization processing between arithmetic devices, and is distinguished by the value of "TYPE" in FIG.

The values T1, T2 ,. . . ,
Tn is used for routing at each stage of each crossbar switch that constitutes the multistage network 15. For example, in the switches 16 and 17 of the first stage in FIG. 1, the value of T1 is used to determine which of the two output ports O1 and O2 is to be output. The switches 18 and 19 in the second stage use the value of T2 to determine which output port to output to. Similarly, the k-th switch in the multi-stage network uses the value of Tk to determine which output port to output to. Further, in each stage, it is possible to output to a plurality of output ports simultaneously, and this designation is also made for T1, T2 ,. . . , Tn.

"SID" in the header 21 shown in FIG. 2 is a field for designating a synchronization number when performing a synchronization process. A synchronization process is performed between packets having the same synchronization number. The values F1, F2 ,. . . , Fn
Is used to specify which input port is to be used for synchronization when the synchronization process is performed by the switches in each stage. For example, the first-stage switch 1 in FIG.
6 and 17 use the value of F1 to generate two input ports Il and I
Specifies whether or not to perform synchronization processing between packets arriving from 2.

FIG. 3 is a block diagram showing an example of the arithmetic unit 11 shown in FIG. In the figure, the arithmetic unit 11 is a FIFO 3
0, 31, arithmetic unit 32, control device 33, and table 34
It is composed of The arithmetic unit 32 is a unit that performs arithmetic operations, and packets are transmitted to the FIFO 31 from here. After the packet is input to FIFO31 once,
Output to network. The packet sent from the network is received by the FIFO 30, and the arithmetic unit 32
Passed to. The controller 33 controls transmission / reception while exchanging information with the arithmetic unit 32. The table 34 is used when performing synchronization. Other arithmetic devices 12 to 14 of FIG.
Also has the same configuration as in FIG.

FIG. 4 is a block diagram showing an example of the crossbar switch 16 shown in FIG. The crossbar switch 16 is FI
The FO 41 and 42, the buffers 43 to 46, the control device 47, and the table 48 are included. The packet sent to the crossbar switch 16 is first sent to the FIFO 41.
Alternatively, it is input to the FIFO 42. The control device 47 is
The value T of the header of the packet in the FIFO 41 or 42
1, T2 ,. . . , Tn, which output port O
1, decides whether to send a packet to O2. The output port to which the data is sent is controlled by selectively turning on / off the buffers 43 to 46 by the output of the control device 47.

For example, from the data line 104 to the FIFO 41
When outputting the packet sent to the output port O2 (data line 107), the buffer 45 is turned on,
At the same time, the buffer 46 is turned off. In addition, the FIFO41
Packets sent to both output ports O1, O2
When sending to (data lines 106 and 107), both buffers 43 and 45 are turned on and buffers 44 and 46 are turned off. The table 48 is used to perform the synchronization processing. Other crossbar switches 17 to 19 in FIG.
Also has exactly the same configuration as in FIG.

FIG. 5 is a block diagram of another example of the crossbar switch 16 in FIG. In FIG. 5, the crossbar switch 16 includes FIFOs 121 to 124 and a selector 125.
And 126, control devices 127 and 128, and tables 129 and 130. In FIG. 5, the packet arriving from the input port I1 is first F
It is input to both the IFOs 121 and 123. Control device 1
27 and 128 refer to the value in the header of the packet (the value of Tk for the switch at the kth stage), and when the output destination of the packet is the output port O1, the packet that has arrived at the FIFO 121 becomes valid, FI by Seretaku 125
The FO 121 is selected and output to the output port O1. F
The packet arriving at the IFO 123 is discarded. If the output destination of the packet is the output port O2, the FIFO
The packet arriving at 121 is discarded and the FIFO 123 is
Only the packet that arrives at
The FIFO 123 is selected by and output to the output port O2.

Similarly, the packet arriving from the input port I2 is first input to both the FIFOs 122 and 124. Then, the control devices 127 and 128 refer to the value in the header of the packet (the value of Tk for the switch at the kth stage), and when the output destination of the packet is the output port O1, the packet that has arrived at the FIFO 122 is It becomes effective,
It is selected by the selector 125 and output to the output port O2. The packet arriving at the FIFO 124 is discarded. If the output destination is the output port O2, the FIF
The data arriving at O122 is discarded, and the FIFO124
The data arriving at is selected by the selector 126 and sent to the output port O2. The tables 127 and 128 are used for synchronization processing.

Next, how a packet for data transfer is transmitted will be described. In FIG. 1, it is assumed that data is transmitted from the arithmetic unit 11 to the arithmetic unit 13.

The packet transmitted from the arithmetic unit 11 is
It is sent to the crossbar switch 16 by the data line 104. In the example shown in FIG. 4, the packet is first sent to the FIF.
Input to O41. The control device 47 refers to the value T1 in the header of the packet in the FIFO 41, and determines which output port O1, O2 (data line 106,
107) decide whether to send the packet. In this case, the packet is sent to the output port O2 (data line 107). For this purpose, the control device 47 turns on the buffer 45 and turns off the buffers 43 and 46.

On the other hand, when the crossbar switch 16 has the configuration shown in FIG. 5, the packet is first input to the FIFOs 121 and 123 in the crossbar switch 16. The control devices 127 and 128 refer to the value T1 in the header to know that the output destination is the output port O2 (data line 107). The control device 128 selects the packet arriving at the FIFO 123 with the selector 126 and sends it to the output port O2 (data line 107). On the other hand, the control device 127 discards the packet arriving at the FIFO 121.

The crossbar switch 19 sends the packet to the arithmetic unit 13 via the data line 102 in the same manner as the crossbar switch 16. However, the control device in the crossbar switch 19 uses the value T2 in the packet header.
To determine the output destination port. When receiving the packet, the arithmetic unit 13 of FIG. 1 transfers the data in the packet to the arithmetic unit corresponding to the arithmetic unit 32 of FIG.

As described above, the first-stage switches (crossbar switches 16 and 17 in FIG. 1) in the network refer to the value T1 in the packet header to determine which output port the packet should be sent to, and the second stage switch. The eye (in FIG. 1, the crossbar switches 18 and 10) refers to the value of T2 to determine which output port the packet is to be sent to. When the number of stages of the network is larger, the k-th stage switch determines to which output port the packet is to be sent out by the value of the value Tk in the packet header.

Next, a procedure for transferring data from a certain processor to a plurality of processors will be described. It is assumed that the arithmetic unit 11 of FIG. 1 sends packets of the same content to the arithmetic units 11, 12, 13, and 14.

The packet sent from the arithmetic unit 11 is first sent to the crossbar switch 16. In the example shown in FIG. 4, this packet is first input to the FIFO 41 in the crossbar switch 16. Next, the control device 47 refers to the value T1 of the packet header in the FIFO 41. Since it is understood from this value that the output should be output to both output ports, the drivers 43 and 45 are turned on and the drivers 44 and 46 are turned off.
Thus, the data input to the FIFO 41 is output to both the output port O1 (data line 106) and the output port O2 (data line 107).

On the other hand, in the case where the crossbar switch 16 is the example shown in FIG. 5, the packets sent from the arithmetic unit 11 are input to the FIFOs 121 and 123, respectively.
The controllers 127 and 128 refer to the value T1 in the packet header from the FIFO 121 and 123. From this value, it can be seen that the packets must be output to both output ports, so neither controller 127, 128 discards the packet. Therefore, the packet arriving at the FIFO 121 goes to the output port O1 (data line 106) via the selector 125, and the packet arriving at the FIFO 123 goes to the output port O2 (data line 107) via the selector 126. Sent out.

As a result, the packet is transmitted to the crossbar switch 18 of FIG.
1 to the crossbar switch 19 of FIG.
The crossbar switches 18 and 19 perform the same processing as that of the crossbar switch 16, so that the packets are sent to the arithmetic units 11, 12, 13, and 14 via the data lines 100, 101, 102, and 103.

Next, the case where the synchronization processing is performed among the arithmetic units 11, 12, 13, and 14 will be described. Arithmetic unit 1
1, 12, 13, and 14 respectively send a synchronization packet. The fact that the packet is a synchronization packet is indicated by the value of TYPE in the packet header. The same synchronization number S is used as the synchronization number for each synchronization packet.
Are assigned by the arithmetic units of the arithmetic units 11, 12, 13, and 14.

First, in the arithmetic unit 11, when transmitting this synchronization packet, the control unit 33 sets the value of the position corresponding to the synchronization number S in the table 34. It is assumed that the values in the table 34 have been reset in advance. If you try to send a sync packet,
When the value of the position corresponding to the synchronization number S in 4 is set, the control device 33 takes some action such as exception processing.

When the arithmetic unit 11 receives the synchronization packet, the control unit 33 refers to the synchronization number S in the packet header and the value in the table 34 corresponding to the synchronization number S. If this value is set, packet reception processing is performed. When the value in the table 34 is not set, the control device 33 discards the arrived synchronization packet because the arithmetic device has not issued the synchronization packet (not participating in the synchronization processing).

Next, the processing performed by the crossbar switch 16 will be described with reference to the example shown in FIG. First, it is assumed that the packet arriving from the arithmetic unit 11 to the FIFO 41 is processed by the control unit 47. Sync packet is F
When arriving at the IFO 41, the controller 47 refers to the value F1 in the packet header. F1 designates from which input port the synchronization packet to arrive and the synchronization process are to be performed.

When it is not designated to perform the synchronization process with the synchronization packet from any port, the output is performed to the output port designated by the value T1 in the packet header, like a normal packet. When it is designated to perform the synchronization process, the synchronization number S in the packet header is referred to, and the value corresponding to the synchronization number S in the table 48 is referred to.

The table 48 has the same number of input ports as 2
It is assumed to be a bit width. If the value is "00", the controller 47 sets the bit at the position corresponding to the input port designated by the value F1 in the packet header. However, the bit corresponding to the port number that arrived by itself is reset. In this case, F1 is "1"
1 "is designated and the process is for a synchronization packet that has arrived at the input port I1, so the first bit of the 2-bit value corresponding to the synchronization number S in the table 48 is reset and the value"
01 ”is written (updated) in the table 48.
This synchronization packet that has arrived at the FIFO 41 is discarded because the value before update corresponding to the synchronization number S in the table 48 is "00".

In general, when there are L input ports, the bit at the position corresponding to the input port for which the arrival of the synchronization packet is waited is set to "1", and the position of the port corresponding to the port not related to the synchronization processing is set. Set the bit to "0". How to set this bit is specified by the value of F1 in the packet header.

Further, the width of the table 48 can be set to logL bits. In this case, rather than designating from which input port the arrival of the synchronization packet is to be waited for, the number of packets required to establish the synchronization-1 is set. This value is also specified by the value F1 in the packet header. In this case, since the number of inputs is 2, and the arrival of one more synchronization packet is required, the bit width of the table 48 is 1, and the value is set to "1".

Next, it is assumed that the synchronization packet from the arithmetic unit 12 arrives at the FIFO 42. When the synchronization packet arrives, the control device 47 refers to the synchronization number S in the packet header and the value corresponding to the synchronization number S in the table 48. If this value is not "00", the bit corresponding to the input position is reset to "0". In this case, since it is the processing of the synchronization packet that has arrived at the FIFO 42 from the input port I2, the second bit of the value of the position corresponding to the synchronization number S in the table 48 corresponding to the input position is set to "
Update to 0 ".

If the updated result of the table 48 is not "00", the control unit 47 discards the arrival synchronization packet because the synchronization packet arriving at the FIFO 42 is not the last synchronization packet to be synchronously processed. If the result after updating the table is "00", it indicates that the packet arriving at the FIFO 42 has arrived from all of the two input ports. A packet is output with reference to the value T1 of the transmission destination.

In this case, the value T in the packet header
Since it is designated to output to both the output ports O1 and O2 by 1, the buffers 44 and 46 are controlled to the on state and the drivers 43 and 245 are controlled to the off state, respectively, and the synchronization packet is output to the output ports O1 and O2. It is output and sent to the crossbar switches 18 and 19.

When the table 48 has a log L bit width (1 bit in this case), when the synchronization packet arrives at the FIFO 42, the control device 47 refers to the synchronization number S in the packet header and refers to the table 48 in the table 48. The value corresponding to the synchronization number S is reduced by "1". If this value is not "0", the packet is discarded. If this value becomes "0", refer to the value T1 of the destination in the packet header,
Output to the output port specified by the packet header in the same manner as above.

The same processing is performed in the crossbar switch 17, and the synchronization packet is transmitted to the crossbar switch 18,
Sent to 19. The crossbar switches 18 and 19 also perform the same processing as the crossbar switch 16, and the synchronization packet is sent to the arithmetic units 11, 12, 13, and 14 via the data lines 100, 101, 102, and 103.

Next, the operation of the crossbar switch 16 in the configuration example shown in FIG. 5 will be described. First, the synchronization packets from the arithmetic unit 11 are transferred to the FIFOs 121 and 123.
Suppose you have arrived at. When the control devices 127 and 128 know that the synchronization packet has arrived, they refer to the value of the transmission destination T1 in the packet header. In this case, output port O
Since it is specified to output to both 1 and O2,
Both data of the FIFOs 121 and 123 are stored in the control device 12.
7,128. Each control device 127, 1
28 refers to the synchronization number S in the packet header, refers to the value of the position corresponding to the synchronization number S in the tables 129 and 130, and performs the same processing as the example shown in FIG.
Perform on 9,130. After this, the FIFO 121,1
The sync packet in 23 is discarded.

Then, the synchronization packet from the arithmetic unit 12 arrives at the FIFO 122, 124. The destination T1 of the header of the synchronization packet that arrived is both output ports O
1 and O2 are specified, the arithmetic units 127 and 128 do not discard these packets,
The same processing as that described in the example of FIG. 4 is performed on the table. As a result, the control device 127 selects the synchronization packet arriving at the FIFO 122 with the selector 125 and outputs it to the output port O1. Further, the control device 128 uses the FIF
The selector 126 selects the synchronization packet arriving at O124 and outputs it to the output port O2. As a result, the synchronization packet is output to both output ports O1 and O2.
Similar processing is performed in the other crossbar switches 17, 18, and 19, and the synchronization packet is sent to the arithmetic units 11, 12, 13, and 14.

The synchronization packet arriving at the arithmetic unit 11 is
First, it is input to the FIFO 30 of FIG. Control device 33
If the arriving packet is a synchronization packet, refers to the synchronization number S in the packet header, and refers to the value of the position corresponding to the synchronization number S in the table 34. If this value has already been set, the control device 33 notifies the arithmetic unit 32 of the arrival of the synchronization packet. If the value in the table 34 is not set, the control device 33
Discards the arrived synchronization packet. In this case, since the value of the position corresponding to the synchronization number S in the table 34 is set, the synchronization packet is passed to the arithmetic unit 32.
Thereby, the calculation unit 32 knows that the synchronization is established.

The same processing is performed in the other arithmetic units 12, 13, and 14.

Next, the case where the synchronization processing is performed among the arithmetic units 11, 13 and 14 will be described.

The synchronization packet having the synchronization number S is sent from the arithmetic unit 11 to the crossbar switch 16. In this synchronization packet, output to both output ports O1 and O2 is designated by the value T1 in the packet header. Further, the value F1 in the packet header does not specify queuing. So this packet
Immediately copied and sent to the crossbar switches 18 and 19.

From the arithmetic units 13 and 14, the synchronization packet having the synchronization number S is sent to the crossbar switch 17, and the above processing is performed. As a result, the synchronization packet is sent to the crossbar switches 18 and 19, and the crossbar switches 18 and 19 also perform the same processing as the above synchronization processing. As a result, the synchronization packet is sent to the arithmetic units 11, 12, 13, and 14.

In the arithmetic unit 12, since the synchronization packet is not transmitted, the value at the position corresponding to the synchronization number S in the table is not set. Therefore, the synchronization packet arriving at the arithmetic unit 12 is discarded. In the other arithmetic units 11, 13, 14 the synchronization number S in the table
Since the value of the position corresponding to is set, the synchronization packet is received.

Next, the synchronization packet is issued among the arithmetic units 11, 12 and 14, and the fact that the synchronization is established is confirmed by the arithmetic unit 13.
The case of notifying to will be described.

First, the synchronization packet sent from the arithmetic units 11 and 12 arrives at the switch 16. Packet waiting is performed in the same manner as the above-described synchronization processing. When the queuing is established, the synchronous packet is output. In the above case, the output is performed to both output ports O1 and O2. In this case, however, the packet is output only to the output port O2. The difference is that it is specified by the value T1 in the header. As a result, the packet is sent only to the crossbar switch 19.

A synchronization packet is sent from the arithmetic unit 14 to the crossbar switch 17. Regarding this synchronous packet, the value T1 in the packet header indicates that the output port is O2, and F1 indicates that the crossbar switch 17 does not perform synchronous processing. Only output and sent to the crossbar switch 19.

As described above, the crossbar switch 1
9, a sync packet is sent. For these synchronization packets, the value F2 in the header specifies that synchronization processing is to be performed, and T2 specifies only the output port O1 as the output destination. Therefore, in the crossbar switch 19, the crossbar switch 16
By performing the same synchronization processing as in (1), the synchronization packet is sent only to the output port O1 of the crossbar switch 16, and the synchronization packet is sent to the arithmetic unit 13 via the data line 102.

The present invention is not limited to the above-described embodiment. For example, in FIG. 1, two stages of 2 × 2 switches (the crossbar switches 16 and 17 are the first stage, the crossbar switch 18 is the 19 shows the multistage network including the second stage), but the present invention can be applied even if the size of the crossbar switch and the number of stages of the multistage network are different.

Further, in the example of the packet format shown in FIG. 2, the information used for routing at each stage is clearly separated for each stage, but this information is not separated for each stage. The same processing can be performed when the routing information for each stage is calculated by performing some calculation with the switches in each stage.

[0063]

As described above, according to the present invention,
Since a table is provided in each crossbar switch forming the multistage network, a synchronization number is designated, and a synchronization packet is waited for and copied in the crossbar switch, the synchronization processing can be speeded up.

Further, according to the present invention, each arithmetic unit is provided with a table for recording the synchronization number of the synchronization packet issued by itself, and discards the synchronization packet having the synchronization number not issued by itself. Therefore, the synchronization processing between arbitrary arithmetic devices can be realized.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of an embodiment of a system of the present invention.

FIG. 2 is a diagram showing an example of a packet format.

FIG. 3 is a configuration diagram of an example of the arithmetic device of FIG.

4 is a configuration diagram of an example of a crossbar switch that constitutes the multistage network of FIG.

5 is a configuration diagram of another example of the crossbar switch which constitutes the multistage network of FIG. 1. FIG.

[Explanation of symbols]

11, 12, 13, 14 Arithmetic device 15 Multistage network 16, 17, 18, 19 Crossbar switch 21 Header 22 Data field 30, 31, 41, 42, 121, 122, 123, 1
24 FIFO 32 operation part 33, 47, 127, 128 control device 34, 48, 129, 130 table 43, 44, 45, 46 buffer 100, 101, 102, 103, 104, 105, 1
06,107 Data line 125,126 Selector

Claims (4)

[Claims] 1. A transmission / reception unit for a synchronization packet having a synchronization number, a plurality of arithmetic units having at least a selection unit for a received synchronization packet, and K stages each having N input ports and M output ports. A crossbar switch (N, M, and K are integers of 2 or more), each input port of the first-stage crossbar switch is connected to the plurality of arithmetic units, and the last-stage crossbar switch is connected to the plurality of arithmetic units. A multi-stage network for outputting a packet to a designated arithmetic unit, the synchronization packet including information designating which crossbar switch of the K-stage crossbar switches is used for transmission. Is issued, the received synchronization packet is selected from the value by the selection means, and the K-stage crossbar switch in the multistage network is Each has a table, refers to the table from the value of the synchronization number of the input synchronization packet, updates the value of the table from the reference value, and discards the synchronization packet input from the updated value or the next stage. A synchronization method between arithmetic units characterized by outputting to 2. The sorting means sets a table and the table when the synchronization packet is issued, and discards the synchronization packet that has arrived at the arithmetic unit according to the value of the table when the synchronization packet is received. 2. The inter-arithmetic-device synchronization method according to claim 1, further comprising a control device that determines whether or not to execute. 3. Each of the K-stage crossbar switches forming the multi-stage network has N memory for storing a packet input through N input ports and a number of the input ports. When the table of the corresponding size and the packet stored in the memory are synchronous packets, the table is referred to by the synchronous number of the synchronous packet, the value of the table is updated from the reference value, and after the update And a control device that discards or outputs the synchronization packet based on the values in the table, and a storage synchronization packet from the designated memory among the N memories under the control of the control device when the synchronization packet is copied and output. 2. The inter-arithmetic-device synchronization method according to claim 1, further comprising a selection circuit for selectively outputting. 4. Each of the K-stage crossbar switches forming the multi-stage network includes a packet input via one input port of N input ports and another (N-
1) N memories for respectively storing packets input via the input ports, a table having a size corresponding to the number of the input ports, and when the packets stored in the memory are synchronous packets, A control device for referring to the table with the synchronization number of the synchronization packet, updating the value of the table from the reference value, and discarding or duplicating and outputting the synchronization packet from the updated table value;
A selection circuit for selectively outputting a storage synchronization packet from a designated memory among the N memories under the control of the control device when the synchronization packet is copied and output; 2. The inter-arithmetic-device synchronization method according to claim 1, characterized in that the arithmetic units are provided in pairs.