JPH09305553A - Parallel computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a parallel computer system with which execution efficiency is not lowered even when scheduling is performed. SOLUTION: This parallel computer system is composed of a secondary storage device 105 storing a program, main storage device 104 for reading the program stored in the storage device 105, and plural processors 101 for executing the read program. Concerning the secondary storage device, the schedule attribute of the program settable from the outside are stored in a file attribute storage part 1051. The main storage device has a program switching procedure part for switching the program to be executed on the processor 101 inside an OS resident part 1041. Thus, when the schedule attributes of the program are set, this program is executed on the specified processor according to the schedule attributes but when the schedule attributes of the program are not set, this program is executed on any arbitrary processor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel computer system, and more particularly to a parallel computer system suitable for performing a scheduling process.

[0002]

2. Description of the Related Art In a conventional parallel computer system, an operating system manages execution units of user programs in units called processes (or tasks) in order to execute a plurality of programs in a multiplexed manner. In such an operating system, for example, S.
J. Leffler et al., Translated by Akira Nakamura et al., “UNIX
4.3 BSD Design and Implementation ", Maruzen Co., Ltd., p. 71
~ 97, in order to execute a plurality of processes on a limited number of processors, the process is switched, triggered by an interrupt from the outside of the processor such as a timer or an input / output device.
Scheduling processing is in progress.

Further, for example, Norihisa Suzuki et al., "Practice of Shared Memory Parallel System", Corona Publishing Co., p. 119-17
As described in No. 4, in a parallel computer system in which a memory is shared by a plurality of processors, an operating system that allocates a process to each of the plurality of processors and executes a user program in parallel is known.

On the other hand, for example, C.I. By Schimmel,
"Unix Systems for Modern
Architectures ", ADDison-WE
SLEY Publishing Company,
p. As described in Nos. 285 to 335, a parallel computer system having a cache memory between a processor and a main memory operates so that the contents of a plurality of caches are the same.

[0005]

In a parallel computer system having such a mechanism, when a process frequently moves between different processors at each scheduling, data movement between caches for cache coherency guarantee operation is performed. However, there is a problem in that the execution efficiency of the computer system deteriorates.

Here, the movement of data between caches caused by scheduling depends on the operating characteristics of each program. For example, in a program that frequently executes input / output operations, execution of the program is suspended until the input / output is completed after the input / output instruction is issued, and when restarted, the processor that executed the input / output instruction May run on a different processor than. In such a process, data movement occurs between a plurality of caches. However, the operating characteristics of such a program are often unknown only when the program is actually executed.

In order to prevent data movement, all programs should be executed by the same processor, but if this is done, the allocation to the processors will not be uniform and the processing efficiency of the entire computer system will be increased. Becomes worse.

An object of the present invention is to provide a parallel computer system in which the execution efficiency does not decrease even if scheduling is performed.

[0009]

In order to achieve the above object, the present invention provides a secondary storage device for storing a program,
In a parallel computer system having a main storage device for reading the program stored in the secondary storage device and a plurality of processors for executing the program read in the main storage device, the secondary storage device can be set from the outside. Storing the schedule attributes of various programs, the main storage device has a program switching procedure part for switching the programs to be executed on the processor, and the program switching procedure part is set in the secondary storage device. If the schedule attribute of the program is set according to the schedule attribute, the program is executed on a specific processor, and if the schedule attribute of the program is not set, the program is executed on any processor. With this configuration, the Even if the scheduling by limiting the movement of one cache, and those which may improve the execution efficiency.

In the parallel computer system, preferably, the schedule attribute of the program is composed of a bit string, and if it is "1", the schedule attribute is set.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A parallel computer system according to an embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a system block diagram of a parallel computer system according to an embodiment of the present invention.

The parallel computer system 100 includes a plurality of processors 101-1, 101-2, ... 101-n and a plurality of cache memories 102-1, 102-2 ,.
n, a main storage device 104 and a secondary storage device 105. Processor 101, cache memory 10
2. The main storage device 104 and the secondary storage device 105 are connected to each other via the system bus 103.

The data stored in the main storage device 104 is
Via the system bus 103, the cache memory 102
Is temporarily stored in the processor 101 and then stored in a register held by the processor 101. The main storage device 104 is assigned an address in fixed-length data units, for example, in units of 1 byte, and when transferring data from the main storage device 104 to the processor 101,
If the data of the same address is already stored in the cache memory 102, the data of the cache memory 102 is used instead. As a result, the system bus 10
Data transfer via 3 can be reduced.

In the parallel computer system 100, there are a plurality of processors 101 and cache memories 102. Since the data at any address in the main storage device 104 may exist in a plurality of cache memories 102, the content of the data held by each of the plurality of cache memories 102 and the main storage device 104 should be the same. A mechanism is provided for this.

This mechanism is called cache coherency control processing. Schimmel, "Unix
Systems for Modern Archi
“Tectures”, ADDison-Wesley
Publishing Company, p. 285-
It can be realized using the technique described in 335.

In this embodiment, the main storage device 104
It is composed of an OS resident unit 1041 and a user program execution unit 1049. The OS resident unit 1041 stores operating system procedures and data. The user program execution unit 1049 stores procedures and data.

The secondary storage device 105 is composed of a file attribute storage unit 1051 and a file content storage unit 1052. The file attribute storage unit 1051 stores the program attributes, and the file content storage unit 1052 stores the program contents.

Next, referring to FIG. 2, the OS resident unit 1041
The configuration of will be described. FIG. 2 is a configuration diagram of the OS resident unit used in the parallel computer system according to the embodiment of the present invention.

The OS resident section 1041 has a process management table 1042, a running process management table 1043, an executable process list 1044, and a program start procedure section 104.
5, a program switching procedure section 1046, and a file attribute change procedure section 1047 are stored.

The process management table 1042 has a process number 1042 for managing execution of a plurality of programs.
1, register save area 10422, process execution state 1
A plurality of 0423, process movement information 10424, processor number 10425, and list area 10426 are prepared.

The process number 10421 is used to uniquely identify the user program to be executed within the operating system. Register save area 1042
2 is used to hold the contents of the register held inside the processor 101. Any processor 10
When switching the user program operating at 1, the contents of this register can be saved or restored.

The process execution state 10423 is used to identify whether the process is "running" or "waiting for execution". The process being “running” means that the program is being executed on any processor 101, and the process being “waiting for execution” means that the program is not running on any processor 101. means. Process movement information 10424
Indicates which processor 101 the process is executed by the program switching procedure unit 1046.

The program switching procedure section 1046
This is a procedure started at an arbitrary time interval or when a process waits for I / O. J. Leffl
er et al., Akira Nakamura et al., "Design and Implementation of UNIX 4.3 BSD", Maruzen Co., Ltd., p. 71 to 97,
It corresponds to what is also called a scheduler. Although details of the program switching procedure unit 1046 in the embodiment of the present invention will be described later, the process migration information 1042.
If 4 is "1", allocation to a specific processor is prohibited, and movement between processors is prohibited. If "0", allocation is not to a specific processor but to any free processor. I have to.

The processor number 10425 is used in the process movement information 10424 to specify the processor allocation to an arbitrary processor. The processor number assigned to the process number whose process execution status 10423 is "execution" represents the processor number that is actually assigned. For example, process number ”
1003 "is being executed in the processor number" 1 ", and this relationship is shown in the executing process management table 1043. The process execution state 10423 is given to the process number of" executable ". The processor number represents the processor number assigned last time. For example, the process number “1005” indicates that the process was executed in the processor number “5” at the time of the previous execution.

The running process management table 1043 is used to identify the process running in each processor 101, and a set of the processor number 10431 and the running process number 10432 is registered.

The execution waiting process list 1044 is used to register a process that is executable but not allocated to a processor, and stores the process number at the head of the list. The list of executable processes is set in the list area 10426 of the process management table 1042 by setting the list area 10426 of the process management table 1042 as the next entry. Followed by the process number shown, the end of the list is "-
End with 1 ".

For example, in the embodiment shown in FIG. 2, the executable processes are process numbers "1000" and "100".
2 "and" 1005 ".

Regarding the program start procedure section 1045 and the process switching procedure section 1046, respectively,
This will be described later with reference to FIGS.

Next, the configuration of the file attribute storage unit 1051 will be described with reference to FIG. FIG. 3 is a configuration diagram of a file attribute storage unit used in the parallel computer system according to the embodiment of the present invention.

The file attribute storage unit 1051 has a file number 10511, a writable flag 10512, a readable flag 10513, and an executable flag 1051.
4 and a scheduling flag 10515.

The file number 10511 is used to identify a plurality of files stored in the file content storage section 1052. Writable flag 1051
2, read flag 10513, executable flag 105
14 are used to determine whether to write, read, or execute the file contents indicated by the file number 10511. The function provided using this bit is, for example, S.S. J. Leffler et al., Akira Nakamura et al., "Design and Implementation of UNIX 4.3 BSD", Maruzen Co., Ltd., p. It has a function equivalent to the function using the access mode of the files shown in 193 to 234.

The scheduling flag 10515 can be set to "1" or "0" by executing the file attribute change procedure part 1047. The file attribute storage unit 1051 is referred to by the program activation procedure unit 1045. Program start procedure section 104
The result referred to in step 5 is reflected in the process movement information 10424 of the process management table 1042, and is referred to by the process switching procedure unit 1046.

Next, the details of the program activation procedure unit 1045 will be described with reference to FIG. FIG. 4 is a PAD diagram for explaining the program start procedure part in the parallel computer system according to the embodiment of the present invention.

First, in processing step 401, the OS
The program activation procedure section 1045 of the resident section 1041
Of the programs stored in the file content storage unit 1052, the file number of the program to be started is designated. The file number is, for example, the file attribute storage unit 10
As shown in the column of file number 10511 of 51, since the numbers are “000” and “001”,
Specify one of these file numbers.

Next, in process step 402, the program activation procedure part 1045 causes the process management table 104
In step 2, create a new process. A process number is assigned to each process. The assigned process number is, for example, the process number 10421 of the process management table 1042.
As shown in the column, "1000", "100"
In the determination processing step 403, the program activation procedure unit 1045 determines whether the file attribute corresponding to the file number 10511 stored in the file attribute storage unit 1051 has a scheduling flag 10515. For example, it is determined that the scheduling flag 10515 is “1” and the scheduling flag is present for the file number “000” in the file attribute storage unit 1051.
For the file number “001” of 051, the scheduling flag 10515 is “0”, and it is determined that there is no scheduling flag.

If the judgment processing step 403 is:
If there is the scheduling flag 10515, in the processing step 404, the program start procedure part 1045.
Sets the process migration information flag 10424 column of the process management table 1042 to "1".

If there is no scheduling flag 10515 in the judgment processing step 403, in the processing step 405, the program starting procedure part 1045
Process migration information flag 10 of process management table 1042
The column 4240 is set to “0”.

Finally, in processing step 406, the program activation procedure section 1045 stores the file contents of the corresponding file number in the user program execution section 1049 in the main storage device and activates the program.

Details of the program switching procedure unit 1046 will be described below with reference to FIG. FIG. 5 is a PAD diagram for explaining the program switching procedure unit in the parallel computer system according to the embodiment of the present invention.

In processing step 501, the program switching procedure section 1046 sets the head of the executable process list 1044 as a candidate for the next execution process. For example, since "1000" is stored in the executable process list 1044 shown in FIG. 2, the process number "1000" stored in the process number 10421 column.
Process becomes a candidate for the next execution process.

Next, in the repeat determination processing step 502, the program switching procedure unit 1046 refers to the process management table 1042 and determines whether the execution process is not selected and there is a candidate for the next execution process. To do. That is, the process number "100" shown in FIG.
For the process “0”, it is determined by referring to the process execution state 10423 column of the process management table 1042 that no execution process is selected, that is, in the “executable” state. Further, the process management table 1042
Checking that there is a candidate for the next execution process, that is, that there is a candidate for the next execution process in the list area 10426 by referring to the list area 10426 column.

For example, the process with the process number "1000" is stored in the list area 10426 as "1002", indicating that there is a next execution process, but the process with the process number "1005" is shown in the list area 104.
"-1" is stored in 26, indicating that there is no next execution process. A process in which "-1" is stored in the list area 10426 is called an idle process.
The details will be described later.

If the result of the repeat determination processing step 502 is true, processing steps 503 to 506 are executed. For the process with the process number “1000”, the column of the process execution status 10423 of the process management table 1042 is “executable”, and the column of the list area 10426 of the process management table 1042 is “1002”.
Is stored and indicates that there is a next execution process, processing steps 503 to 506 are executed.

In processing step 503, the program switching procedure section 1046 sets the current processor number as the number of the processor that executes the scheduling process. For example, the running process management table 104 shown in FIG.
The processor number “3” in 3 finishes the execution process,
When the next process is to be executed, the number of the processor that executes the scheduling process is the processor number "3".

In the determination processing step 504, the program switching procedure section 1046 determines whether or not the column of the process migration information 10424 of the program management table 1042 shown in FIG. 2 is "0".

The column of process movement information 10424 is
If the value is "0", the movement of the processor is not prohibited, and the process can be executed by any processor. Therefore, in process step 505, the process selected as the candidate is selected as the execution process.

The column of process movement information 10424 is
If the value is "1", the movement of the processor is prohibited, and therefore the process proceeds to the determination processing step 506.

For example, for the process with the process number "1000", since the column of the process migration information 10424 is "1", the process proceeds to the judgment processing step 506.

In the decision processing step 506, the program switching procedure part 1046 indicates that the column of the process migration information 10424 of the program management table 1042 shown in FIG. 2 is "1" and the processor number of the program management table 1042 is the present. It is determined whether it is the processor number of.

If the result of the determination is true, the process 50
In 7, the process selected as the candidate is selected as the execution process. If the result of the judgment is not true,
In process 508, the next program from the executable program list is set as a candidate for the execution program, and the repeat determination process step 502 is repeated.

For example, for the process with the process number “1000”, the column of the process migration information 10424 of the program management table 1042 is “1”. Further, the processor number stored in the processor number 10425 column of the program management table 1042 is "5", but since the number of the processor that executes the scheduling process in the processing step 503 is "3", both numbers Means that the process management table 1042 corresponding to the process number “1000” is reached.
The process number “1002” stored in the column of the list area 10426 of FIG.

In the repeat determination processing step 502, the process number “1002” of the program is “executable” in the column of process execution status 10423, and is the next execution process candidate in the column of list area 10426. Since there is "1005", processing step 503
After that, the process proceeds to the determination processing step 504.

In the judgment processing step 504, since the column of the process movement information 10424 is "1" for the program with the process number "1002", the processing advances to the judgment processing step 506.

In the judgment processing step 506, the process of process number "1002" is the program management table 1
The column of the process movement information 10424 of 042 is “1”. Further, the processor number stored in the processor number 10425 column of the program management table 1042 is "
Although it is 3 ", since the number of the processor that executes the scheduling process is set to" 3 "in the processing step 503, the two numbers match, and the processing step 5
Proceed to 07.

Then, in process step 507, the process "1002" selected as a candidate is selected as an execution process.

In the decision processing step 509, the program switching procedure section 1046 decides whether or not the execution process is selected. That is, processing step 503
At 508, it is determined if a run process has been selected.

If no execution process is selected, a special process called an idle process is selected as an execution process. The idle process is a program that executes an infinite loop, and the process number is "-1"
And List area 1042 of process management table 1042
Since the end of 6 is "-1", the executing process can be recognized as an idle process if no process is selected.

If the execution process is not selected in the processing steps 503 to 508, the program switching procedure unit 104 is processed in the processing step 510.
6 selects the idle process as the execution process.

Next, in processing step 511, the program switching procedure section 1046 registers the selected process in the running process management table 1043. For example, processor number 1 in the running process management table 1043
The selected process number “1002” is registered in the process number 10432 column corresponding to the processor number “3” in the column 0431.

In processing step 510, the program switching procedure section 1046 restores the register information of the selected process to the processor.

By the above processing, it is possible to switch the processor using the process migration information in the process management table.

Details of the file attribute change procedure section 1047 will be described below with reference to FIG. FIG. 6 is a PAD diagram for explaining the file attribute change procedure part in the parallel computer system according to the embodiment of the present invention.

In processing step 601, the file attribute change procedure section 1047 of the OS resident section 1041 designates the file number of the program whose file attribute is to be changed among the programs stored in the file attribute storage section 1051. The file number is a number such as "000" or "001" as shown in the column of the file number 10511 of the file attribute storage unit 1051. Therefore, one of these file numbers is designated.

In the judgment processing step 602, the file attribute change procedure section 1047 judges whether or not the movement of the processor is prohibited, and when the movement is prohibited,
Proceed to processing step 603, and if the movement is not prohibited, proceed to processing step 604.

In the processing step 603, the file attribute change procedure part 1047 causes the file attribute storage part 105.
The flag in the column of the scheduling flag 10515 corresponding to the designated file number in 1 is set to "1".
This prohibits processor movement.

In the processing step 604, the file attribute change procedure part 1047 causes the file attribute storage part 105.
The flag in the column of the scheduling flag 10515 corresponding to the designated file number in 1 is set to "0".
This allows the processor to be moved.

In this way, the file attribute storage unit 10
By setting the flag in the column of the scheduling flag 10515 in 51 to “1” or “0”, it is possible to easily set whether or not the program can be moved.

According to the present embodiment, for a process that frequently repeats the input / output operation, scheduling is performed based on the process movement information so that the movement of the processor is prohibited. Can be improved.

[0069]

According to the present invention, in a parallel computer system, execution efficiency can be improved even if scheduling is performed.

[Brief description of drawings]

FIG. 1 is a system block diagram of a parallel computer system according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of an OS resident unit used in the parallel computer system according to the embodiment of the present invention.

FIG. 3 is a configuration diagram of a file attribute storage unit used in the parallel computer system according to the embodiment of the present invention.

FIG. 4 is a PA for explaining a program start procedure part in the parallel computer system according to the embodiment of the present invention.
FIG.

FIG. 5 is a PAD diagram illustrating a program switching procedure unit in the parallel computer system according to the embodiment of the present invention.

FIG. 6 illustrates a file attribute change procedure part in the parallel computer system according to the embodiment of the present invention.
It is an AD diagram.

[Explanation of Codes] 100 ... Parallel Computer System 101 ... Processor 102 ... Cache Memory 103 ... System Bus 104 ... Main Storage Device 1041 ... Operating System Resident Unit 1042 ... Process Management Table 1043 ... Running Process Management Table 1044 ... Executable Process List 1045 ... Program start procedure section 1046 ... Program switching procedure section 1047 ... File attribute change procedure section 105 ... Secondary storage device 1051 ... File attribute storage section 1052 ... File content storage section

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kazuo Horikawa, Inventor Kazuo Horikawa 12 890 Kashimada, Sachi-ku, Kawasaki-shi, Kanagawa Hitachi, Ltd. Address No. 12 Hitachi Ltd., Information & Telecommunication Development Headquarters (72) Inventor Kominori Yamada 5030 Totsuka-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture

Claims (2)

[Claims] 1. A parallel system having a secondary storage device for storing a program, a main storage device for reading the program stored in the secondary storage device, and a plurality of processors for executing the program loaded in the main storage device. In the computer system, the secondary storage device stores a schedule attribute of a program that can be set from the outside, and the main storage device has a program switching procedure unit that switches a program to be executed on the processor. The program switching procedure unit executes the program on a specific processor if the schedule attribute of the program is set according to the schedule attribute set in the secondary storage device, and sets the schedule attribute of the program. If not, run this program on any processor A parallel computer system characterized by being executed by. 2. The parallel computer system according to claim 1, wherein the schedule attribute of the program is composed of a bit string, and the schedule attribute is set if it is “1”.