JPH09305493A - Buffer memory circuit and memory switch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent data from being disabled to correctly be read out after an error occurs in an address pointer area of a buffer memory circuit since write/read order is determined by an address chain. SOLUTION: This buffer memory circuit has an address memory 40 which stores write addresses, a free address memory 35 which stores free addresses of the buffer memory 31, and an error address detecting circuit 50 which has information regarding in-use addresses of the buffer memory 31. An error detecting circuit 50 detects an overlap of the in-use addresses of the buffer memory 31 and an address read out of the free address memory 35 and sends an error signal out to a control circuit 60 when there is the overlap.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer memory circuit or a memory switch for temporarily storing data, and more particularly to an A in a wide band ISDN.
The present invention relates to a buffer memory circuit or a memory switch used for TM transmission or high-speed packet communication.

[0002]

2. Description of the Related Art Conventionally, there have been techniques disclosed in the following documents as techniques relating to memory switches.

"ATM switch memory switch with shared buffer", IEICE Transactions BI Vo
l. J72-BI No. 11 pp1062-10
69 November 1989 The memory switch disclosed in the above document has an ATM cell data (hereinafter referred to as ATM cell) write area and an address pointer area at the same address in the buffer memory. When the ATM cell data is written in the buffer memory, the ATM cell is written in the ATM cell writing area, and the address of the cell to be written next is also written in the address pointer area of the same address in units of output lines. Thus, in the address pointer area of the buffer memory, an address chain is formed in which the read addresses are sequentially referenced in units of outgoing lines. On the other hand, when reading an ATM cell from the buffer memory, the address of the area in which the ATM cell to be read next is stored can be found by referring to the address pointer area of the same address as the ATM cell read in line-out units. The cells can be sequentially read out in units of outgoing lines without breaking the order of the buffered cells.

[0004]

However, in the circuit having the above-mentioned structure, the order of the ATM cells to be read is determined by the address chain formed by using the address pointer area, so that the address pointer area is stored in one address pointer area in the buffer memory. When an error occurs, there is a problem that the address chain is divided and the ATM cell cannot be read correctly after that at the outgoing line. Further, when an error occurs in the address pointer area of one address chain, not only that address chain but also the address chain of another outgoing line is erroneously read, and the address chain of another outgoing line is erroneously read. The ATM cells stored in the buffer memory may be invalidated.

[0005]

In order to solve such a problem, a buffer memory circuit of the present invention has an input port and a first memory for temporarily storing first data input from the input port. A second memory for storing information about an in-use address of the first memory, and a third memory for storing an unused free address of the first memory.
Write control for reading an empty address from the first memory and the third memory, writing the first data to the first memory using the empty address, and storing the read empty address as the address in use in the second memory A circuit, and an error detection circuit that detects an overlap between information about an address in use stored in the second memory and an empty address stored in the third memory and sends an address error signal when the overlap occurs. .

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention are shown in FIGS.
3 and FIG. FIG. 1 is a diagram showing a mode example in which the buffer memory circuit of the present invention is applied to a memory switch. The memory switch shown in FIG. 1 is a switch for temporarily storing and exchanging information transmitted from various terminals connected to the communication network in the packet communication network. This form example is a form example in which the present invention is applied to a memory switch in an asynchronous transfer mode (hereinafter referred to as ATM).

In FIG. 1, the memory switch of this embodiment is
N input ports 10-1 to 10 for inputting ATM cells
-N, and has n output ports 20-1 to 20-n for outputting ATM cells after buffering. This memory switch is a circuit that outputs an input ATM cell from a predetermined output port based on a header, and the output order of the ATM cell is stored in each of the plurality of address memories 40 corresponding to the output port. . As an example, here, an ATM to be output from the output port 20-1
The storage addresses of the cells are stored in the address memory 40-1 in the output order. Similarly, the output ports 20-2 to 20
The storage addresses of the ATM cells to be output from -n are stored in the address memories 40-2 to 40-n in the output order.

The input port 10 is connected to another communication device via an ATM network, and the ATM cell input from the input port 10 is input to the cell multiplexer 30. The cell multiplexer 30 uses the ATM input from each input port 10.
A circuit for time-division multiplexing cells and sending them to the buffer memory 31, which is connected to the port WD of the buffer memory 31. The buffer memory 31 is the input ATM
It is a memory for buffering cells, and the port WD is a port for inputting write data. The buffer memory 31 also has a port WA for inputting a write address.

The multiplexed ATM cells are also input to the output port recognizing unit 32, and the output port recognizing unit 32 outputs each A
The output port number to be output is extracted from the header of the TM cell. Each ATM extracted by the output port recognition unit 32
The output port number of the cell is input to the write control circuit 33, and the write control circuit 33 controls the address separating unit 34 based on this information. Free address memory 35
Is a memory that stores an address indicating a free area of the buffer memory 31, that is, a free address, and one of the free addresses is output to the port WA of the buffer memory 31. The address of the buffer memory 31 consists of k bits. The buffer memory 31 stores the ATM cell input from the port WD at the address input to the port WA. Further, the vacant address sent from the vacant address memory 35 is also input to the address separating unit 34, and under the control of the read control circuit 33, the address memory 40
It is sent to one of the address memories of -1 to 40-n.

Each of the plurality of address memories 40 is a read-ahead read-out memory (hereinafter referred to as a FIFO memory), and is provided corresponding to the output port as already described. Each address memory 40 stores the read addresses of the ATM cells output from the corresponding output ports in the order of reading.

The read control circuit 41 includes a cell separation section 43.
Also, the control circuit is connected to the address multiplexing unit 42 and reads the ATM cells stored in the buffer memory 31 and outputs the ATM cells from any one of the output ports 20-1 to 20-n. Address multiplexer 42
Is a circuit for time-division multiplexing the addresses read from the address memories 40-1 to 40-n under the control of the read control circuit 41 and supplying the addresses to the port RA of the buffer memory 31. The cell separation unit 43 outputs the ATM cell read from the port RD of the buffer memory 31 to the output port 20-1 under the control of the read control circuit 41.
It is a circuit for allocating to 20-n. The output ports 20-1 to 20-n are connected to other communication devices via an ATM network.

The error address detection circuit 50 is a circuit for inputting the addresses respectively input to the port WA and the port RA of the buffer memory 31 and detecting whether reading or writing is performed from the incorrect address. The control circuit 60 is a circuit that controls each circuit portion of the memory switch as a whole, and specifically performs desired control so that the memory switch operates as described later. In FIG. 1, the control signal line from the control circuit 60 to each circuit section is omitted.

Next, the write operation of the shared buffer memory in the memory switch shown in FIG. 1 will be described. First, at the time of initialization, all addresses used in the buffer memory 31 are written in the empty address memory 35. After initialization, ATM cells sent from other communication devices are
It is input to the input port 10 via the ATM network. ATM cells input from the plurality of input ports 10 are time-division multiplexed in the cell multiplexing unit 30, and the time-division-multiplexed ATM cells are input to the output port recognition unit 32 as one data string. The time-division multiplexed ATM cell is also input to the port WD of the buffer memory 31.

The output port recognizing unit 32 refers to the headers of the ATM cells which are time-division-multiplexed and sequentially input, and outputs the output port number of the ATM cell among the plurality of output ports 20, for example, the output port number. The number indicating the output port 20-2 is detected. Furthermore, the output port recognition unit 32
Sends the detected output port number to the write control circuit 33.

As described above, the free address memory 35 stores the address of the unused memory area of the buffer memory 31, that is, the free address. Therefore, the write control circuit 33 reads one of the addresses stored in the empty address memory and inputs the read empty address to the port WA of the buffer memory 31. In this way, data to be written to the port WD and the port WA of the buffer memory, that is, ATM
An ATM cell is stored at a predetermined address by inputting an address designating a cell and a writing area.

Further, the above-mentioned address read from the empty address memory 35 is also input to the address separating unit 34. Here, the write control circuit 33 controls the address separation unit 34 so that the above address is input to one of the address memories 40 corresponding to the output port numbers detected by the output port recognition unit 32. For example, when the output port of the input ATM cell to be output is the output port 20-1, the above-mentioned address read from the empty address memory 35 is input and stored in the address memory 40-1. As described above, since the address is written in the FIFO address memory 40 in units of output ports, a queue of addresses in units of output ports is formed in each address memory 40. Further, the above-mentioned address read from the empty address memory 35 is also input to the error address detection circuit 50.

FIG. 2 is a block diagram showing an example of the internal circuit of the error address detection circuit 50. The error address detection circuit 50 includes an address input unit 101 for inputting an address from the empty address memory 35 and an address input unit 1 for inputting an address from the address multiplexing unit 42.
02. In addition, the error address detection circuit 50
It has a used address storage unit 103, and the used address storage unit 103 stores all the addresses of the areas currently used in the buffer memory 31 for storing ATM cells.

The used address storage unit 103 updates the stored contents each time the buffer memory 31 is written or read, and operates so that the stored address and the address of the used area of the buffer memory 31 always match. Specifically, when writing to the buffer memory 31, the write address output from the free address memory 35 is input from the address input unit 101, and the used address storage unit 10 is input.
3 adds the address to the stored contents. Further, when reading the buffer memory 31, the address multiplexing unit 42
The read address output from the address input unit 10
2, the used address storage unit 103 deletes the address from the stored contents.

The comparison detection unit 104 in the error address detection circuit 50 overlaps either the address input from the empty address memory 35 via the address input unit 101 or the address stored in the used address storage unit 103. Compare and detect whether or not. If they overlap, it is already A
The comparison detection unit 104 sends an error signal to the control circuit 60 because it indicates that an ATM cell is to be further stored in the memory area of the buffer memory 31 in which the TM cell is stored.

FIG. 3 is a circuit diagram showing in more detail the internal circuit of the error address detection circuit 50 shown in FIG.
3 is an example of an internal configuration of a used address storage unit 103 and a comparison detection unit 104. Used address storage unit 103 in FIG.
Are the delay circuits 111 and 112 and the decoder circuit 11 of FIG.
4, 115 and a set / reset flip-flop circuit (hereinafter referred to as SR-FF) 117. The comparison / detection unit 104 of FIG. 2 corresponds to the decoder circuit 1 of FIG.
13, 116 AND circuit groups 118 and 119, OR circuit 1
It is composed of 20, 121.

The SR-FF 117 is an m-bit SR-FF.
The SR-FF 117 stores information about whether each memory area of the buffer memory 31 is currently in use. Specifically, among the m outputs Qa (a: 0 ≦ a ≦ m) of the SR-FF 117, the buffer memory 3
The SR-FF 117 is set and reset by the decoder circuit 114 or 115 so that only the output Qa corresponding to the memory area 1 in use is at the high level potential. In addition, this set-reset operation enables the SR-FF
Of the m inverted outputs QNa (a: 0 ≦ a ≦ m) 117, only the inverted output QNa corresponding to the empty memory area of the buffer memory 31 has a high-level potential. Since the set of addresses of the memory area in use of the buffer memory 31 and the set of addresses stored in the free address memory 35 are exclusive, in other words, with respect to the addresses stored in the free address memory 35, Is SR-FF
117 is set, and the address read from the empty address memory 35 is reset. Therefore, in the initial setting, all the usable addresses are written in the empty address memory 35, so that all m bits of the SR-FF 117 are reset.

Now, the operation of the error address detection circuit 50 shown in FIG. 3 will be described. The k-bit address input from the address input unit 101 is input to the decoder circuit 113, and the decoder circuit 113 outputs the m output lines out of the m output lines.
Only the output line corresponding to the input k-bit binary address is set to the high level potential. The output indicating the write address from the decoder circuit 113 is input to the AND circuit group 118, and the output indicating the used address of the SR-FF 117 is also input to the AND circuit group 118. The AND circuit group 118 is composed of m AND circuits.

The AND circuit group 118 includes the buffer memory 3
It detects whether the address input to the port WA of 1 matches one of the addresses in use. In particular,
It is detected whether the addresses match by taking the logical product of the output of the decoder circuit 113 and the corresponding output of the SR-FF 117. Address error is k
The write error can be detected by detecting a match / mismatch because it apparently results from a change to another address due to bit inversion of the bit address. If they match, that is, if an address error occurs, A
One of the outputs of the ND circuit group 118 becomes a high-level potential, and an error signal of a high-level potential is output via the OR circuit 120. If they do not match, that is, in a normal state, the outputs of the AND circuit group 118 are all at a low level potential, and no error signal is output.
There are various possible places where the address error occurs,
For example, address memory 40, free address memory 3
5, on the wiring between the address multiplexing unit 42 or the functional units.

Further, the above error signal is input to the control circuit 60 of FIG. When the error signal is received, the control circuit 60 controls the address separating unit 34, the vacant address memory 35, etc. so that the address will not be used thereafter. Further, the control circuit 60 reads an alternative address from the vacant address memory 35 instead of the address in which the error has occurred, and the alternative address is input to the buffer memory 31 and the address separating unit 34. If errors occur continuously in the empty address memory 35,
It suffices to read as many alternative addresses as the number of the error addresses, but the alternative addresses are stored in the buffer memory 31.
AT output from the cell multiplexer 30 before being supplied to
It is necessary to delay M cells to adjust the timing. The allowable amount of delay determines the number of consecutive readings of the alternative address, that is, the number of consecutive errors that can be dealt with. In this way, by performing the above-mentioned control, the address in which the error is detected is not used anymore, so that the failure associated with the address does not propagate thereafter.

Referring back to FIG. 3, the k-bit address input from the address input unit 101 is also input to the delay circuit 111. The delay circuit 111 delays the input address by one clock and outputs it to the decoder circuit 114.
Output to Similar to the decoder circuit 113, the decoder circuit 114 sets only the output line corresponding to the input k-bit binary address among the m output lines to the high level potential. The m output lines of the decoder circuit 114 are SR-FF1.
17 set inputs Sa (a: 0 ≦ a ≦ m), and the SR-FF 117 is connected to the address input unit 1
The address input from 01 is set. By this operation, the state of the SR-FF 117 is updated, that is, the currently used address is stored.

Next, the read operation of the shared buffer memory circuit in the memory switch shown in FIG. 1 will be described.
When reading an ATM cell from the buffer memory 31, the read control circuit 41 controls the address multiplexing unit and the cell separating unit. The addresses stored in each address memory 40 are sequentially read from the addresses stored at the beginning of the memory, and the read addresses are time-division multiplexed by the address multiplexing unit 42. The time-division multiplexed address is supplied to the port RA of the buffer memory 31, and ATM cells stored at the supplied address are sequentially output from the port RD of the buffer memory 31.

The ATM cell output from the port RD of the buffer memory 31 is input to the cell separation section 43. Here, the read control circuit 41 controls the cell separation unit 43 so that the read ATM cell is output from one of the desired output ports 20. Specifically, when an address output from one of the address memories 40 is input to the port RA of the buffer memory 31 and an ATM cell of that address is output from the port RD, it corresponds to the address memory 40 that outputs the address. The cell separating unit 43 is controlled so that the ATM cell is output from one of the output ports 20 that are connected to each other. For example, the address is transferred from the address memory 40-1 via the address multiplexing unit 42 to the buffer memory 31.
When it is input to the port RA, the cell separation unit 43 is controlled so that the ATM cell output from the port RD is output from the output port 20-1. In this way, the ATM cell input from the input port 10 is the desired output port 2
The output from 0 functions as a cell switch.

On the other hand, the address output from the address memory 40 is also input to the vacant address memory 35 because it is used as a write address of the buffer memory 31 thereafter. The address output from the address memory 40 is also input to the error address detection circuit 50.

In FIG. 2, the address is input from the address input unit 102. Error address detection circuit 5
The comparison / detection unit 104 in 0 stores the address input from the address input unit 101 and the used address storage unit 103.
Comparing and detecting whether or not any of the addresses stored by is duplicate. If they do not overlap, it indicates that the ATM cells have been read from the area of the buffer memory 31 in which the ATM cells are not stored, so the comparison and detection unit 104.
Sends an error signal to the control circuit 60.

This operation will be described in detail below with reference to FIG. As described above, the SR-FF 117 is set and reset by the decoder circuit 114 or 115, so that m Qa (a:
0 ≦ a ≦ m) Of the outputs, only the output line corresponding to the address of the memory area in use of the buffer memory 31 is at the high level potential. Further, by this set-reset operation, m ports QNa (a: 0 of SR-FF117
Among ≦ a ≦ m), only the outgoing line corresponding to the address of the empty memory area of the buffer memory 31 has the high level potential.

The k-bit address input from the address input unit 102 is input to the decoder circuit 116, and the decoder circuit 116 outputs the k input bits out of the m output lines.
Only the output line corresponding to the bit binary address is set to the high level potential. Decoder circuit 11 representing a read address
The output from 6 is input to the AND circuit group 119, and the output of the SR-FF 117 indicating the address of the empty memory area of the buffer memory 31 is also input to the AND circuit group 119. The AND circuit group 119 is composed of m AND circuits.

The AND circuit group 119 includes the buffer memory 3
It is detected whether the address input to the port RA of 1 does not match one of the addresses in the free memory area. When they match, that is, when an address error occurs, one of the outputs of the AND circuit group 119 becomes a high-level potential, and an error signal of a high-level potential is output via the OR circuit 121. SR-FF117 QNa
In other words, the (a: 0 ≦ a ≦ m) output is the inverted output of Qa (a: 0 ≦ a ≦ m).
An error signal will be output if the address input to the port RA of 1 does not overlap with one of the addresses of the memory area being used. Also, if they do not match, that is,
In the normal state, all the outputs of the AND circuit group 119 have a low level potential, and no error signal is output.

The above-mentioned error signal is generated by the control circuit 60 of FIG.
Is input to When the error signal is received, the control circuit 6
0 controls the address separating unit 34, the vacant address memory 35, etc. so that the address is not used thereafter.
The address where the error is detected is stored in the buffer memory 3
Since one has already been supplied to 1, one ATM cell will be erroneously read. This is an unavoidable phenomenon in the present embodiment, but the failure caused by it is erroneous reading of 1 ATM cell at the most, and the individual failures do not spread thereafter.

Returning to FIG. 3, the k-bit address input from the address input unit 102 is also input to the delay circuit 112. The delay circuit 112 delays the input address by one clock and outputs it to the decoder circuit 115. Similar to the decoder circuit 116, the decoder circuit 115 sets only the output line corresponding to the input n-bit binary address among the m output lines to the high level potential. The m output lines of the decoder circuit 115 are SR-FF1.
The SR-FF 117 is connected to the reset inputs SNa (a: 0 ≦ a ≦ m) of the respective 17, and the SR-FF 117 resets the address input from the address input unit 102. By this operation, the state of the SR-FF 117 is updated, that is, the currently used address is stored.

As described above, according to this embodiment, the shared buffer memory circuit is provided with the error address detection unit to detect whether or not the write address or the read address of the buffer memory 31 has an error. Therefore, with this configuration, the address in which an error has been detected is not used thereafter, so that the error address that has been a problem in the conventional buffer memory circuit does not continue to circulate inside the device forever. Therefore, when an error address occurs, the damage can be minimized, and as a result, the reliability of the circuit can be greatly improved.

Further, as shown in this embodiment, by having a plurality of FIFO type address memories for each output line, although the hardware scale becomes larger than the method using the address chain, one address is used. Even if an error occurs, the address queues of other outgoing lines are not divided.

This embodiment is an embodiment in which the present invention is applied to a shared buffer memory circuit in a memory switch. However, the present invention is not limited to the shared buffer memory circuit in the memory switch, and a single buffer that does not perform a switch operation. It can also be applied to memory circuits. In this case, in FIG. 1, the number of the input ports 10 and the number of the output ports 20 may each be one, and the cell multiplexing unit 30, the output port recognition unit 32,
The address separating unit 34, the cell separating unit 43, and the address multiplexing unit 42 are unnecessary.

Further, in this embodiment, the buffer memory 31 is used.
The information about the address being used is stored in the used address storage unit 103 of FIG. 2 separately from the address memory 40 of FIG. 1, but the present invention does not necessarily include the used address storage unit 103 of FIG. It is not necessary to detect the address error by detecting the overlap between the write address / read address input to the error address detection circuit 50 and the address stored in the address memory 40.

[0039]

According to the present invention, in the buffer memory circuit for storing the data inputted from the input port in the temporary memory, by providing the error address detecting circuit, the error address detecting circuit can be used while the memory is in use. It detects whether the address and the write address / read address of the data input from the input port overlap, and sends an error signal when it overlaps / does not overlap, so do not use the address where the error occurred again. It can be controlled and the reliability of the circuit can be greatly improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example in which a buffer memory circuit of the present invention is applied to a memory switch.

2 is a block diagram showing an example of an internal circuit of an error address detection circuit 50. FIG.

FIG. 3 is a circuit diagram illustrating in detail an internal circuit of the address detection circuit 50.

[Explanation of symbols]

10-1 to 10-n input port 20-1 to 20-n output port 30 cell multiplexing unit 31 buffer memory 32 output port recognition unit 33 write control circuit 34 address separation unit 35 free address memory 40-1 to 40-n address Memory 41 Read control circuit 42 Address multiplexing unit 43 Cell multiplexing unit 50 Error address detection circuit 60 Control circuit 101, 102 Address input unit 103 Used address storage unit 104 Comparison detection unit 111, 112, 113, 114, 115, 116
Decoder circuit 117 Set / reset flip-flop 118, 119 AND circuit group 120, 121 OR circuit

Claims (6)

[Claims] 1. An input port, a first memory for temporarily storing first data input from the input port, and a second memory for storing information about an address in use of the first memory. A third memory for storing an unused unused address of the first memory; reading the empty address from the third memory; and using the empty address to store the first address in the first memory. Write control circuit for storing the read and written empty address in the second memory as an in-use address, the information about the in-use address stored in the second memory and the third A buffer memory circuit having an error detection circuit that detects duplication with the empty address stored in the memory and sends an address error signal when the duplication occurs. 2. The buffer memory circuit according to claim 1, wherein the error detection circuit inputs the empty address read from the third memory, and the input empty address is used as an address in use. Before being stored in the second memory, the duplication is detected by comparing the input free address with the information about the address in use stored in the second memory. Buffer memory circuit. 3. The buffer memory circuit according to claim 2, wherein the second memory is a set-reset flip-flop, and the set-reset flip-flop inputs the empty address read from the write control circuit and inputs the empty address. A buffer memory circuit for storing information about an in-use address of the first memory by setting or resetting a bit corresponding to the empty address that has been stored. 4. An input port, an output port, a first memory for temporarily storing first data input from the input port, and information about an address in use of the first memory. A second memory; a third memory for storing an unused free address of the first memory; a read of the free address from the third memory; and a use of the free address for the first memory A write control circuit for writing the first data into the second memory and storing the read empty address in the second memory as an address in use; and reading the first data from the first memory, Of the data from the output port and delete the read address from the information in the second memory as an unused address, A read control circuit for storing the read address as an empty address in the third memory; and the read address and the read address before the read address is input and the read address is deleted from the information of the second memory. A buffer memory circuit having an error detection circuit that detects duplication by comparing the information stored in the second memory and outputs an address error signal when the duplication does not occur. 5. A plurality of input ports, a plurality of output ports, a first memory for temporarily storing first data input from the plurality of input ports, and the first data stored therein. A plurality of second read-ahead read-out memories for storing addresses, a data recognition unit for classifying the first data in correspondence with the plurality of second read-ahead read-out memories, and the first data not stored A third memory that stores an empty address, a fourth memory that stores information about an address being used by the first memory, the empty address read from the third memory, and the read empty address Is used to write the first data to the first memory and select one of the plurality of second memories based on the classification of the data recognizing unit. A write control circuit for storing the empty address in the second memory as an in-use address and for storing the empty address in the fourth memory as an in-use address; An address is read from one, the first data is read from the first memory using the read address, and is output to one of the plurality of output ports, and the read address is set as an unused address. A read control circuit that deletes the read address from the information in the fourth memory and stores the read address in the third memory as an empty address, and inputs the empty address read by the write control circuit. The empty address is stored in the fourth memory as an address in use. To,
A duplication is detected by comparing the input address with the information about the address in use stored in the fourth memory, and when the duplication occurs, an address error signal is transmitted and the read address is input. , Before the read address is deleted from the fourth memory,
A memory switch having an error detection circuit that detects duplication by comparing the read address and the information about the address in use stored in the fourth memory, and outputs the address error signal when the duplication does not occur. . 6. The buffer memory circuit according to claim 5, wherein the first data is an ATM cell, and the data recognizing unit uses the output port information indicated by the header of the first data to output the first data. Memory switch, wherein a plurality of the second memories correspond to the output ports in a one-to-one correspondence.