JPH09305379A - Sorting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sorting circuit which is improved in rearranging speed. SOLUTION: Input data is stored in a register 102 and selection data is stored in a register file 103. An address generating circuit 107 generates addresses for reading from and writing to the register file 103 in the order of 0, 1, 2, 3, 4, 0, 1.... A comparator 101 outputs the MSS of (A-B) as C, where A is the value in the register 102 and B is the output of the register file 103. A selecting circuit 104 selects an input IN when an address is '0' or '4', and B when C=0 or IN when C=1 in other cases. A multiplexer 105 selects A when C=0 or B when C=1. An input request generating circuit 108 outputs an input request signal NXT=1 when the address is "0" and C:1 or when the address is '4'. When NXT=1, next input data is inputted from IN.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sorting device that sorts data in ascending order or descending order.

[0002]

2. Description of the Related Art A conventional sorting apparatus uses a method of sequentially comparing two data at a time.

Here, a case will be described in which the upper n data are selected in descending order. For example, in the configuration shown in FIG. 5, 501 is a register, 502 is a comparator that compares two data and outputs a comparison result, 503 is a multiplexer, IN is input data, CLK is a clock signal, and RST.
Is a reset signal and OUT is an output.

The operation for selecting the upper 4 data from the N data will be described with the time required for one comparison as one cycle. When selecting the maximum value from the N pieces of data, first, the register 501 is initialized by the reset signal and the minimum value is stored. Next, N pieces of data are sequentially input from IN. The comparator 502 compares the data input to IN with the value of the register 501. Multiplexer 5
03 uses the comparison result output from the comparator 502 to select the larger value of IN and the value of the register 501, and writes it in the register 501 using the clock signal CLK as a write signal. Clock signal C for N data
The maximum value is output from OUT in the next cycle after inputting all the N data in synchronization with LK.

Even when the second largest value is selected from the N pieces of data, the (N-1) pieces of data excluding the maximum value are set to IN.
It is possible to perform in the same manner as above by inputting into.

N cycles are used to obtain the data having the maximum value, and (N-1) pieces of data other than the maximum value are input to obtain the data having the next largest value, so (N-1).
Need a cycle. Similarly, in order to select the 3rd and 4th largest data, (N-2) cycles and (N-3) cycles are required, respectively, and the time of (Equation 1) is required as a whole.

[0007]

[Equation 1]

When N = 100, it takes 394 cycles to select all the upper four data.

[0009]

As described above, in the conventional sorting apparatus, the larger the number of input data or the number of data to be selected, the more the number of cycles required for selection increases in proportion to the number of data. Processing time also becomes long. In addition, it is necessary to repeatedly input the data excluding the selected data.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a sorting apparatus which inputs input data only once to improve the data rearrangement speed.

[0011]

In order to achieve the above-mentioned object, a first solving means of the present invention is a sorting apparatus for selecting n data from N input data, First storage means for storing one data; n
Second storage means for storing a plurality of pieces of data, and designation means for receiving one of the signals requesting input of new data and designating one of the n pieces of data stored in the second storage means. A comparison means for comparing the value of the first storage means with the value of the second storage means; and the input of the first storage means using the output of the designation means and the result of the comparison means. First input means for selecting either input data or the value of the second storage means and the result of the comparison means are used to determine whether the input of the second storage means is the value of the first storage means. A second one of the values stored in the second storage means
The selection means, and the input request generation means for outputting a signal requesting the input of the new data by using the output of the designation means and the result of the comparison means.

The second means for solving the problems of the present invention is as follows.
A sorting device for selecting n data out of N input data, the first storage means for storing one data, and the second storage means for storing n data,
One of the n data stored in the second storage means in response to a signal requesting input of new data
Specifying means for specifying one, a comparing means for comparing the value of the first storing means with the value of the second storing means, and the first using the output of the specifying means and the result of the comparing means. The first selection means for selecting either the input data of the storage means or the value of the second storage means, and the input of the second storage means by using the result of the comparison means.
Second selection means for selecting either the value of the storage means or the value of the second storage means, the output of the designation means, the value of the first storage means, and the output of the second selection means. Is used to generate a determination signal, and an input request generating means for outputting a signal requesting the input of new data using the output of the designating means and the determination signal.

The third means for solving the problems of the present invention is as follows.
The first selecting means receives the output of the designating means and the first multiplexer that selects either the input data or the output of the second storing means using the result of the comparing means. It comprises a selection control circuit for generating a selection signal and a second multiplexer for selecting either the input data or the output of the first multiplexer by using the output of the selection control circuit.

The fourth means for solving the problems of the present invention is as follows.
The designation means generates an address of the lowest data of the n pieces of data stored in the second storage means, and then sequentially generates addresses from the highest data to the lowest data. It has a configuration that is a possible address generation circuit.

The fifth means for solving the problems of the present invention is as follows.
The judging means writes the output of the second selecting means only when the specifying means specifies the lowest data of the n data stored in the second storage means. It comprises a possible third storage means and a third comparison means for comparing the value of the first storage means with the value of the third storage means and outputting the determination signal.

The sixth means for solving the problems of the present invention is as follows.
Of the N pieces of data, only n pieces of data are rearranged in descending order.

The seventh means for solving the problems of the present invention is as follows.
Only N pieces of N pieces of data are rearranged in ascending order.

The sorting apparatus of the present invention has means for storing n pieces of data to be selected, and N pieces which are sequentially input.
This data is first compared with the lowest data among the stored n selection data. If the input data is lower than the lowest data, the next target data is input without performing comparison with higher data. When the input data is higher than the lowest data, comparison with the higher data and sorting are performed.

Therefore, when the data lower than the n selected data are input, the comparison operation can be omitted and the processing time for rearranging the data can be shortened.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) FIG. 1 is a circuit diagram showing a part of the configuration of a sorting apparatus according to Embodiment 1 of the present invention. Here, in order to simplify the explanation, it is assumed that the number of selected data items is four and the data items are sorted in descending order.

In FIG. 1, IN is input data, 101
Is a comparator, 102 is a register, 103 is a register file, and F1, F2, F3, and F4 are registers for storing the first, second, third, and fourth largest values, respectively.
Reference numeral 04 is a selection circuit, 105 is a multiplexer, 107 is an address generation circuit that generates an address for reading and writing data in the register file 103, 108 is an input request generation circuit that generates an input request signal for requesting the next input data, OUT is output data and NXT is an input request signal.

Here, the comparator 101 is composed of a subtractor. The comparator 101 calculates (A−B), where A is the value of the register 102 and B is the value of the register of the register file 103 designated by the address generation circuit 107. Assuming that the resulting MSB is C, A is larger when C = 0, and B is larger when C = 1. The multiplexer 105 selects A when C = 0 and B when C = 1. Address generation circuit 107 uses register file 1
Addresses for reading and writing 03 are generated as 0, 1, 2, 3, 4, 0, 1, ... In synchronization with the clock. When NXT = 1, the address generation is reset, and the addresses are generated again in the order of 0, 1, 2, 3, 4, 0, 1, ... The address generated by the address generation circuit 107 is ADRS. The register file 103 is
When ADRS = 0, only the register of F4 is read, and when ADRS = 1, 2, 3, 4 respectively,
Reading and writing of F1, F2, F3, and F4 are performed.
The selection circuit 104 selects either IN or B as shown in FIG. The input request generation circuit 108 is ADR
When either S = 0 and C = 1 or ADRS = 4, the input request signal NXT = 1 is output. When NXT = 1, the next input data is input from IN.

In FIG. 3, the register 1 is synchronized with the next clock.
02, data to be written in the register file 103.

In the initial state of sorting, the value of each register of the register file is set to the minimum value that the input data can take. Further, it is assumed that the processing of the comparison operation is completed within one clock, and the register 102 and the register file 103 write data in synchronization with the clock.

The input data IN is first compared with the register F4 in which the smallest data in the register file 103 is stored. Since IN is smaller than F4 and smaller than F1 to F3, it is not compared with these values. If IN is greater than F4, then F
1 to F4 are sequentially compared. After five comparisons, F1
~ F4 and four larger values out of the five values of the input data are stored in F1 to F4 in descending order.

The operation of the sorting apparatus according to this embodiment will be described with reference to FIG.

In the file register 103, F1 = 20
Assume that 0, F2 = 150, F3 = 100, and F4 = 50 are stored, and input data IN = 20 and 120 are sequentially input. The multiplexer 106 selects the input data IN, and IN = 20 is stored in the register 102 in synchronization with the first clock.

First clock: Since ADRS = 0,
B = F4 = 50. Since A = 20, AB =
-30 <0 and C = 1. The register file 103 does not perform writing in synchronization with the second clock. The input request generation circuit 108 outputs NXT = 1. Therefore,
The following input data is input to IN. Selection circuit 104
Selects IN and the next input data is written to the register 102 in synchronization with the second clock. Further, the address generation circuit 107 resets the address generation.

Next, receiving the input request signal, IN = 120
The operation when is input will be described.

Second clock: Since ADRS = 0,
B = F4 = 50. Since A = 120, AB
= 70> 0 and C = 0. In the register file 103, writing in synchronization with the third clock is not performed. Since the input request generation circuit 108 outputs NXT = 0, new input data is not input to IN. Selection circuit 10
4 selects IN, and the current input data is written in the register 102 in synchronization with the third clock.

Third clock: Since ADRS = 1,
B = F1 = 200. Since A = 120, A-
B = -80 <0 and C = 1. Multiplexer 105
Selects F1 and is written to F1 in synchronization with the fourth clock. Further, the selection circuit 104 selects IN and
It is written in the register 102 in synchronization with the clock.

Fourth clock: Since ADRS = 2,
B = F2 = 150. Since A = 120, A-
B = -30 <0 and C = 1. Multiplexer 105
Selects F2 and is written to F2 in synchronization with the fifth clock. Further, the selection circuit 104 selects IN and
It is written in the register 102 in synchronization with the clock.

Fifth clock: Since ADRS = 3,
B = F3 = 100. Since A = 120, A-
B = 20> 0 and C = 0. In this case, the multiplexer 105 selects A and synchronizes with F6 in synchronization with the sixth clock.
Is written to. Further, the selection circuit 104 selects F3, and F3 is written in the register 102 in synchronization with the sixth clock.

6th clock: Since ADRS = 4,
B = F4 = 50. Since A = 100, AB
= 50> 0 and C = 0. In this case, the multiplexer 105 selects A and is written in F4 in synchronization with the seventh clock. Further, the input request generation circuit 108 is an NXT.
= 1 is output. Therefore, the next input data is input to IN, the selection circuit 104 selects IN, and the next input data is written to the register 102 in synchronization with the seventh clock. Further, the address generation circuit 107 resets the generation order of addresses.

From the above, by the processing in the first to sixth clocks, F1, F2, F3, F4 = 200, 150, 100, 5
The sequence of data 0 is F1, F2, F3, F4 = 200, 150, 120, 1
You can see that it is sorted as 00.

The processing for two inputs of IN = 20 and 120 is completed in 1 + 5 = 6 cycles.

As in the conventional example, assuming that N = 100 and half the 50 input data are smaller than the data stored in F4, the time required for sorting is (Equation 2). Therefore, it can be seen that speed improvement can be realized as compared with the 394 cycle of the conventional example. Also,
You only have to enter the input data once.

[0038]

[Equation 2]

(Second Embodiment) FIG. 5 is a circuit diagram showing a part of the configuration of a sorting apparatus according to the second embodiment of the present invention. As in the case of the first embodiment, the number of selected data is 4, and the data is sorted in descending order.

In FIG. 5, IN is input data, 101
Is a comparator, 102 is a register, 113 is a register file, and F1, F2, F3, and F4 are registers for storing the first, second, third, and fourth largest values, respectively.
Reference numeral 14 is a selection circuit, 105 is a multiplexer, 119 is a determination circuit for determining whether the input data is smaller than the least significant data of the register file 113, and 117 is an address generator for generating an address for reading and writing data in the register file 113. A circuit, 118 is an input request generation circuit for generating an input request signal requesting the next input data,
OUT is output data and NXT is an input request signal.

The operations of the comparator 101, the register 102, and the multiplexer 105 are the same as those in the first embodiment.

The address generation circuit 117 generates addresses for reading and writing to the register file 113 in the order of 1, 2, 3, 4, 1, 2, ... In synchronization with the clock.
When NXT = 1, the address generation is reset. When ADRS = 1, 2, 3, 4 is generated,
The register file 113 has F1, F2, and F, respectively.
3 and F4 are read and written. The selection circuit 114 selects either IN or B as shown in FIG. When the output of the determination circuit 119 is F, the input request generation circuit 118 outputs the input request signal NXT = 1 when ADRS = 1 and F = 1 or when ADRS = 4. . When NXT = 1, the next input data is input from IN.

The determination circuit 119 is specifically composed of a circuit as shown in FIG. In FIG. 7, 121 is a comparator, 1
22 is a register. Register 122 has ADRS = 4
Write D only when. That is, the same value as F4 of the register file 113 is stored in the register 122. The comparator 121 sets the value of the register 122 to E and calculates (AE). When the resulting MSB is F, A is larger when F = 0, and when F = 1,
E is larger.

In FIG. 8, the register 1 is synchronized with the next clock.
02, 112 and data to be written in the register file 113.

The input data IN is the register file 113.
F1 to F4 are sequentially compared. At the same time when comparing with F1, the value of the register 122 is also compared, and F4
When the data smaller than the data stored in is input, the comparison processing with F2 to F4 is not performed.

The operation of the sorting apparatus of the second embodiment when the same numerical value as that of the first embodiment is input in FIG. 9 will be described.

In the file register 113, F1 = 20
It is assumed that 0, F2 = 150, F3 = 100, and F4 = 50 are stored. Further, the same value as F4 is stored in the register 122. It is assumed that the input data IN = 20 and 120 are sequentially input. The selection circuit 114 receives the input data I
N is selected and IN = 20 is stored in the register 102 in synchronization with the first clock.

First clock: Since ADRS = 1,
B = F1 = 200. Since A = 20, AB
= -180 <0, C = 1. At this time, the multiplexer 105 selects F1 and is written in F1 in synchronization with the second clock. Also, since E = 50, A−
Since E = -30> 0 and F = 1, the input request generation circuit 11
8 outputs NXT = 1. Therefore, the following input data is input to IN. The selection circuit 114 selects IN,
The next input data is synchronized with the second clock and the register 10
2 is written. The address generation circuit 107 resets the address generation order.

Next, the operation when IN = 120 is input in response to the input request signal will be described.

Second clock: Since ADRS = 1,
B = F1 = 200. Since A = 120, A-
B = -80 <0 and C = 1. At this time, the multiplexer 105 selects F1 and is written in F1 in synchronization with the third clock. The selection circuit 114 selects IN,
It is written in the register 102 in synchronization with the third clock.

Third clock: Since ADRS = 2,
B = F2 = 150. Since A = 120, A-
B = -30 <0 and C = 1. At this time, the multiplexer 105 selects F2 and is written in F2 in synchronization with the fourth clock. The selection circuit 114 selects IN,
It is written in the register 102 in synchronization with the fourth clock.

Fourth clock: Since ADRS = 3,
B = F3 = 100. Since A = 120, A-
B = 20> 0 and C = 0. At this time, the multiplexer 105 selects A and synchronizes with F5 in synchronization with the fifth clock.
Is written to. The selection circuit 114 selects F3, and the fifth
It is written in the register 102 in synchronization with the clock.

Fifth clock: Since ADRS = 4,
B = F4 = 50. Since A = 100, AB
= 50> 0 and C = 0. At this time, the multiplexer 105 selects A and is written in F4 in synchronization with the sixth clock. At the same time, A is also written in the register 122 in synchronization with the sixth clock. Further, the input request generation circuit 118 outputs NXT = 1. Therefore, the following input data is input to IN. The selection circuit 114 selects IN and the next input data is written in the register 102 in synchronization with the sixth clock. The address generation circuit 107 resets the address generation order.

As described above, by the processing in the first to fifth clocks, F1, F2, F3, F4 = 200, 150, 100, 5
The sequence of data 0 is F1, F2, F3, F4 = 200, 150, 120, 1
You can see that it is sorted as 00.

The processing for two inputs of IN = 20 and 120 is completed in 1 + 4 = 5 cycles.

As in the first embodiment, assuming that N = 100 and half the 50 input data are smaller than the data stored in F4, the time required for sorting is ( Equation 3), and the first embodiment
It can be seen that the speed can be further improved than in the case of.

[0057]

(Equation 3)

[0058]

As described above, according to the sorting apparatus of the present invention, a desired number of data can be rearranged at a high speed by giving the target data only once.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a sorting device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an output of a selection circuit of the sorting apparatus according to the present embodiment.

FIG. 3 is a diagram showing values to be written in a register of the sorting device according to the present embodiment.

FIG. 4 is a timing diagram of the sorting apparatus according to the present embodiment.

FIG. 5 is a circuit diagram of a sorting device according to a second embodiment of the present invention.

FIG. 6 is a diagram showing an output of a selection circuit of the sorting device according to the present embodiment.

FIG. 7 is a configuration diagram of a determination circuit of the sorting device according to the present embodiment.

FIG. 8 is a diagram showing values written in a register of the sorting device according to the present embodiment.

FIG. 9 is a timing diagram of the sorting apparatus according to the present embodiment.

FIG. 10 is a diagram showing an example of a conventional sorting device.

[Explanation of symbols]

 101, 121 Comparator 102, 122 Register 103, 113 Register File 104, 114 Selection Circuit 105 Multiplexer 107, 117 Address Generation Circuit 108, 118 Input Request Generation Circuit 119 Judgment Circuit IN Input Data OUT Output Data NXT Input Request Signal

Claims (7)

[Claims] 1. A sorting device for selecting n pieces of data out of N pieces of input data, the first storage means storing one piece of data, and the second storage means storing n pieces of data. And one of the n data stored in the second storage means in response to a signal requesting input of new data.
Specifying means for specifying one, a comparing means for comparing the value of the first storing means with the value of the second storing means, the first using the output of the specifying means and the result of the comparing means. First selecting means for selecting either the input data or the value of the second storing means for the input of the storing means, and the input of the second storing means for the first using the result of the comparing means. Second selection means for selecting either the value of the storage means or the value of the second storage means, and a signal for requesting input of the new data using the output of the designation means and the result of the comparison means. And a sorting device having an input request generating means for outputting. 2. A sorting apparatus for selecting n pieces of data from N pieces of input data, the first storage means storing one data, and the second storage means storing n pieces of data. And one of the n data stored in the second storage means in response to a signal requesting input of new data.
Specifying means for specifying one, a comparing means for comparing the value of the first storing means with the value of the second storing means, the first using the output of the specifying means and the result of the comparing means. First selecting means for selecting either the input data or the value of the second storing means for the input of the storing means, and the input of the second storing means for the first using the result of the comparing means. Second selection means for selecting either the value of the storage means or the value of the second storage means, the output of the designation means, the value of the first storage means, and the output of the second selection means. A sorting device comprising: a determination unit that generates a determination signal by using the input unit; and an input request generation unit that outputs a signal requesting input of the new data by using the output of the designation unit and the determination signal. 3. The first selecting means uses the result of the comparing means to compare the input data and the second data.
A first multiplexer that selects one of the outputs of the storage means, a selection control circuit that receives the output of the designating means and generates a selection signal, and the input data using the output of the selection control circuit. A second selecting one of the outputs of the first multiplexer
The sorting device according to claim 1 or 2, wherein the sorting device comprises a multiplexer. 4. The specifying means generates an address of the lowest data of the n pieces of data stored in the second storage means, and thereafter, from the highest data to the lowest data. 2. The sorting device according to claim 1, wherein the sorting device is an address generating circuit capable of sequentially generating the addresses. 5. The second selection is made only when the specifying means specifies the lowest data of the n pieces of data stored in the second storage means. It comprises a third storage means capable of writing the output of the means, and a third comparison means for comparing the value of the first storage means with the value of the third storage means and outputting the determination signal. The sorting device according to claim 2, wherein 6. The sorting apparatus according to claim 1, wherein n pieces of N pieces of data are sorted in descending order. 7. The sorting device according to claim 1, wherein n pieces of N pieces of data are rearranged in ascending order.