JPH09304913A - Mask for lithography and manufacture thereof and manufacture of semiconductor integrated circuit device using the mask - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform pattern shape compensation of a mask for photo lithography at high speed. SOLUTION: When electronic line drawing data required for the manufacture by an electronic line drawing device of a mask for photo lithography is prepared based on design data 101, the design data 101 is converted into framing data 103 by OR operation 102, AND operation 112 is executed for width classification data 106-1 to 106-N obtained by classifying the framing data 103 by width classification 104 by using graphic operation and a workpiece 111 obtained by classifying the framing data 103 by distance classification 109 by using graphic operation, and dimensional compensation operation 113 is done for the results of the execution to add compensation which corresponds to a specific width condition and a distance condition to the design data 101. OR operation 115 is applied to outputs of the results of compensation 114-1 to 114-m to prepare the compensated design data 116, and the electronic line drawing data is prepared based on it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a design rule of
The present invention relates to a technique effectively applied to fine processing of a semiconductor integrated circuit device having a size of 35 μm or more.

[0002]

2. Description of the Related Art Current semiconductor integrated circuit devices such as LSI are
In many cases, a mask (or reticle) that is 5 to 10 times the size of an actual LSI is used, and it is created using a photolithography technique that forms a pattern on a wafer by optical transfer using a reduction projection exposure apparatus. It

The mask used for this photolithography is a functional design for designing a function to be realized as a semiconductor integrated circuit device, as described in "LSI Handbook", p260, published by Ohmsha, Ltd. on November 30, 1984. Layout design based on the design data of the logic design based on it and the circuit design data based on the device design, generate the data for pattern generator or electron beam drawing through the artwork process, and create based on this drawing data. It is something.

Further, the artwork processing is described in the same document, p2.
As described in 10 to p217, it is to verify whether or not there is any abnormality in the result of layout design. Design rule check, logical connection check (verification of short error, open error, element loss), logical function check, etc. Is to do. As an example of these verification methods, a graphic logic operation method can be cited.

[0005]

However, as a result of the high integration and large scale of LSIs in recent years and the reduction in element size, the problem of exposure light interference in the lithography process comes to occur. That is, when the width of the pattern or the distance between the patterns decreases, the interference of the exposure light occurs in that area, a portion that should not be exposed originally is exposed, and the exposure pattern is biased. As a result, the exposure pattern becomes thick in a region where interference occurs, such as a portion where the pattern distance is short, and the exposure pattern becomes thin in a region where it does not, such that the pattern dimension is biased according to the pattern interval.

Such unevenness of the exposure pattern causes a decrease in pattern accuracy, which in turn causes a decrease in yield.

Therefore, it is necessary to predict the deviation of the exposure pattern due to the effect of the interference of the exposure light at the design stage of the LSI and to correct the design pattern in advance according to the pattern width and the pattern interval. In other words, the thick part of the pattern is
It is necessary to make it thinner in advance and thicken the portion where the pattern becomes thinner.

As a method of this correction, a method of manually correcting the pattern shape can be considered. However, in the current situation where the number of patterns in the LSI has increased due to the large scale of the LSI, the shape correction of all patterns has to be performed manually. It is almost impossible to do.

An object of the present invention is to perform pattern shape correction at high speed and accurately.

Another object of the present invention is to provide a lithographic mask in which the shape of a pattern is accurately corrected at high speed.

Still another object of the present invention is to provide a manufacturing technique of a semiconductor integrated circuit device using the lithography mask.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A lithographic mask manufacturing method according to the present invention is a lithographic mask manufacturing method in which a mask pattern is formed by combining graphic elements.
(A) a step of performing a layout design based on LSI function and circuit design data, and generating first design data which is a set of layout pattern data; (b) first
The layout pattern data is corrected by adding a correction value specific to the width of the layout pattern included in the design data and the distance from the layout pattern adjacent to the layout pattern to the shape of the layout pattern, and the corrected layout pattern It includes a step of generating second design data which is a set of data, and (c) a step of generating drawing data based on the second design data, performing mask drawing, and forming a mask pattern.

According to such a method for manufacturing a lithography mask, the width of the layout pattern included in the first design data, which is a set of layout pattern data, and the distance from the layout pattern adjacent to the layout pattern are unique. Since the layout pattern data is corrected by adding the correction value to the shape of the layout pattern, the correction according to the pattern shape can be performed.

Further, since the lithography mask manufactured by such a manufacturing method is corrected according to the shape of the pattern, the processing accuracy of the semiconductor integrated circuit device manufactured using this mask is improved. The height can be increased, and defects in the semiconductor integrated circuit device can be reduced and yield can be improved.

(2) The method for manufacturing a lithography mask of the present invention is the method for manufacturing a lithography mask according to (1) above, wherein the layout pattern data is corrected.
The layout pattern is classified by graphic calculation according to the width and the distance, and a correction value unique to this classification is added to the shape of the layout pattern.

According to such a method for manufacturing a lithography mask, the layout pattern data is corrected by classifying the layout pattern data by a graphic operation according to the width and the distance of the layout pattern, and then the correction value unique to this classification is calculated for the layout pattern. Since the shape is added to the shape, in addition to the effect described in (1), the correction work can be automated, and the correction can be executed quickly and accurately. That is, the graphic operation used in the artwork processing is also used for the correction work, and the conventional design environment resources can be effectively used. As a result, it is possible to carry out the present invention without changing the conventional design method except for programming work, etc., so that the present invention can be implemented easily and at low cost, streamlining the design work and reducing the design period. It can be shortened. Further, it becomes possible to correct all of the enormous amount of layout pattern data, and it is possible to perform the correction work which cannot be done manually. Further, since there is no need to change the conventional design data structure, the consistency with the conventional design work is high and the conventional design data resource can be utilized.

(3) A method for manufacturing a lithographic mask according to the present invention is the method for manufacturing a lithographic mask according to (1) or (2) above, wherein the step (b) is to generate the second design data. Is (d) a step of generating framed data by performing an OR operation by graphic operation on the first design data, (e) a step of extracting a rectangular graphic element from the framed data, (f) a graphic A step of classifying an element by a figure calculation according to the width and a distance to a figure element adjacent to the figure element to generate width category data and distance category data; (g) figure belonging to the width category data and the distance category data Among the elements, a step of performing a correction operation for adding a correction value specific to the width condition and the distance condition to the graphic data that matches the width condition and the distance condition to correct the graphic element,
(H) a step of performing an OR operation by a graphic operation on the corrected graphic element to generate second design data which is a set of the corrected layout pattern data.

According to such a method for manufacturing a lithographic mask, since the framed data is generated by performing the OR operation by the graphic operation, it is possible to reduce the target data when executing the subsequent data classification. Therefore, the calculation speed can be improved.

Further, according to the method for manufacturing a lithographic mask of the present invention, since a rectangular graphic element is extracted from the framed data, it is possible to target the subsequent data classification and correction calculation to the graphic element. The shape of the layout pattern is not generally limited to a square such as a square or a rectangle, but has a complicated shape formed by an arbitrary combination of these squares. When layout patterns having such a complicated shape are close to each other, it is not possible to unambiguously determine in which area the interference occurs. Therefore, in the present invention, the layout pattern is decomposed into rectangular graphic elements, the effect of interference is uniformly simulated by the width of the graphic elements and the distance between the graphic elements, and correction is added to compensate for this effect. It is a thing. That is, in the present invention, the graphic element has a basic shape which is the basis of the correction calculation.

According to the method for manufacturing a lithographic mask of the present invention, the graphic element is classified by the graphic operation according to the width and the distance between the graphic element and the graphic element adjacent to the graphic element, and the width classification data and the distance classification data are classified. Is generated, and the correction calculation for adding the correction value specific to the width condition and the distance condition is performed on the graphic element that matches the width condition and the distance condition. Therefore, if the layout pattern is determined, the correction calculation is uniquely performed. Can be executed. Further, since the correction value is not calculated as the specific functional relationship between the graphic elements and the specific functional relationship between the graphic elements, but a method of classifying the correction values according to the width and the distance is adopted, the calculation speed can be improved, and Since the classification width can be determined arbitrarily,
It is possible to reflect the results of examination by experiments and make use of the knowledge obtained from experience. Furthermore, because it uses graphic operations, it ensures consistency with conventional design work, and at the same time,
It is possible to improve the calculation speed.

The width condition, the distance condition, and the correction value are determined by an experimental examination, and change depending on the process adopted, for example, the resist material, the resist film thickness, the etching process, the etching condition, the etchant, and the like. It is a thing. Before the design work, it is necessary to clarify the optimum value according to the process to be adopted in advance by examination and examination.

The width classification and the distance classification may be performed independently, but either the width classification or the distance classification may be performed first, and the other classification may be performed on the graphic elements belonging to the classification. Good. In that case, since the number of graphic elements to be classified can be reduced, the calculation speed can be improved.

Further, according to the method for manufacturing a lithographic mask of the present invention, since the corrected graphic element is subjected to the OR operation by the graphic operation, the consistency with the drawing data in the next step can be improved. That is, the present invention can be implemented without changing the conventional design work process.

(4) The lithographic mask of the present invention comprises:
A lithographic mask in which a mask pattern is formed by a combination of graphic elements, wherein the graphic elements are classified by the width of the graphic element and the distance classification by the distance from the graphic element adjacent to the graphic element. Graphic elements belonging to the same classification of the width classification and the distance classification have their shapes corrected by the same correction value.

According to such a lithographic mask, the graphic elements constituting the mask pattern are classified according to the width of the graphic element and the distance to the adjacent graphic element, and the graphic elements belonging to the same classification of the width classification and the distance classification are Since the shape is corrected by the same correction value, the shape of the mask pattern can be corrected according to the width of the mask pattern and the distance between the mask patterns. By using such a mask, the processing accuracy of the semiconductor integrated circuit device is improved, and it is possible to improve the reliability and the yield.

Further, since the same correction value is applied according to the classification, the correction work in the mask design work can be simplified.

(5) The lithographic mask of the present invention comprises:
The lithographic mask according to (4), wherein the correction is such that the smaller the width of the graphic element or the shorter the distance between the graphic elements, the smaller the area of the graphic element.

According to such a lithographic mask, the correction is performed such that the smaller the width of the graphic elements, the shorter the distance between the graphic elements, and the smaller the area of the graphic elements. Can be corrected so as to compensate for the interference light. As a result, the processing accuracy of the semiconductor integrated circuit device manufactured using such a mask can be improved, and the reliability and the yield can be improved.

(6) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the photoresist formed on the main surface of the semiconductor substrate is irradiated with light shaped by the mask pattern of the lithography mask to pattern the photoresist. Then, a method of manufacturing a semiconductor integrated circuit device including a photolithography step of forming a constituent member of a semiconductor integrated circuit formed on a main surface of a semiconductor substrate by etching a thin film along a resist pattern formed by patterning. As a lithographic mask, the resist patterns are classified with respect to the width of the resist pattern and the distance between the resist pattern and the resist pattern adjacent to the resist pattern. The narrower the width or the shorter the distance, the mask pattern corresponding to the resist pattern. Small area And it is characterized in the use of a mask for lithography.

According to such a method of manufacturing a semiconductor integrated circuit device, the smaller the width of the resist pattern or the shorter the distance from the resist pattern adjacent to the resist pattern, the smaller the area of the mask pattern corresponding to the area. Since the mask for lithography that is made small is used, it is possible to compensate the effect of light interference and improve the processing accuracy of the semiconductor integrated circuit device. As a result, the reliability and yield of the semiconductor integrated circuit device can be improved.

[0033]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a conceptual diagram showing an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, from the design data to the creation of electron beam drawing data, and FIG. 3 is a flowchart showing an example of a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

First, a method of manufacturing the semiconductor integrated circuit device of this embodiment will be described with reference to the flow chart of FIG.

First, a layout design is performed based on LSI function and circuit design data, and first design data, which is a set of layout pattern data, is generated (step 201).

The design data generated in step 201 is a set of individual layout patterns for one mask, and the layout patterns are overlapped or joined. Each layout pattern constitutes a functional element such as a gate electrode and a diffusion region window in a semiconductor integrated circuit device. The generation of these layout patterns is no different from the conventional layout design technique, and thus detailed description thereof is omitted.

Next, a graphic calculation program is executed on the first design data (step 202) to generate second design data (step 203).

In step 203, the layout pattern is corrected in order to generate the second design data, which is a set of corrected layout patterns. The details will be described later.

Next, electron beam drawing data is created based on the second design data (step 204) and stored as graphic drawing data (step 205).

Since the layout pattern included in the second design data is stored as graphic data, it is converted into electron beam drawing data which can be handled by the electron beam drawing apparatus in step 204. To do.

Next, based on the electron beam drawing data,
The electron beam drawing apparatus is operated (step 205) to manufacture a lithographic mask that is a workpiece (step 2).
06).

The lithographic mask manufactured in step 206 has a mask pattern corresponding to the corrected layout pattern. Step 205
Since the processing accuracy is generally high, it is considered that the deviation of the pattern shape at the time of forming the mask pattern is not so large. However, the correction of the layout pattern shape in step 202 can also be corrected by including the deviation of the pattern shape in step 205. A well-known technique can be used for the electron beam drawing apparatus and the lithography technique for the resist used therein, and thus detailed description thereof will be omitted.

Next, the mask formed in step 206 is set in a reduction projection exposure apparatus, and the photoresist formed on the wafer is exposed (step 207) to form gate electrodes or the like constituting the semiconductor integrated circuit device on the wafer. The constituent members are formed (step 208).

In step 207, when the mask patterns are close to each other or the width of the mask pattern is narrow, there is a phenomenon that the pattern of the light irradiated on the resist becomes thick due to the interference of the exposure light. In the lithographic mask of this embodiment, since the mask pattern has been corrected in advance to compensate for the interference effect of light, the pattern of light irradiated on the resist is
It is optimized to be processed as designed, including interference effects.

Therefore, the semiconductor integrated circuit device manufactured by the method for manufacturing a semiconductor integrated circuit device according to the present embodiment is processed with high precision, so that the reliability is high and the yield can be increased. It is a thing.

Next, the layout pattern correction process by the graphic operation in step 202 will be described with reference to FIG.

The design data 101 is the first design data generated in step 201 in FIG. As described above, the design data 101 contains layout pattern data corresponding to each layout pattern.

Next, the design data 101 is subjected to the OR operation 102 to generate the framed data 103.

Since the layout patterns included in the design data 101 have overlaps and the like with each other, the OR
By performing the operation 102, the overlapping portion can be removed.

Next, the width classification 104 is executed on the framed data 103.

The width classification 104 verifies by the width check calculation 105 whether or not the graphic element included in the framed data 103 conforms to the width condition. It is allocated to the width classification data 106-1 and at the same time, the deletion operation 107 for removing the matching graphic element from the framed data 103 is executed.

The framing data after the delete operation 107 has been executed is stored as the input 108 of the next width classification,
The width check calculation 105 for the second time is executed. It goes without saying that the width condition of the second width check calculation 105 is a width condition unique to the second time different from the width condition of the first time. Also, a graphic element that meets the second width condition is assigned to the second width classification data 106-2, and the graphic element is deleted by the delete operation 107 as in the first operation. Is.

The width classification 104 is the width check calculation 1 described above.
05 and the deletion operation 107 are repeated N times, which is the number of width classifications, and the first width classification data 106-1 to the Nth width classification data 106-n are created, and the process ends.

The width condition and the number of width classifications in the width classification 104 are determined by the designer in consideration of the light interference effect in the actual lithography process. As specific values, the lower limit of the width condition is set in the range of 0.05 μm to 0.2 μm, the upper limit is set in the range of 2 μm to 10 μm, and the width classification step is set to 0.
It can be in the range of 05 μm to 0.2 μm. The number of width classifications is uniquely determined by determining the upper and lower limits of the width condition and the width classification step.

The width check calculation 105 is not performed for each layout pattern, but for each graphic element included in the layout pattern. Therefore,
When the layout pattern includes a plurality of graphic elements and only some of the graphic elements meet the width condition, only some of the graphic elements of the layout pattern are deleted.
It will be deleted by 7. Eventually, the layout pattern is decomposed into graphic elements and the width classification data 106-1 to
It will be assigned to any of 106-n.

As described above, the layout pattern is classified by the width classification 104 according to the width designated by the designer.

Next, the distance classification 109 is executed.

The distance classification 109 verifies by the distance check calculation 110 whether or not the graphic element included in the framed data 103 conforms to the distance condition.
It is executed by extracting the graphic element into the work 111.

AN for the graphic elements extracted on the work 111 and the graphic elements included in the width classification data 106-1
The D operation 112 is executed, and the dimension correction operation 113 is executed on the graphic element resulting from the execution of the AND operation 112.
That is, a graphic element satisfying both the width condition corresponding to the width classification data 106-1 and the distance condition is extracted,
A dimensional correction is added to this graphic element. The correction executed in the dimension correction calculation 113 is to add a correction value specific to the width condition and the distance condition to the graphic element. The narrower the width of the graphic element is or the shorter the distance between the graphic elements is, It is possible to correct in the direction of decreasing the area. Specific numerical values will be described later. The execution result of the dimension correction calculation 113 is stored as the output 114-1.

AND operation 1 with the graphic element of the work 111
12 and the dimension correction calculation 113, the width classification data 106
All of the width classification data from -2 to 106-n are executed, and the calculation results are output to 114-2-1.
Stored as 14-n.

Next, the contents of the work 111 are cleared,
Distance check calculation 11 to see if the following distance conditions are met
0 is executed. Store the execution result of the distance check calculation 110 in the work 111 and the width classification data 106-1
The AND operation 112 and the dimension correction operation 113 with 106-n are as described above.

This distance check operation 110 is repeated p times, which is the number of distance classifications, and eventually m = n × p output 114
-1 to 114-m will be stored.

The distance condition and the number of distance classifications in the distance classification 109 are determined by the designer in consideration of the light interference effect in the actual lithography process. As a specific value, the lower limit of the distance condition is in the range of 0.3 μm to 0.4 μm,
The upper limit can be in the range of 3 μm to 4 μm, and the step of distance classification can be in the range of 0.3 μm to 0.5 μm. The distance classification number is uniquely determined by determining the upper and lower limits of the distance condition and the distance classification step.

As a concrete example of the correction value, in the case of a gate electrode pattern having a width of 0.3 μm as a graphic element, when the pattern interval is 0 μm or more and less than 2.8 μm, the correction amount on one side is 0 nm, 2 When 0.8 μm or more and less than 10 μm-
When it is 5 nm or 10 μm or more, it can be set to −10 nm. Also, the relative positional relationship between graphic elements can be considered.

The point that the distance check calculation 110 is not performed for each layout pattern is that the width classification 10
The same as in the case of No. 4.

Finally, O is output to the outputs 114-1 to 114-m.
The R calculation 115 is performed, the corrected design data 116 is output, and the layout pattern correction process by the graphic calculation in step 202 ends.

FIG. 3 shows a pattern formed by the manufacturing method of this embodiment. 3A is a design pattern of the LSI, FIG. 3B is a pattern after the graphic calculation processing, and FIG. 3C is a pattern to be formed on the wafer.

Design pattern 301 in FIG. 3 (a)
Is corrected so that the area of the graphic element 303 after correction becomes smaller in the narrow region 302 as shown in FIG. 3B, and conversely, in the wide region 304 of the design pattern 301, The area of the graphic element 303 is corrected to be large. In the pattern 305 to be formed formed on the wafer using the mask created by the pattern thus corrected, the pattern becomes thick due to the interference effect of the exposure light in the region where the distance between the patterns is narrow, and the interference effect does not occur. In the region, the pattern becomes thin due to the effect of etching, and eventually the pattern becomes almost the same as the design pattern 301.

According to this embodiment, the following effects can be obtained.

(1) Since the width classification 104 and the distance classification 109 are performed by using the figure calculation and the correction values specific to the width condition and the distance condition are added to the shape of the layout pattern, the dimension correction calculation according to the pattern shape is performed. 113 can be performed.

Since the lithography mask manufactured by such a manufacturing method is corrected according to the shape of the pattern, the processing accuracy of the semiconductor integrated circuit device manufactured using this mask is increased. Therefore, it is possible to reduce defects and improve the yield of the semiconductor integrated circuit device.

(2) Since the graphic operation is used, the correction work is automated, and the width classification 104 and the distance classification 10 are quickly and accurately performed.
9 and dimension correction operation 113 can be performed.

Therefore, it is possible to realize a dimension correction work which cannot be performed manually, and it is possible to perform a high-speed and accurate correction process.

(3) Since the framed data 103 is generated by performing the OR operation 102, the target data after that can be reduced and the operation speed can be improved.

(4) Since the width condition, the distance condition, and the classification width can be arbitrarily determined, the result of the examination by the experiment can be reflected and the experience can be utilized.

(5) Since the graphic operation is used, it is possible to ensure the consistency with the conventional design work and at the same time improve the operation speed.

(6) Since the corrected graphic element is subjected to the OR operation 115 by a graphic operation, the consistency with the drawing data in the next process can be improved.

(7) Since the same correction value is applied according to the classification, the correction work in the mask design work can be simplified.

(8) Since the dimension correction calculation 113 is performed so that the area of the graphic elements is reduced as the width of the graphic elements is narrower or the distance between the graphic elements is shorter, the portion where the interference of exposure light is likely to occur. Can be corrected to compensate for the interference light.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it can be changed.

For example, in this embodiment, the width classification 10
Although the example in which the distance classification 109 is executed after executing 4 has been described, this may be reversed.

[0083]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) In the method of manufacturing a lithographic mask, the layout pattern data is corrected by adding correction values specific to the width of the layout pattern and the distance between the layout pattern and an adjacent layout pattern to the shape of the layout pattern. Therefore, it is possible to perform correction according to the pattern shape.

(2) Since the lithography mask manufactured by the manufacturing method of the present invention is corrected according to the shape of the pattern, the processing accuracy of the semiconductor integrated circuit device manufactured using this mask is improved. Therefore, it is possible to reduce the defects and improve the yield of the semiconductor integrated circuit device.

(3) Since the correction of the layout pattern data is performed by classifying the layout pattern data by a graphic operation according to the width and distance of the layout pattern, and adding a correction value specific to this classification, the above (1) or (2) In addition to the effect described in (1), the correction work can be automated, and the correction can be performed quickly and accurately.

As a result, the present invention can be implemented easily and at low cost without changing the conventional design method.
It can streamline the design work and shorten the design period.

(4) It becomes possible to correct all of a huge amount of layout pattern data, and it is possible to perform a correction work that cannot be done manually.

(5) Since there is no need to change the conventional design data structure, the consistency with the conventional design work is high, and the conventional design data resource can be utilized.

(6) Since the framed data is generated by performing the OR operation by the graphic operation, it is possible to reduce the target data when executing the subsequent data classification, and to improve the operation speed. it can.

(7) Since the rectangular graphic element is extracted from the framed data, the graphic data can be targeted for the subsequent data classification and correction calculation. As a result, even when layout patterns having complicated shapes are close to each other, the effect of interference is uniformly predicted by the width of the graphic element and the distance between the graphic elements, and the effect is compensated. Corrections can be added.

(8) To classify graphic elements by graphic calculation according to their widths and distances between graphic elements, and to perform correction calculation for adding a unique correction value to graphic elements that meet the width condition and the distance condition. If the layout pattern is determined, the layout pattern is uniquely classified, and the correction calculation can be executed. As a result, the calculation can be simplified and the calculation speed can be improved.

(9) Since the corrected graphic element is subjected to the OR operation by the graphic operation, the consistency with the drawing data in the next process can be improved.

(10) Since the correction is performed so that the width of the graphic element is narrower and the distance between the graphic elements is shorter, the area of the graphic element is smaller. It can be corrected to compensate for the interference light.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention from design data thereof to generation of electron beam drawing data.

FIG. 2 is a flowchart showing an example of a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 3A is a design pattern of an LSI, and FIG.
Is a pattern after the graphic calculation processing, and (c) is a pattern to be formed on the wafer.

[Explanation of symbols]

 101 Design Data 102 OR Operation 103 Framed Data 104 Width Classification 105 Width Check Operation 106-1 to 106-n Width Classification Data 107 Deletion Operation 108 Next Width Classification Input 109 Distance Classification 110 Distance Check Operation 111 Work 112 AND Operation 113 Dimension correction operation 114-1 to 114-m output 115 OR operation 116 corrected design data 301 design pattern 302 narrow area 303 graphic element 304 wide area 305 formed pattern

Claims (6)

[Claims] 1. A method of manufacturing a lithographic mask in which a mask pattern is constituted by a combination of graphic elements, comprising: (a) performing a layout design based on design data of an LSI function and a circuit, and collecting a set of layout pattern data. And (b) a correction value specific to the width of the layout pattern included in the first design data and the distance from the layout pattern adjacent to the layout pattern to the layout. Correcting the layout pattern data by adding it to the shape of the pattern and generating second design data which is a set of the corrected layout pattern data, (c) drawing data based on the second design data And mask drawing to form the mask pattern. Method of manufacturing a mask for lithography characterized by and. 2. The method for manufacturing a lithography mask according to claim 1, wherein the correction of the layout pattern data classifies the layout pattern by a graphic operation according to the width and the distance, and is unique to the classification. Is added to the shape of the layout pattern. 3. The method for manufacturing a lithographic mask according to claim 1, wherein the step (b) of generating the second design data includes: (d) adding a graphic to the first design data. Generating framed data by performing an OR operation by calculation, (e) extracting a rectangular graphic element from the framed data, (f) adhering the graphic element to its width and to the graphic element A width condition and a distance among the graphic elements belonging to the width classification data and the distance classification data. A step of correcting the figure element by performing a correction operation for adding a correction value specific to the width condition and the distance condition to the figure element that matches the condition, and (h) drawing the corrected figure element A step of performing an OR operation by a shape operation to generate second design data which is a set of corrected layout pattern data, and a method for manufacturing a lithography mask. 4. A lithographic mask, wherein a mask pattern is formed by a combination of graphic elements, wherein the graphic element includes a width classification classified by the width of the graphic element, and a graphic element adjacent to the graphic element. The lithographic mask characterized in that the shape elements of the graphic elements belonging to the same one of the width classification and the distance classification are corrected by the same correction value. . 5. The lithographic mask according to claim 4, wherein the correction reduces the area of the graphic element as the width of the graphic element becomes narrower or as the distance between the graphic elements becomes shorter. A mask for lithography, which is characterized by being a thing. 6. The photoresist formed on the main surface of a semiconductor substrate is irradiated with light shaped by a mask pattern of a lithography mask to pattern the photoresist, and the photoresist pattern is formed along the resist pattern. A method of manufacturing a semiconductor integrated circuit device having a photolithography step of forming a constituent member of a semiconductor integrated circuit formed on a main surface of a semiconductor substrate by etching a thin film with a resist as the lithography mask. The resist patterns are classified with respect to the width of the pattern and the distance between the resist pattern and the resist pattern adjacent to the resist pattern, and the narrower the width or the shorter the distance, the smaller the area of the mask pattern corresponding to the resist pattern. Risog The method of manufacturing a semiconductor integrated circuit device, which comprises using Ficoll mask.