JPH09293065A - Two-dimensional pe array device, associative memory, data transfer method and morphology arithmetic processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a PE array device with high performance by suppressing a whole data transfer time and reducing hardware quantity. SOLUTION: In a two-dimensional PE array device PEA1, PE arrayed in X×Y is divided into the blocks of q-columns in a longitudinal direction and r-rows in a horizontal direction and one associative memory 11 is assigned to the respective divided blocks. X is the number of PEs in the longitudinal direction, Y is the number of PEs in the horizontal direction, X=Mq and Y=nr are more than two optional integers and (q) and (r) are more than two optional numbers. In the assigned respective associative memories 11(1 ,1) , w pieces of words 12 are divided by (X÷q), arrayed in a zigzag state to be (X÷q)×(Y÷r) and successively assigned to the blocks of PE. The high-order shift input/output of the one associative memory 11 is connected to the low-order shift input/output of another associative memory 11 being adjacent to the horizontal direction by an inter-associative memory hit flag shift line 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-dimensional processing element (PE) array device, an associative memory, a data transfer method, and a morphology operation processing method which are effective for image processing, sound processing, knowledge processing and the like. Regarding

[0002]

2. Description of the Related Art Visualization of network services,
The need for advanced image processing, sound processing, and knowledge processing is increasing due to higher added value. However, such processing generally requires enormous processing performance, so an existing microprocessor based on Neumann architecture,
It is often difficult to execute with a signal processor.

As a device for effectively performing such processing,
A two-dimensional PE array device is known. This two-dimensional PE
The array device includes a large number of PEs that perform various logic and arithmetic operation processes, and a single control circuit that gives a single instruction sequence to each PE by a single instruction stream / multiple data stream method (SIMD). Prepare This two-dimensional PE
The array device is a device that holds a mechanism in which each PE simultaneously performs the above-mentioned arithmetic processing by these circuits and methods and a data transfer mechanism to a neighboring PE in the two-dimensional direction.

A cellular automaton for efficiently allocating various processes in a two-dimensional PE array device,
A calculation theory such as a cellular neural network is known. Regarding the above-mentioned cellular automata and cellular neural net, "Chua, LO et al," C
ellular Neural Networks: T
"", IEEE Trans. on Circ
uits and Systems, Vol. 35,
No. 10 Oct. 1988 ”.

FIG. 28 shows a conventional two-dimensional PE array device P.
It is a figure which shows EA11.

In a device known as a conventional two-dimensional PE array device, a PE 202, which is composed of a microprocessor or an integrated circuit having a logic and arithmetic operation circuit, is formed into a two-dimensional form as shown in FIG. X × Y (X is the vertical direction,
Y is the number of PEs in the horizontal direction. X and Y are integers of 2 or more), and each of them is arranged in a data transfer path 203 in the two-dimensional vertical and horizontal directions.
It is a device combined with.

However, in this conventional example, when the number of PEs is large, a large number of data transfer paths 203 are required, and the hardware amount of the entire two-dimensional PE array device is large.

Further, when the PEs 202 are arranged two-dimensionally, it is generally difficult to increase the degree of integration of the PEs, and from this point also there is a problem that the amount of hardware increases. Further, as the number of PEs 202 increases, the data width in the data input / output 201 increases, which makes it difficult to exchange data with the outside.

In this case, if a mechanism for compressing the data width in the data input / output 201 is added, it becomes easy to exchange data with the outside. However, when the data width compression mechanism is added, it is difficult to provide expandability such that the number of PEs 202 can be changed.

FIG. 29 shows a conventional two-dimensional PE array device P.
It is a figure which shows EA12.

A device known as another example of the conventional two-dimensional PE array device is a PE 21 which is composed of a microprocessor or an integrated circuit having a logic and arithmetic operation circuit.
29, as shown in FIG. 29, X × Y pieces are connected by a data transfer path 213 only in one-dimensional direction.
Z is laid out in a zigzag pattern, and a pseudo X × Y 2
This is a device for realizing a three-dimensional PE array device.

In the case of this device, the P adjacent to each other in the two-dimensional direction
As a data transfer method to the E212, a method of using the one-dimensional data transfer path 213 and using the PE 212 as a bridge can be considered.

However, in this method, the data transfer between the PEs in the horizontal direction in FIG. 29 needs to be performed through X PEs, resulting in a long transfer time, resulting in a huge transfer time. The problem arises that

Although a method of providing a dedicated path can be considered in order to shorten the transfer time between the PEs in the horizontal direction, this method is different from the method using the data transfer path 203 in the vertical and horizontal two-dimensional directions. Similarly, since the number of data transfer paths increases, there is a problem that the amount of hardware is large.

FIG. 30 is a diagram showing a conventional associative memory M11.

In FIG. 30, the conventional associative memory M11 is used.
Is a word 224 ₍₁₎ to a word 224 _(w) , a mask register 222, an address decoder 225, and a word 2
24 ₍₁₎ to word 224 _(w) and a hit flag register 227 that can be used as a one-dimensional data transfer path. This associative memory M11 is called "Ogur
a, T .; et al. "A 20-kbit Asso
passive Memory LSI for Ar
tactical IntelligenceMach
ines ”, IEEE J. Solid-State
Circuits Vol. 24, No. 4, pp. 1
014-1020 Aug. 1989 ".

The associative memory M11, like an ordinary memory, gives an address value to the address input 223, so that an arbitrary word 224 ₍₁₎ to word 224 _{(w) can be obtained.}
It also has a function to read and write data to, and also has a mask search function and a parallel partial write function. By using these functions, various logic and arithmetic operations can be executed simultaneously on all words. it can. Therefore, by using this associative memory in a two-dimensional PE array device, it can be used as a massively parallel computing device having an extremely large number of PEs.

However, word 224 ₍₁₎ to word 224
_{Since the} hit flag register 227 that can be used as a one-dimensional data transfer path between _(w) has only a unidirectional shift mode of shift up or shift down,
In the above conventional example, word 224 ₍₁₎ to word 224
There is a problem that the direction of efficiently performing data transfer between _(w) is limited to a specific direction. Also, because it does not have a mode to read and write data and shift simultaneously,
In the above-mentioned conventional example, there is a problem that the data transfer processing and the like cannot be efficiently performed.

Therefore, when a two-dimensional PE array device is constructed using the associative memory, there is a problem that the data transfer time becomes long.

[0020]

In many image processing algorithms, it is often effective to directly allocate pixels in an image to a two-dimensional PE for processing. For example, if 256 pixels × 256 pixels = 65.536,
Since many PEs are required, a two-dimensional PE array device capable of mounting many PEs is required. In this case, part 2
If a two-dimensional PE array device is composed of a large number of boards, the cost of those devices becomes enormous.
It is hoped that this can be realized with the amount of hardware equivalent to the board.

Many of the image processing and the like require real-time processing. Therefore, in various image processing, a two-dimensional PE array device capable of real-time processing by suppressing the processing time in each PE and the data transfer time to the adjacent PE in the two-dimensional direction is desired. .

The parallelism in image processing, acoustic processing, knowledge processing, etc. varies depending on each processing, and therefore the PE configuration of the required two-dimensional PE array device also varies. From this point, a highly expandable two-dimensional PE array device capable of arbitrarily changing the PE configuration is desired.

A first object of the present invention is to provide a two-dimensional PE array device, an associative memory, and a data transfer method which have a small amount of hardware, a short transfer time, and high expandability.

The morphological operation processing is a theoretical system in which a method of transforming a target image to be constructed by a set theory operation is consistent, and is widely used in feature extraction, shape description, shape recognition processing for a binary image or a grayscale image. Has been. For details of the morphological operation processing method, refer to “P.
maragos, "Tutorial on adva"
nces in morphological image
ge processing and analysis
s ", Optical Engineering, Vo
l. 26 No. 26. 7, 1987 "and the like.
As a conventional morphology operation processing device, "MH
assoon, et al "A VLSI gray
-Scale morphology process
or for real-time NDE image
e processing application
s ", SPIE, Vol. 1350 Image Al
gebra and Morphological I
"Mage Processing, 1990".

FIG. 31 is a diagram showing a conventional morphology arithmetic processing unit MS0.

This conventional morphology arithmetic processing unit M
S0 is a 5 × 5 PE array 83 and an exclusive OR 81
And a comparator 82 and the like, and performs the morphological operation processing by performing scanning, arithmetic operation processing, and comparison operation processing on the original image by the PE array 83.

However, the conventional morphological operation processing device MS0 has a problem that it cannot process a large structural element of 5 × 5 or more, which is the size of the PE array 83. Further, since a processing time proportional to the size of the original image is required, there is a problem that when processing a large original image, the morphology calculation processing time becomes long. Further, in order to be able to process a large structural element, the number of PE arrays 83 must be increased, and due to this increase, the number of wires between adjacent PEs increases and the amount of hardware increases. is there.

In order to apply the morphological operation processing to various image processings, it is necessary to be able to perform real-time processing (video rate) on a large original image and a large structuring element. A morphological operation processing device capable of processing is desired.

A feature of the morphological operation processing is that it can be processed only by the local operation of the original image, which is extremely parallel. Therefore, in order to realize a high-performance morphology operation processing device, it is sufficient to maximize the feature of high parallelism and realize a morphology operation processing device having the same number of PEs as the number of pixels.

However, when realized in this way, a large number of PEs of about 260,000 pixels are required to process a realistic original image, for example, an original image of 512 pixels × 512 pixels. Therefore, a morphological operation processing device capable of mounting many PEs is required.

A large number of boards are required to realize such a device, and the cost of the device becomes enormous. Therefore, in the morphology operation processing device having a large number of PEs as described above, it is desired that the morphology operation processing device can be realized with a hardware amount of about one board in order to keep the cost low.

A second object of the present invention is to provide a morphological operation processing method using a two-dimensional PE array device having a high performance and a small amount of hardware.

[0033]

According to the first aspect of the present invention,
W words (where w is an arbitrary natural number) arranged in one dimension, a hit flag register that can be shifted up and down, an upper shift input / output and a lower shift input that put the contents of this hit flag register in and out. Of associative memories having q and r (q and r are arbitrary integers of 2 or more) having an output and one of the associative memories of the associative memories that are laterally adjacent to each other. Each of the hit flag shift line connecting the lower shift input / output and the shift input / output of the other associative memory of the horizontally adjacent associative memories and w words of the associative memory are m columns, n rows (w, m, n is w = mXn
PEs arranged in a zigzag pattern that satisfy any natural number that satisfies
Are sequentially allocated to m × q in the vertical direction and n in the horizontal direction.
Xr PEs are provided.

Here, in claim 1, the control section for generating a single control instruction stream for the associative memory array section including the associative memory and the hit flag shift line can be further provided. .

Here, in claim 1, a plurality of PEs are allocated to one word of the associative memory, and one PE among the PEs is assigned to the current state field of its own PE and the next state of its own PE. A field and each status field of adjacent PEs may be further provided.

According to a fourth aspect of the present invention, data writing / reading means for a word using an address, shift mode means of a hit flag register, data writing / reading means for a word using the address, and the hit are described. And a mode means for simultaneously executing the shift mode means of the flag register.

Here, in the associative memory according to any one of claims 1 to 3, the associative memory includes means for writing and reading data to and from a word using an address, shift mode means for a hit flag register, and a word using the address. It is possible to have a mode means for simultaneously executing the data writing and reading means and the shift mode means of the hit flag register.

According to a sixth aspect of the present invention, a step of arranging w words (where w is an arbitrary natural number) in one dimension, and q × r
Between associative memories (q and r are arbitrary integers of 2 or more),
A step of transferring data by moving the contents of the hit flag register capable of shifting up and down by using the upper shift input / output and the lower shift input / output to transfer the data; Connecting a lower shift input / output of one associative memory of the associative memory and the shift input / output of the other associative memory of the laterally adjacent associative memories by a hit flag shift line, Arranging w words in the associative memory in m columns and n rows (m and n are arbitrary natural numbers satisfying w = mxn) in a zigzag pattern, and assigning each of the w words in the associative memory to PEs And a step that is performed.

Here, in claim 6, the step of allocating a plurality of PEs to one word of the associative memory, and one PE of the plurality of PEs has a current state field of its own PE and the own PE. The next state field of each PE and the current state field of each adjacent PE may be further provided in the one word.

According to an eighth aspect of the invention, a step of arranging w words (where w is an arbitrary natural number) in one dimension, and q × r
Between associative memories (q and r are arbitrary integers of 2 or more),
A step of transferring data by moving the contents of a hit flag register capable of shifting up and down by using the upper shift input / output and the lower shift input / output to transfer the data; and the associative memory arranged in q columns in the vertical direction. Of the associative memory group of odd columns to the associative memory group of even columns,
Alternatively, a step of simultaneously performing data transfer from the associative memory group of even columns to an associative memory group of odd columns, and a step of simultaneously performing the data transfer to all the associative memories arranged in r rows in the horizontal direction. It is characterized by having.

According to a ninth aspect of the present invention, a step of arranging w words (where w is an arbitrary natural number) in one dimension and a part of the search data by collating the data stored in the words with the search data. The step of performing a mask search that ignores the collation, and the step of transferring the content of a specific bit in the first word designated by the mask search to a first hit flag register capable of shifting up and down. Shifting up or down the contents of the first hit flag register to the second hit flag register of the second word of the transfer destination; and searching data for the second word whose second hit flag register has a specific value. Using parallel partial write, which writes the search data to the bits of the second word corresponding to the unmasked bits,
Transferring the contents of the second hit flag register to a particular bit in the second word.

According to the tenth aspect of the present invention, the steps of writing and reading data to and from the word using the address, the step of executing the shift mode by the hit flag register, and writing and writing the data to the word using the address are performed. It is characterized by including a step of reading and a step of simultaneously executing the step of executing the shift mode of the hit flag register.

According to the eleventh aspect of the present invention, there are w (w is an arbitrary natural number) words arranged in a one-dimensional manner and provided with an original image field, a processed image field and a shifted image feed, and shift up and shift down. Q × r associative memories (q and r are arbitrary integers of 2 or more) having possible hit flag registers and upper shift input / output and lower shift input / output for putting the contents of the hit flag registers in and out. Of the q × r associative memories, the lower shift input / output of one of the associative memories adjacent in the horizontal direction and the associative memory adjacent in the horizontal direction. Each of the hit flag shift line that connects the shift input / output of the other associative memory and the w words of the associative memory have m columns and n rows (w,
An associative memory array having m × q PEs in the vertical direction and n × r PEs in the horizontal direction, which are sequentially allocated to PEs arranged in a zigzag pattern (m is an arbitrary natural number satisfying w = m × n). And a control unit for supplying a single control instruction stream to the associative memory array unit.

According to a twelfth aspect of the present invention, a step of arranging w (w is an arbitrary natural number) words in one dimension, and one original image field, one processed image field, and one horizontal shift image in each word are provided. Field and two vertically shifted image fields, q × r (q,
r is an arbitrary integer greater than or equal to 2), the content of the hit flag register which can be shifted up and down is put in and out of the associative memory using upper shift input / output and lower shift input / output. Out of the xr associative memories, the lower shift input / output of one of the associative memories that are laterally adjacent to each other and the other of the associative memories that are laterally adjacent to each other The step of connecting the upper shift input / output of the associative memory with a hit flag shift line, and each of the w words of the associative memory have m columns and n rows (w, m, n satisfy w = m × n). Providing an associative memory array unit having m × q PEs in the vertical direction and n × r PEs in the horizontal direction, which are sequentially allocated to the PEs arranged in a zigzag pattern (arbitrary natural number), Communicating The step of giving a single control instruction stream to the memory array section, and the data of the original image field of the PE in the horizontal direction or the data of the vertical shift image field are sequentially transferred to the horizontal shift image field, arithmetic processing is performed and stored in the processed image field. A transfer operation processing step for transferring, and an image shift up / down processing step for transferring the data of the original image field of PE in the vertical direction or the data for one of the vertical shift image fields to the other vertical shift image field, and the transfer operation processing step. Image shift up and down processing steps, P
And a step of repeating until all the transfer arithmetic processing from E is completed.

Here, in claim 12, the data of each element of the original image is converted into the corresponding P of the two-dimensional PE array device.
It may further be provided with a step of transferring to the original image field of E and a step of performing data transfer and arithmetic processing from any PE defined in the vertical and horizontal directions by the structuring element.

Here, in the twelfth aspect, a mask search for a specific bit of the original image field or the vertically shifted image field, m upshifts (m is m in the m column) or downshifts, and left and right shifts. Only when the data transfer processing step in which the parallel partial writing to the corresponding bits of the image field is repeated by the number of bits of the data and the data in the left / right shift image field is the data from the PE to be processed, the processed image field And an arithmetic processing step of performing arithmetic processing on the left and right shift image fields and storing the result of the arithmetic processing in the processed image field, and the data transfer processing step and the arithmetic processing step, all of the left and right transfer arithmetic processing. And steps to repeat until finished. It is possible.

Here, in claim 12, a mask search for a specific bit of the original image field or one of the vertical shift image fields, one shift up or shift down process, and the other vertical shift image field correspond. By using the internal word transfer step in which parallel partial writing to bits is repeated for the number of bits of data and the function of reading and writing data to and from the word using the address of the associative memory, the upper or lower word group of the odd or even associative memory group is Transferring all the bits of the original image field or one upper shift image field of a particular word to the upper or lower boundary word of the other upper or lower shift image field of the corresponding even or odd associative memory group. can do.

[0048]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) FIG. 1 is a diagram showing a basic configuration of a two-dimensional PE array device PEA1 which is an embodiment of the present invention.

The two-dimensional PE array device PEA1 is composed of a plurality of associative memories 11 arranged two-dimensionally and an associative memory hit flag shift line 16 connecting the two associative memories 11 to each other.

In the following, when the individual associative memories are referred to separately, the associative memory 11 is used instead of the associative memory 11.
_(1,1) etc. Similarly, when individually referring to individual words, the word 24 ₍₁₎ , the word 12 _(1,1) or the like is used instead of the word 24 or the word 12.

The two-dimensional PE array device PEA1 is
W words (where w is an arbitrary natural number) arranged in one dimension, a hit flag register that can be shifted up and down, an upper shift input / output and a lower shift input that put the contents of this hit flag register in and out. Of the q × r associative memories 11 (q and r are arbitrary integers of 2 or more) having outputs and the above q × r associative memories 11,
Lower shift input / output of one of the associative memories 11 adjacent to each other in the horizontal direction and the shift input / output of the other associative memory 11 of the associative memories 11 adjacent to each other in the horizontal direction. A hit flag shift line 16 connected to the output, w words of the associative memory 11 are arranged in a z-zag pattern in m columns and n rows, and each of the w words of the associative memory 11 has various values. Is a two-dimensional PE array device assigned to PEs that perform the logic and arithmetic processing of.

FIG. 2 shows the two-dimensional PE array device PEA.
FIG. 3 is a diagram showing an associative memory 11 _(1,1) which constitutes No. 1.

The associative memory 11 _(1,1) has a search / write data input 21, a mask register 22, an address input 23, a word 24, an address decoder 25, an upper shift input / output 26, a shift up, It is composed of a hit flag register 27 for transferring the contents of the word 24 by shifting down, a read data output 28, and a lower shift input / output 29. Also, all the numbers w of the words 24 in one associative memory 11 _(1,1) are
w = m × n, and w, m, and n are arbitrary natural numbers that satisfy the above formula. The word 24 in FIG. 2 is the same as the word 12 shown in FIG. That is, each of the words 24 _{(1) to} 24 _(w) is the word 12 _(1,1).
Corresponds to ~ 12 _{(m, n)} . In addition, another associative memory 11
_{Since the configurations of (2,1) to} 11 _{(q, r)} are similar to the above-described configurations of the associative memory 11 _(1,1) , the following description will be made by taking the associative memory 11 _(1,1) as a representative. To do.

The associative memory 11 _(1,1) has a data write function, a data read function, a mask search function, and a parallel partial write function.

The data writing function is the same as that of the associative memory 1.
1 _(1,1) is a function of writing data to an arbitrary word 24 by giving an address value to the address input 23 and giving write data to the search / write data input 21.

The data read function is the same as the associative memory 1
1 _(1,1) is a function of reading the data of an arbitrary word 24 and reading it from the data output 28 by giving an address value to the address input 23.

Further, the mask search function uses the search data given to the search / write data input 21 and the word 24.
Collate in parallel with the data stored in, and write the collation result to the hit flag register 27. In this case,
This is a function of giving a bit position to be masked to the mask register 22 to ignore collation of a part of the search data. Then, by setting data for masking other than a specific bit in the mask register 22 and supplying search data “1” to the search / write data input 21,
A function of transferring a specific bit in the word 24 to the hit flag register 27 can be realized.

The parallel partial write function is a function in which the data of the search / write data input 21 is written to a specific bit which is not masked for the word whose hit flag register 27 is "1".

The hit flag register 27 has a bidirectional shift mode of upshifting and downshifting, that is, switching between upshifting and downshifting by a selector (not shown), upper shift input / output 26, lower shift input / output 29. It has a function of serially reading and writing from outside the associative memory 11 _(1,1) via the.

Further, as shown in FIG.
In the array device PEA1, PEs arranged in X × Y are divided into blocks of q columns in the vertical direction and r rows in the horizontal direction, and one associative memory 11 _(1,1) is allocated to each of the divided blocks. It is a thing. Note that X is the number of PEs in the vertical direction, Y is the number of PEs in the horizontal direction, and X = mq, Y = nr.
Is an arbitrary integer of 2 or more, and q and r are arbitrary numbers of 2 or more.

Each assigned associative memory 11
_(1,1) is divided into w words 12 (X ÷ q) each, arranged in a zigzag pattern (X ÷ q) × (Y ÷ r), and sequentially allocated to the PE blocks. It consists of:

In this way, one associative memory 11
_(1,1) can mount m × n PE. Note that m is m =
It is a natural number that satisfies X ÷ q, and n is a natural number that satisfies n = Y ÷ r. Therefore, as a whole, the vertical direction X = m × q
It is possible to realize a two-dimensional PE array device PEA1 equipped with a number of PEs of Y = n × r in the horizontal direction.

Further, between the associative memories adjacent in the horizontal direction,
The associative memories are connected by the hit flag shift line 16. Specifically, the upper shift input / output 26 of one associative memory 11 and the lower shift input / output 29 of another associative memory 11 laterally adjacent to the associative memory 11 are
The associative memories are connected by the hit flag shift line 16. Specifically, the upper shift output 26 of one content addressable memory 11 _(1,1), the lower shifting-associative memory 11 laterally adjacent and its associative memory 11 _{(1,1) (1,2)} The output 29 is the associative memory hit flag shift line 16
Are joined by. Therefore, among the associative memories 11 that are adjacent to each other in the horizontal direction, the same associative memory 11 can handle the operations such as shift up and shift down in a unified manner.

FIG. 3 shows the above embodiment, on the right,
It is a figure which shows the allocation method of the word 24 of the associative memory 11 _(1,1) in the case of transferring data to 4 adjacent PEs of the lower left, and the upper.

As shown in FIG. 3, the PE 31 has a current state field C32, a next state field C + 33, and a right P
E state field R34 and lower PE state field D3
5, a left PE status field L36, and an upper PE status field U37.

The work field W38 includes a current state field C32, an adjacent PE (right PE state field R34
The lower PE status field D35, the left PE status field L36, and the upper PE status field U37) are used as temporary areas when various operations are performed.

FIG. 4 shows the associative memory 11 (1, 1) in the above embodiment when data is transferred to the eight adjacent PEs of right, lower right, lower, lower left, left, upper left, upper and upper right.
It is a figure which shows the allocation method of the word of.

As shown in FIG. 4, the PE 41 has a current state field C42, a next state field C + 43, a right PE state field R44, and a lower right PE state field RD4.
5, lower PE status field D46, lower left PE status field LD47, left PE status field L48, upper left PE
Status field LU49, upper PE status field U41
0, upper right PE status field RU411.

The work field W412 includes a current state field C42, an adjacent PE (right PE state field R4).
4, lower right PE status field RD45, lower PE status field D46, lower left PE status field LD47, left P
E status field L48, upper left PE status field LU
49, upper PE status field U410, upper right PE status field RU411) is used as a temporary area when various calculations are performed.

By the same method as shown in FIG. 3 and FIG.
Words of the associative memory 11 _(1,1) can be allocated when data is transferred to adjacent PEs or more.

FIG. 5 is a flowchart showing the overall processing procedure in the two-dimensional PE array device PEA1.

After the power is turned on, first, the current state field C3
Initial data is externally set to 2 or C42.

Next, all the adjacent state fields in the two-dimensional PE array device PEA1 are initialized to "0" by using the parallel partial write function of the associative memory 11 _(1,1) (5
1). In the case where all the adjacent state fields in the two-dimensional PE array device PEA1 are four adjacent, the right PE state field R34, the lower PE state field D35, and the left P state field R34.
E status field L36, upper PE status field U37
In the case of 8 adjacencies, the right PE status field R44, the lower right PE status field RD45, the lower PE status field D46, and the lower left PE status field L.
D47, left PE status field L48, upper left PE status field LU49, upper PE status field U410, and upper right PE status field RU411.

Next, data transfer to the adjacent PE is performed (54). This data transfer is divided into internal word transfer (transfer in associative memory: 52) and upper and lower boundary word transfer (transfer between associative memories: 53). The internal word transfer (52) is all transfers except the data transfer to the upper PE of the upper boundary word group 13 and the lower PE of the lower boundary word group 15, and the upper and lower boundary word transfers (53). Is data transfer to the upper PE of the upper boundary word group 13 and word transfer to the lower PE of the lower boundary word group 15. When the upper PE of the upper boundary word group 13 is 8 adjacent, it includes the upper right PE and the upper left PE, and the lower boundary word group 15
The lower PE includes a lower right PE and a lower left PE in the case of 8 adjacencies.

Next, the internal word transfer (52) in the above embodiment will be described.

FIG. 6 is a flowchart showing a 4-adjacent internal word transfer procedure in the above embodiment.

The 4-adjacent internal word transfer (52) is composed of two stages: a bit transfer to the lower and right PEs (61) and a bit transfer to the upper and left PEs (62).

Below, in the bit transfer (61) to the right PE,
First, the mask register 22 is set with data for masking a bit other than the specific bit of C32, and a search with "1" is performed to transfer the content of the specific bit of C32 to the hit flag register 27. Next, the hit flag register 27 is shifted down by one lower, and the hit flag register 27 becomes a word of "1" by the corresponding bit of U37.
"1" is written in parallel. By the above procedure,
Bit transfer to the lower PE can be performed. Next, the hit flag register 27 is shifted down by m-1 times, and L
Depending on the corresponding bit of 36, the hit flag register 27
The partial writing of "1" is performed in the word of "1".
Bit transfer to the right PE is performed by the above procedure.

Above, in the bit transfer (62) to the left PE,
First, the contents of the specific bit of C32 are transferred to the hit flag register 27 by searching the mask register 22 for the data other than the specific bit of C32 by setting "1". Next, the hit flag register 27 is shifted up once, and "1" is added to the word in which the hit flag register 27 is "1" by the corresponding bit of D35.
Write in parallel part. By this procedure, bit transfer to the upper PE is performed. Then, the hit flag register 27 is shifted up by m-1 times, and "1" is written in parallel to the word "1" by the hit flag register 27 by the corresponding bit of R34. This allows the left PE
Bit transfer to.

Then, the above procedure is repeated by the number of bits of C32.
Repeatedly, the 4-adjacent internal word transfer is completed.

FIG. 7 is a flowchart showing the 8-adjacent internal word transfer procedure in the above embodiment.

As shown in FIG. 7, the 8-adjacent internal word transfer is a bit transfer to the lower, upper right, right and lower right PEs (71).
And bit transfer to the upper, lower left, left, and upper right PE (72).

In the bit transfer (71) to the lower, upper right, right, and lower right PEs, first, data for masking other than the specific bits of C42 is set in the mask register 22, and a search is performed with "1". The contents of the specific bit of C42 are transferred to the hit flag register 27. Then, the hit flag register 27 is shifted down once, and "1" is written in parallel to the word of which the hit flag register 27 is "1" by the corresponding bit of U410. By this procedure, bit transfer to the lower PE is performed. Next, the hit flag register 27 is shifted down by m−2 times, and “1” is written in parallel to the word of which the hit flag register 27 is “1” by the corresponding bit of the LD 47. By this procedure, bit transfer to the upper right PE is performed.

Next, the hit flag register 27 is shifted down once, and "1" is written in parallel to the word of which the hit flag register 27 is "1" by the corresponding bit of L48. Bit transfer to the right PE is performed by this procedure. Next, the hit flag register 27 is shifted down once, and "1" is written in parallel to the word of which the hit flag register 27 is "1" by the corresponding bit of the LU 49. In this way, the bit transfer to the lower right PE is performed.

In the bit transfer to the upper, lower left, left, upper left PE (72), first, data for masking other than the specific bits of C42 is set in the mask register 22, and a search is performed with "1" to hit. The contents of the specific bit of C42 are transferred to the flag register 27, and the hit flag register 27 is shifted up once. Next, with the corresponding bit of D46, the hit flag register 27 writes "1" in parallel to the word of "1". By this procedure, bit transfer to the upper PE is performed. Next, the hit flag register 27 is shifted up by m-2 times, and RU4
According to 11 corresponding bits, the hit flag register 27
The partial writing of "1" is performed in the word of "1".
By this procedure, bit transfer to the lower left PE is performed. Next, the hit flag register 27 is shifted up once and the hit flag register 2 is changed depending on the correspondence of R44.
7 parallel-writes "1" to the word "1".
By the above procedure, bit transfer to the left PE is performed.

Next, the hit flag register 27 is shifted up once, and "1" is written in parallel to the word of which the hit flag register 27 is "1" by the corresponding bit of the RD 45. By the above procedure, bit transfer to the upper left PE is performed. Then, the above procedure is repeated for the number of bits of C42. By these procedures, all 8-adjacent internal word transfers are performed. The 24-adjacent internal word transfer or the number of adjacent internal word transfers of more than 24 is performed in the same procedure as the procedure of the 4-adjacent or 8-adjacent internal word transfer.

The upper / lower boundary word transfer (53) is sequentially performed by using the data writing / reading function for the word using the address of the associative memory 11 _(1,1) . Further, after all the internal word transfers (52) are completed, the above-mentioned upper and lower boundary word transfers (53) are executed. During the internal word transfer (52), for example, upper boundary word group 1
Incompatible data is written to U37 of 3
At the time of transfer of the upper and lower boundary words (53) in the flowchart shown in FIG. 5, there is no problem because the uncorresponding data is overwritten.

Next, the current state field C32 or 42
The next state is calculated using the adjacent state and the adjacent state (55), and the calculated next state is set to the next state field C + 33 or 43.
Put in. In the associative memory 11 _(1,1) , this process can be executed simultaneously for all words. Next, the role of the next state field C + 32 or 42 and the role of the current state field C33 or 43 are exchanged, and the process returns to the initialization stage (51). The above procedure is repeated any number of times, and finally the data of the next state field C + 33 or 43 is output to the outside.

In the above embodiment, the associative memory 11
_{Since (1,1)} is configured based on a memory technology having a very high degree of integration, one PE and a data transfer path can be realized with a small amount of hardware. Therefore, it is possible to realize the two-dimensional PE array device PEA1 with a small amount of hardware. Also, X × Y PE
When implementing the two-dimensional PE array device PEA1 configured by
The data transfer time between PEs in the horizontal direction is shortened, and as compared with the conventional two-dimensional PE array device PEA12 that allocates PEs in Ys in a zigzag pattern as shown in FIG.
The data transfer time between E becomes short.

In the above embodiment, it is necessary to transfer words between the associative memories 11 in the vertical direction, but since the associative memory 11 capable of directly reading and writing data in the words is used, the transfer efficiency is improved. To be done. Also from this point, the two-dimensional PE array apparatus PEA1 can suppress the entire data transfer time. Further, in the case of the two-dimensional PE array device PEA1, since the number of words to be assigned in zigzag and the vertical and horizontal numbers q and r of the associative memory 11 can be arbitrarily selected, PEs can be configured by an arbitrary number and a two-dimensional PE array device Can be said to be highly expandable.

(Second Embodiment) FIG. 8 is a flow chart showing an upper / lower boundary word transfer procedure 53 in the second embodiment of the present invention.

FIG. 9 is a diagram showing an example of transferring one word of the lower word group 15 of the odd-numbered associative memory group 91 at four adjacent locations to the even-numbered associative memory group 92 in the second embodiment. The associative memories forming the odd-numbered associative memory group 91 and the even-numbered associative memory group 92 are the associative memory 11
_{It is the same as (1,1)} .

FIG. 10 shows that in the second embodiment, 4
Lower word group 15 of even associative memory group 92 adjacent to each other
FIG. 3 is a diagram showing an example in which one word of is transferred to an odd-numbered associative memory group 91.

FIG. 11 shows that in the second embodiment, 4
Upper word group 13 of odd-numbered associative memory group 91 adjacent to each other
FIG. 9 is a diagram showing an example in which one word of is transferred to an even associative memory group 92.

FIG. 12 shows that in the second embodiment, 4
Upper word group 13 of even associative memory group 92 adjacent to each other
FIG. 3 is a diagram showing an example in which one word of is transferred to an odd-numbered associative memory group 91.

As shown in FIG. 8, in the upper / lower boundary word transfer procedure (53), first, all bits of the current state field C32 or 42 of a specific word belonging to the lower word group 15 of the odd memory group 91 are The data is transferred to U37 (LU49, U410, RU411 in the case of 8 adjacencies) of the word of the upper word group 13 of the corresponding even memory group 92.
In this case, as shown in FIG. 9, all the data transfers shown in the data transfer direction 93 are simultaneously performed. This is repeated in order for the number of lower word groups 15.

Next, the lower word group 1 of the even memory group 92
All the bits of the current state field C32 or 42 of the specific word belonging to 5 are assigned to U37 of the word of the upper word group 13 of the corresponding odd-numbered memory group 91 (LU4 in case of 8 adjacencies LU4
9, U410, RU411). In this case, as shown in FIG. 10, all the data transfers shown in the data transfer direction 101 are simultaneously performed. This operation is sequentially repeated for the number of lower word groups 15.

Next, the upper word group 1 of the odd memory group 91
All bits of the current state field C32 or 42 of the specific word belonging to 3 are stored in D35 of the word of the lower word group 15 of the corresponding even memory group 92 (LD4 in the case of 8 adjacencies).
7, D46, RD45). In this case, FIG.
As shown in, all the data transfers shown in the data transfer direction 111 are simultaneously performed. This is repeated in order for the number of upper word groups 13.

Next, the upper word group 1 of the even memory group 92
All the bits of the current state field C32 or 42 of the specific word belonging to 3 are set to D35 of the word of the lower word group 15 of the corresponding odd-numbered memory group 91 (LD4 in the case of 8 adjacencies).
7, D46, RD45). In this case, FIG.
As shown in, all the data transfers shown in the data transfer direction 121 are simultaneously performed. This is repeated in order for the number of upper word groups 13.

By these procedures, all upper and lower boundary word transfers (53) are performed. In the second embodiment, data transfer is performed in parallel by the number of arrows shown in FIGS. 9, 10, 11 and 12, so that the two-dimensional PE array device PEA1 shown in FIG. The transfer time is even shorter than the data transfer.

That is, in the second embodiment, w words (w is an arbitrary natural number) arranged in one dimension, a hit flag register capable of shifting up and shifting down,
Q × r having upper shift input / output and lower shift input / output for putting the contents of the hit flag register in and out.
In the associative memory of (where q and r are arbitrary integers of 2 or more), among the associative memories arranged in q columns in the vertical direction,
Simultaneous data transfer from the associative memory group of odd columns to the associative memory group of even columns, or from the associative memory group of even columns to the associative memory group of odd columns, and all the associative memories arranged in the horizontal direction r rows On the other hand, the data transfer method includes the step of simultaneously performing the data transfer.

By adopting such a data transfer method, different associative memories 11 can be operated independently of each other. Utilizing this property, when data is transferred between different associative memories 11, data transfer from the associative memory group 91 of odd columns to the associative memory group 92 of even columns, and associative memory group 92 of even columns may be performed. Data transfer to the associative memory group 91 or data transfer of all the associative memories arranged in the horizontal direction can be performed at the same time, whereby the data transfer time can be shortened.

(Embodiment 3) FIG. 13 shows a method of allocating words 24 in the associative memory 11 to PEs in the two-dimensional PE array apparatus PEA3 according to Embodiment 3 of the present invention (in the case of 4 adjacencies). It is a figure.

FIG. 20 shows a two-dimensional PE when two PEs are allocated to one word 24 of the associative memory 11.
It is a figure which shows the structural example of an array device.

As shown in FIG. 13, the current state field C
132, next state field C + 133, right PE state field R134, lower PE state field D135, left P
E state field L136, upper PE state field U1
The PE 131 constituted by 37 is allocated to J (J is an arbitrary natural number of 2 or more) one word 24 of one associative memory as long as the number of bits allows.

In this case, assuming that J is 2, as shown in FIG. 20, two PEs of the upper PE a2 and the lower PE a3 are allocated to one word a1, and the vertical direction X = m.
It is possible to realize a two-dimensional PE array device having × 2 × q PEs and Y = n × r PEs in the horizontal direction. However, in this case, the lower PE status field D1 of the upper PE a2
Since the data of No. 35 and the data of the upper PE status field U137 of the lower PE a3 exist on the same word, each status field is not provided.

In the case of 8-adjacent and 24-adjacent as well, words are allocated in the associative memory in the same manner as described above. As a result, a larger number of PEs can be realized with the same number of associative memories, so that a two-dimensional PE array device with a small amount of hardware can be realized.

Next, the overall processing procedure for performing various processes using the two-dimensional PE array device PEA3 will be described with reference to FIG.

The above processing procedure is the same as the procedure shown in FIG. 6, except for the internal word transfer (52) shown in FIG. 6 and the upper and lower boundary word transfers (53).

The internal word transfer (52) is performed by the upper PE a.
The internal word transfer b1 of 2 and the internal word transfer B2 of the lower PE a3 are performed separately.

In the internal word transfer b1 of the upper PE a2, the mask register 22 is set with data for masking a bit other than the specific bit of C32, and a search is performed with "1" to set the contents of the specific bit of C32 in the hit flag register 27. To transfer. Next, the hit flag register 27 is shifted down m times, and "1" is written in parallel to the word of which the hit flag register 27 is "1" by the corresponding bit of L36. Bit transfer to the right PE can be performed by the above procedure.

Next, the mask flag 22 is set again with data for masking other than the specific bit of C32, and a search is performed with "1", whereby the hit flag register 27
The contents of the specific bit of C32 are transferred to and the hit flag register 27 is shifted up once. Then, at the corresponding bit of D35, the hit flag register 27 partially writes "1" in the word "1" in parallel. By the above procedure, bit transfer to the PE a2 can be performed.

Next, the hit flag register 27 is set to m-1.
The number of shifts is increased, and the hit flag register 27 writes "1" in parallel to the word of "1" by the corresponding bit of R34. By this procedure, bit transfer to the left PE can be performed. The above procedure is repeated for the number of bits of C32. By these procedures, the 4-adjacent internal word transfer b1 of the PE a1 can be all performed.

In the internal word transfer b2 of the lower PE a3, the mask register 22 is set with data for masking a bit other than the specific bit of C32, and a search is performed with "1". The contents are transferred and the hit flag register 27 is downshifted once. Then, with the corresponding bit of U37, the hit flag register 27 writes "1" in parallel to the word of "1". Bits can be transferred to the lower PE by the above procedure.

Next, the hit flag register 27 is set to m-1.
Downshifting is performed twice, and the hit flag register 27 partially writes "1" in parallel to the word of "1" at the corresponding bit of L36. Bit transfer to the right PE can be performed by the above procedure.

Next, the mask flag 22 is set again with data for masking other than the specific bit of C32, and a search is performed with "1".
The contents of the specific bit of C32 are transferred to and the hit flag register 27 is shifted up m times. Then, with the corresponding bit of R34, the hit flag register 27 writes "1" in parallel to the word of "1". Bit transfer to the left PE can be performed by the above procedure. These acquisition orders are repeated for the number of bits of C32. By the above procedure, the 4-adjacent internal word transfer b2 of the lower PE a3 can be all performed.

Next, the upper / lower boundary word transfer procedure (5
3) will be described.

The upper / lower boundary word transfer 53 transfers a specific one word of the lower word group 15 of the odd associative memory group 91 to the even associative memory group 92 in the same manner as the procedure shown in FIG. A specific 1 word of the lower word group 15 of the group 92 is transferred to the odd associative memory group 91, a specific 1 word of the upper word group 13 of the odd associative memory group 91 is transferred to the even associative memory group 92, and an even number A specific one word of the upper word group 13 of the associative memory group 92 is transferred to the odd associative memory group 91, and each of them is repeated by the number of words in the upper and lower word groups to perform the transfer.

However, for example, when two PEs are assigned to one word 24 of the associative memory 11 shown in FIG. 20, when the word transfer from the upper word group 13 to the lower word group 15 is performed, the lower PE Only the word a3 is transferred, while the lower word group 15 to the upper word group 1 are transferred.
When word transfer to 3 is performed, only the word of the upper PE a2 is transferred. By the above procedure, all upper and lower boundary word transfers 53 can be performed.

FIG. 13 shows a two-dimensional PE array device PEA3.
FIG. 9 is a diagram showing a method of allocating words 24 of the associative memory 11 to PEs in the case of (4 adjacent).

As shown in FIG. 13, the current state field C
132, next state field C + 133, right PE state field R134, lower PE state field D135, left P
E state field L136, upper PE state field U1
The PE 131 constituted by 37 is allocated to J words (J is an arbitrary natural number of 2 or more) to one word 24 of the associative memory as long as the number of bits allows. Words in the associative memory can be similarly allocated also in the case of 8-adjacent and 24-adjacent. As a result, more PEs can be realized with the same number of associative memories, so that it is possible to realize a two-dimensional PE array device with a small amount of hardware.

Here, the (internal word) transfer method when a plurality of PEs are assigned to one word in the associative memory is as described above.

In the two-dimensional PE array device PEA3, a plurality of PEs are allocated to one word 24 of the associative memory,
One of these PEs 131 is a two-dimensional PE array device in which the current state field of its own PE, the next state field of its own PE, and the state fields of adjacent PEs are held. By allocating a plurality of PEs to one word 24 of the associative memory as described above, more PEs can be realized with the same number of associative memories, so that it is possible to realize a two-dimensional PE array device with a small amount of hardware. It is possible.

(Embodiment 4) Next, as an associative memory 11, in addition to the function of the two-dimensional PE array device PEA1,
A two-dimensional P is used by using an associative memory having a mode in which data writing / reading to / from a word 24 using an address and a shift-up / shift-down operation can be simultaneously performed.
The associative memory according to the fourth embodiment which constitutes the E array device will be described.

The associative memory according to the fourth embodiment has a function of writing / reading data to / from a word 24 using an address,
In the associative memory that executes the shift mode of the hit flag register, the associative memory has a mode in which data writing / reading to / from a word using the address and a shift mode of the hit flag register are simultaneously performed.

FIG. 14 shows four adjacent PEs on the right, bottom, left, and top.
FIG. 3 is a diagram showing a word allocation method of an associative memory for realizing a two-dimensional PE array device having a data transfer function for.

As shown in FIG. 14, one PE 141
Indicates the current state field C142 and the next state field C +
143, a right PE status field R144, a lower PE status field D145, a left PE status field L146, an upper PE status field U147, and a word type identification field I148.

PE 141 is allocated to one word 24 of the associative memory 11 by J (J is an arbitrary natural number of 2 or more) as long as the number of bits allows. Work field W149
Is used as a temporary area when various operations are performed using the data of the current state field C142 and the adjacent PE.

FIG. 15 shows a word 24 of the associative memory for realizing a two-dimensional PE array device having a data transfer function for eight adjacent PEs of right, lower right, lower, lower left, left, upper left, upper and upper right. It is the figure which showed the allocation method.

As shown in FIG. 15, one PE 151 is used.
Indicates a current state field C152 and a next state field C +
153, right PE status field R154, lower right PE status field RD155, lower PE status field D15
6, lower left PE status field LD157, left PE status field L158, upper left PE status field LU15
9, upper PE status field U1510, upper right PE status field RU1511, word type identification field I1
512. PE 151 is allocated to one word 24 of the associative memory 11 by J (J is an arbitrary natural number) as long as the number of bits allows. Work field W
Reference numeral 1513 is used as a temporary area when various operations are performed using the data of the current state field C152 and the adjacent PE.

FIG. 16 shows the word type identification field I1.
It is a figure which shows 48 or 1512.

The word type identification field I 148 or 1512 is composed of 3 bits of an upper boundary word identifier 161, an internal state word identifier 162, and a lower boundary word identifier 163. At power-on, if a word belongs to upper boundary word group 13, upper boundary word identifier 1
When only 61 is “1” and the rest is set to “0”, and the word belongs to the internal word group 14, only the internal state word identifier 162 is set to “1” and the rest is set to “0”, and the word is lower boundary. When belonging to the word group 15, only the lower boundary word identifier 163 is set to "1" and the rest are set to "0".

FIG. 17 is a diagram showing an overall processing procedure for performing various kinds of processing using the two-dimensional PE array device having the above-mentioned configuration.

Except for the data transfer 173 to the adjacent PE, the method is the same as that shown in FIG.

FIG. 18 shows the data transfer 173 to the adjacent PE.
It is a figure which shows the 4 adjacent internal word transfer procedure regarding the internal word transfer 171 among these.

FIG. 19 shows the data transfer 173 to the adjacent PE.
8 is a diagram showing an 8-adjacent internal word transfer procedure regarding an internal word transfer 171 in FIG.

As shown in FIG. 18, the 4-adjacent internal word transfer 171 includes the bit transfer 181 to the lower PE and the upper bit to the right PE.
It is carried out in two steps including the bit transfer 182 to the left PE. under,
In the bit transfer 181 to the right PE, first, data for masking other than the specific bit of C142 is set in the mask register 22 and a search is performed with "1", so that the content of the specific bit of C142 is stored in the hit flag register 27. To transfer.

Next, the hit flag register 27 is downshifted once, and the corresponding bit of U147 and which does not belong to the upper boundary word group 13 and the hit flag register 27 writes "1" in the partial parallel writing to the word of "1". To do.

Whether or not it belongs to the upper boundary word group 13 is searched by searching the word type identification field I148. Bit transfer to the lower PE is performed by the above procedure.
Next, the hit flag register 27 is shifted down by m-1 times, and "1" is written in parallel to the word of "1" by the hit flag register 27 by the corresponding bit of L146. By the above procedure, bit transfer to the right PE is performed.

In the bit transfer 182 to the left PE, first, data for masking other than the specific bits of C142 is set in the mask register 22 and a search is performed with "1" to set the C142 in the hit flag register 27. Transfer the contents of a specific bit. Next, the hit flag register 27 is shifted up once, and "1" is written in parallel to the word corresponding to D145 and not belonging to the lower boundary word group 15 and the hit flag register 27 is "1". Whether the word belongs to the lower boundary word group 15 is searched by searching the word type identification field I148. By the above procedure, the bit transfer to the upper PE is performed.

Next, the hit flag register 27 is set to m-1.
After shifting up, the hit flag register 27 partially writes "1" in parallel to the word "1" with the corresponding bit of R144. By the above procedure, bit transfer to the left PE is performed.

When the above procedure is repeated for the number of bits of C142 and a plurality of PEs are assigned to one word,
Repeat the above procedure for that number of times. By the above procedure,
All four adjacent internal word transfers are performed.

As shown in FIG. 19, the 8-adjacent internal word transfer is a bit transfer 191 to the lower, upper right, right and lower right PEs.
And bit transfer 192 to upper, lower left, left, upper left PE.

Bit transfer to bottom, top right, right, bottom right PE 1
In 91, first, the mask register 22 is set with data for masking other than a specific bit of C152, and a search is performed with "1", so that the hit flag register 27 is C-filled.
The contents of the specific bit of 152 are transferred, and the hit flag register 27 is downshifted once. Next, except for the upper boundary word group 13 corresponding to U1510, the hit flag register 27 partially writes "1" in parallel to the word of "1". Whether or not it belongs to the upper boundary word group 13 is searched by searching the word type identification field I1512. By the above procedure, the bit transfer to the lower PE is performed.

Next, the hit flag register 27 is set to m-2.
Downshifting is performed twice, and the hit flag register 27 writes "1" in parallel to the word of "1" by the corresponding bit of the LD 157. Bit transfer to the upper right PE is performed by the above procedure.

Next, the hit flag register 27 is shifted down once, and the hit flag register 27 writes "1" in parallel to the word "1" at the corresponding bit of L158. By the above procedure, bit transfer to the right PE is performed.

Next, the hit flag register 27 is shifted down once, and the corresponding bit of the LU 159 does not belong to the upper boundary word group 13, and the hit flag register 27 is "1" in the word "1" in parallel part. To write. Whether or not it belongs to the upper boundary word group 13 is searched by searching the word type identification field I1512. By the above procedure, the bit transfer to the lower right PE is performed.

Bit transfer to upper, lower left, left, upper left PE 1
In 92, first, data for masking other than the specific bit of C152 is set in the mask register 22, and a search is performed with "1", so that C is set in the hit flag register 27.
Transfer the contents of 42 specific bits.

Next, the hit flag register 27 is shifted up once, the corresponding bit of D156 and not belonging to the lower boundary word group 15, and the hit flag register 27 is "1" in the word "1" in parallel part. To write. Whether or not it belongs to the upper boundary word group 13 is searched by searching the word type identification field I1512. By the above procedure, the bit transfer to the upper PE is performed.

Next, the hit flag register 27 is set to m-2.
The number of shifts is increased, and the hit flag register 27 writes "1" in parallel to the word of "1" by the corresponding bit of the RU 1511. By the above procedure, bit transfer to the lower left PE is performed.

Next, the hit flag register 27 is shifted up once, and "1" is written in parallel to the word of which the hit flag register 27 is "1" by the corresponding bit of R154. Bit transfer to the left PE is performed by the above procedure.

Next, the hit flag register 27 is shifted up once, and the corresponding bit of the RD 155 does not belong to the lower boundary word group 15 and the hit flag register 27 is "1". To write. Whether it belongs to the boundary word group 13 is searched by searching the word type identification field I1512. By the above procedure, bit transfer to the upper left PE is performed.

The above procedure is repeated for the number of bits of C152, and when a plurality of PEs are assigned to one word, the above procedure is repeated for that number of times. Through the above procedure, all 8-adjacent internal word transfers are performed.

In the case of 24-adjacent internal word transfer or more, the same procedure as the above-mentioned 4-adjacent or 8-adjacent internal word transfer is performed.

The upper and lower boundary word transfer 172 procedure is as follows:
The method is the same as the method described in each of the above embodiments.

Next, the procedure of the internal word transfer 171 and the upper / lower boundary word transfer 172 will be described.

In the internal word transfer procedure 171, the upper and lower boundary word transfers 172 are similarly performed during the shift down and shift up operations.
Hit flag register shift mode (used for internal word transfer 171) and data writing / reading to / from a word using an address (upper / lower boundary word transfer 172)
As described above, the internal word transfer 171 and the upper and lower boundary word transfers 172 can be performed at the same time by using the associative memory having a mode capable of simultaneously executing (1.

Further, as shown in the internal word transfer 171, the internal word transfer 171 is prevented from being written with uncorresponding data, for example, in U147 or the like of the upper boundary word group 13. By performing the word transfer 171 and the upper / lower boundary word transfer 172 at the same time, a problem such as overwriting with correct data does not occur.

Further, since the internal word transfer 171 and the upper / lower boundary word transfer 172 can be performed at the same time, the internal word transfer 171 (shown in the embodiment of claim 1) and the upper / lower boundary word transfer 172 are performed. Compared with the sequential method, the short transfer time becomes short.

That is, since the associative memory having a mode in which the data writing / reading to / from the word using the address and the shift mode of the hit flag register can be performed at the same time is used, the data transfer shown in FIG. 17 can be performed 171 and 172. Can be performed simultaneously.

As described above, the data transfer time between PEs in the horizontal method described above and the vertical direction described above are obtained by simultaneously operating the data writing / reading in the word using the address and the shift mode of the hit flag register. It is possible to simultaneously transfer the words between the associative memories of (1) and (2), and it is possible to suppress the data transfer time. In this case, the shift mode can be applied to both bidirectional and unidirectional cases.

(Fifth Embodiment) FIG. 22 shows a second embodiment for executing a morphology operation process according to another embodiment of the present invention.
It is a figure which shows the basic composition of three-dimensional PE array apparatus MS1.

The two-dimensional PE array device MS1 is composed of an associative memory array section 17 and a control section 18. The associative memory array unit 17 is composed of q × r associative memories 11 that are two-dimensionally arranged (q and r are arbitrary integers of 2 or more).

The associative memory 11 constituting the two-dimensional PE array device MS1 is basically the associative memory 1 shown in FIG.
1 _(1,1) , which is w (where w is any natural number) word 24, address decoder 25, shift up,
It is provided with a hit flag register 27 capable of shifting down, an upper shift input / output 26 for putting the contents of the hit flag register 27 in and out, a lower shift input / output 29 and the like. Two-dimensional PE array device MS1
24 in the associative memory 11 used in
Is a one-dimensionally arranged word having an original image field, a processed image field and a shifted image field.

Further, by using the mask search function and the parallel partial write function described with reference to FIG. 2, all words 24 can be subjected to addition / subtraction, comparison operation, and logical sum operation necessary for morphological operation processing in parallel. It is possible to execute arbitrary logical and arithmetic operations including. Regarding this concrete procedure, "Ogura, Naganuma," Hardware algorithm of local expression neural network on associative processor and its evaluation ", IEICE Technical Report CPSY81
-44, 1991 "and the like.

Focusing on one associative memory 11, it is connected to the lower shift input / output of the associative memory adjacent in one of its lateral directions by the hit flag shift line 16, and the shift input of the associative memory adjacent to the other in the lateral direction. The output and the hit flag shift line 16 are connected. By doing so, the associative memories that are adjacent to each other in the lateral direction can perform operations such as shift up and shift down in a unified manner as the same associative memory.

The w words 24 in one associative memory 11 are respectively m columns and n rows (w, m, n is w =
It is sequentially assigned to PEs that perform various logical and arithmetic operations arranged in a zigzag pattern (arbitrary natural number satisfying m × n). A single associative memory 11 can realize an m × n two-dimensional PE array, and the entire associative memory array unit 17 is a two-dimensional PE having m × q PEs in the vertical direction and n × r PEs in the horizontal direction. realizable. In the associative memory array unit 17, m × q is the vertical pixel number of the original image, and n × r is the horizontal pixel number of the image. Therefore, m, q, n, and r are designated to desired values. As a result, the same number of PEs as the number of pixels of the original image can be realized.

The control unit 18 generates a single control instruction stream in order to cause the associative memory array unit 17 to execute the morphological operation processing, and is a microprocessor or FPGA (field program program).
It is composed of a reconfigurable circuit such as an Able Gate Array).

FIG. 23 is a diagram showing in detail the field configuration of each word 24 in the associative memory 11 used in the two-dimensional PE array device MS1.

Each word 24 includes an original image field C331 for storing each pixel data of the original image, a processed image field C + 332 for storing each pixel data after the morphological operation processing, and shift up or shift down data of the original image. Stored shift image field UD ₁ 33
3 and the shift image field UD ₂ 334 and the left and right P
Shift image field RL for storing original image data of E
And 335. Work field W
Reference numeral 336 is used as a temporary area when various calculations are performed using the data of the original image field C331 or the shift image field UD ₁ 333, UD ₂ 334, RL 335.

Next, a single control command operation generated in the control unit 18 for performing the morphological operation processing will be described in detail. First, the morphological operation will be outlined.

Morphological operations include dilation and erosion.
n), closing, and opening.

FIG. 24 is a diagram defining the structural elements of the morphology.

The "dilation" is a process performed on each pixel of the original image by a calculation using only the pixel data of itself and its neighbors. As shown in FIG. 24, the processing result is (-
Structural elements 3 distributed in (X2, -Y2) to (X1, Y1)
According to the definition of 41 (specifically, when the structuring element is binary, it is “1”, and when it is multivalued, it means “there is data”). It is a result of performing arithmetic processing on the original image. For example,
Structural element 341 is (0,0), (1,1), (1,-
1), (-1, 1), and (-1, -1) are defined, the dilation is the result of arithmetic processing on the data of itself and the four adjacent original images in the upper, lower, left, and right directions. Becomes Here, X1, X2, Y1, and Y2 are arbitrary integers of 0 or more.

The arithmetic processing is performed when the original image is binary and the structuring element 341 is binary (setprocessin).
g), the logical sum operation is executed (in the case of the above example, if there is at least one “1” in the data of itself and the four adjacent original images in the upper, lower, left, and right directions, “1” is output), and the original If the image is multi-valued and the structuring element 341 is binary (functio)
n and set processing), the calculation for the maximum value is executed (in the above example, the calculation for the maximum value of the data between itself and the four adjacent original images on the top, bottom, left, and right is executed), and the original image is multivalued. Yes, if the structuring element 341 is multi-valued (function processin)
g), the value of the structuring element 341 is added, and then the maximum value operation is executed.

"Erosion" can be processed in the same manner as the above dilation. However, when the original image is binary and the structuring element 341 is binary, the logical product operation (in the above example, all of the data of oneself and the four adjacent original images in the upper, lower, left and right directions) Is "1", "1" is output), and when the original image is multivalued and the structuring element 341 is binary, the calculation for the minimum value is executed (in the above example, If the original image is multi-valued and the structuring element 341 is multi-valued, the value of the structuring element 341 is subtracted. Perform the minimum value calculation above.

“Closing” is the result of performing erosion after performing the above dilation, and “opening” is the result of performing dilation after performing erosion.

FIG. 25 is a flow chart showing the overall output procedure in the morphology calculation processing.

First, the two-dimensional image data of the original image are
PE (= word 2) corresponding to the associative memory array unit 17
It is transferred to the original image field C331 in 4). Also, the image processing field C + 332 is initialized.

Next, step 35 of the morphological operation.
3 (1), the transfer calculation process 351 and the image shift process 352 are executed in parallel. In the transfer calculation processing 351,
According to the definition of (-X2,0)-(X1,0) of the structuring element, the original image field C3 of itself and the PEs 12 on the left and right thereof
The data of 31 is transferred to the PE 12 of its own, and calculation is performed, and the calculation result is stored in the processed image field C + 332. As described above, for example, in dilation, when the original image has a binary value and the structuring element 341 has a binary value, the logical sum operation is performed. Image shift processing 3
52 transfers the original image field C331 of the upper PE12 to shift image field UD ₁ 333. As a result, data obtained by shifting down the data of the original image field C331 by one pixel is stored in the image field UD ₁ 333.

Next, step 35 of the morphological operation.
3 (2), the transfer calculation process 351 and the image shift process 352 are executed in parallel. In the transfer calculation processing 351,
Of the structural element (-X2,1) - as defined by (x1,1), the data of the own and the shift image field UD ₁ 333 of PE12 of the left and right, then transferred to their PE12,
Calculation is performed, and the calculation result is processed image field C + 3.
It is stored in 32. The image shift processing 352 is performed on the upper PE 12.
The shift image fields UD ₁ 333, is transferred to the shift image field UD ₂ 334.

The same processing as above is performed in step 353.
Repeat from (3) to step 353 (Y1). In this case, the image shift processing 352 alternately shifts and processes the shift image field UD ₁ 333 and the shift image field UD ₂ 334.

Next, step 35 of the morphological operation.
3 (Y1 + 1), the transfer calculation process 351 and the image shift process 352 are executed in parallel. Transfer calculation processing 351
Then, according to the definition of (-X2, Y1)-(X1, Y1) of the structuring element, the data of the self and the shift image field UD ₁ 333 (or the shift image field UD ₂ 334) of the PEs 12 on the left and right of the self are changed to the data of the own. Transferred to PE12, calculated, and the calculation result is processed image field C + 3
It is stored in 32. In the image shift processing 352, the lower PE1
2 of the original image field C331 to the shift image field UD ₁ 333 (or the shift image field UD ₂ 33
Transfer to 4). This causes the image field UD ₁
(Or, the shift image field UD ₂ 334) stores data obtained by shifting up the data of the original image field C331 by one pixel.

Next, step 35 of the morphological operation.
3 (Y1 + 2), the transfer calculation process 351 and the image shift process 352 are executed in parallel. Transfer calculation processing 351
, The structural element (-X2, -1)-(X1,-
According to the definition of 1), the data of itself and the shift image field UD ₁ 333 (or the shift image field UD ₂ 334) of the PEs 12 on the left and right of the PE 12 are transferred to the PE 12 of its own, and the operation result is processed. C
Store in +332. The image shift processing 352 is performed by the lower PE.
12 shift fields UD ₁ 333 (or shift image field UD ₂ 334) are replaced by shift image field UD ₂ 334 (or shift image field UD ₁ 33).
Transfer to 3).

A process similar to the above is performed in step (Y1 +
Repeat from 3) to step (Y1 + Y2). In this case, in the image shift processing 352, the shift image field UD ₁ 333 and the shift image field UD ₂ 334 are alternately replaced and processed.

Finally, step 3 of the morphological operation
The transfer calculation process 351 is executed as 53 (Y1 + Y2 + 1). In the transfer operation processing 351, the structure element (-X
2, -Y2)-(X1, -Y2) according to the definition of the shift image field UD ₁₃
The data of 33 (or the shift image field UD ₂ 334) is transferred to the PE 12 of its own, is operated, and the operation result is stored in the processed image field C + 332.

FIG. 26 shows the processing step 35 shown in FIG.
3 is a flowchart showing the transfer calculation process 351 in detail by taking 3 (1) as an example.

The transfer calculation process 351 is divided into a transfer calculation process 61 for the self PE 12, a transfer calculation process 362 for the left PE 12, and a transfer calculation process 363 for the right PE 12.

In the transfer operation processing 361 for the self PE 12, first, data for masking other than a specific bit of the original image field C331 is set in the mask register 22 of the associative memory 11, and a search is performed with "1", so that the bit The original image field C331 is added to the flag register 27.
Transfers the contents of a specific bit of.

Next, in the corresponding bit of the shift image field RL335, "1" is partially written in parallel to the word of which the hit flag register 27 is "1". The above procedure is repeated for the number of bits of the original image field C331.

Next, if the corresponding structuring element (in this case, the origin (0, 0) is defined, the arithmetic processing is performed and the result is stored in the processed image field C + 332. The type of the arithmetic is as described above. In addition, for example, when the original image is multi-valued by dilation and the structuring element 341 is binary, the maximum value calculation is performed.

In the transfer arithmetic processing 362 for the left PE 12, first, data for masking other than specific bits of the shift image field RL335 (only the original image field C331 for the first time) is set in the mask register 22, and the search is performed with "1". To the hit flag register 27,
The contents of the specific bit of the shift image field RL335 (the original image field C331 only at the beginning) are transferred.

Next, the hit flag register 27 is downshifted m times, and "1" is written in parallel to the word of which the hit flag register 27 is "1" by the corresponding bit of the shift image field RL335. The above procedure is repeated for the number of bits of the shift image field RL335.
Next, if the corresponding structuring element ((-1, 0) in this case is defined, arithmetic processing is performed, and the result is stored in the processed image field C + 332.
0)-(-X2,0) Repeat until there are no structural elements defined.

In the transfer operation processing 363 for the right PE 12, first, data for masking other than a specific bit of the shift image field RL335 (the original image field C331 only at the beginning) is set in the mask register 22, and the search is performed with "1". Thus, the contents of the specific bit of the shift image field RL335 (only the original image field C331 at the beginning) is transferred to the hit flag register 27.

Next, the hit flag register 27 is shifted up by m times, and the hit flag register 27 writes "1" in parallel in the corresponding bit of the shift image field RL335 to the word of "1". The above procedure is repeated for the number of bits of the shift image field RL335. Next, if the corresponding structuring element ((1,0) in this case is defined, arithmetic processing is performed, and this result is stored in the processed image field C + 332.
0)-(X1,0) is repeated until there are no more structural elements.

By the above processing, (-X2,0)-(X
The morphological operation processing for the structuring elements distributed in (1, 0) ends. The above process is performed from process step 2 to Y1.
The transfer calculation process of + Y2 + 1 is similarly executed, and after the completion of all the steps, the morphology calculation process for all the structural elements ends.

FIG. 27 is a flow chart showing the image shift processing procedure 352 in detail by taking the processing step 353 (1) as an example.

The image shift processing procedure 352 includes internal word transfer 371 ... All transfers other than data transfer to the lower PE of the lower boundary word group 15 and upper and lower boundary word transfer 372. The data transfer to the lower PE is executed separately.

In the internal word transfer 371, first, the mask register 22 is set with data for masking other than a specific bit of the original image field C331, and a search is performed with "1", whereby the hit flag register 27 is sent to the original image field. The contents of the specific bit of C331 are transferred. Next, shift down the hit flag register 27 once,
At the corresponding bit of the shift image field UD ₁ 333, the hit flag register 27 writes “1” in parallel to the word of “1”. The above procedure is applied to the original image field C3.
Repeat for 31 bits.

In the upper / lower boundary word transfer 372, first, all bits of the original image field C331 of a specific word belonging to the lower word group 15 of the odd memory group 91 are stored in the upper word group 13 of the corresponding even memory group 92. Transfer to word shift image field UD ₁ 333. next,
All bits of the original image field C331 of the specific word belonging to the lower word group 15 of the even memory group 92 are transferred to the shift image field UD ₁ 333 of the word of the upper word group 13 of the corresponding odd memory group 91. These transfers are performed using a data write / read function for words using the address of the associative memory 11.

The above-mentioned processing is step 353 (Y1 + 1).
The same can be applied to shift-up processing such as.

The shift operation of the hit flag register 27 is performed by writing data in the word using the above address,
Since it has a mode to be performed simultaneously with reading, the upper and lower boundary word transfer 372 of the image shift processing procedure 352 is
The hit flag of the transfer operation process 351 can be shifted down and up at the same time, and the morphology operation process can be performed efficiently.

By mounting the above processing flowchart in the control unit 18 in the form of a program or state transition and sequentially giving instructions to the associative memory array unit 17,
The two-dimensional PE array device MS1 according to the above embodiment is
The morphological operation processing can be executed on the structural element having an arbitrary shape and size.

The two-dimensional PE array device MS1 of the above embodiment has a two-dimensional PE having the same number of PEs as the pixels of the original image, so that the processing speed depends on the size of the original image. do not do. Further, by providing a shift image field in a word of the associative memory and performing the morphological operation processing while sequentially transferring the data of the adjacent pixels to the shift image field, there is no limitation on the size of the structural element that can be processed. Therefore, it is possible to execute the morphology operation processing on a large structuring element and a large original image in a short processing time, and it is possible to realize a high-performance morphology operation processing device.

Since the associative memory used in the above embodiments can be constructed based on a memory technology having a very high degree of integration, one PE and a data transfer path can be realized with a small amount of hardware. Therefore, the two-dimensional PE array device MS1 can be realized with a small amount of hardware, and the device cost of the two-dimensional PE array device MS1 is reduced.

[0206]

According to the first aspect of the present invention, since the total data transfer time is suppressed and the amount of hardware is reduced, a high performance PE array device can be realized.

According to the second aspect of the invention, since the control unit is provided, it is possible to realize a two-dimensional PE array device having a shorter transfer time.

According to the third aspect of the invention, since a plurality of PEs are assigned to one word, a two-dimensional PE array device having a larger number of PEs can be realized with a small amount of hardware.

According to the invention described in claim 4, since there is a mode means for simultaneously executing the data writing / reading means for the word using the address and the shift mode means of the hit flag register, the total data transfer time is reduced. A more suppressed associative memory can be realized.

According to the fifth aspect of the invention, since the associative memory in which the entire data transfer time is further suppressed is used, a two-dimensional PE array device with a shorter transfer time can be realized.

According to the invention described in claim 6, since the entire data transfer time can be suppressed, a data transfer method having a short transfer time can be realized.

According to the invention described in claim 7, since a plurality of PEs are assigned to one word, a data transfer method having a shorter transfer time can be realized.

According to the invention as set forth in claim 8, since the entire data transfer time can be further suppressed, a data transfer method having a shorter transfer time can be realized.

According to the invention as set forth in claim 9, since the entire data transfer time can be further suppressed, a data transfer method with a shorter transfer time can be realized.

According to the tenth aspect of the present invention, since the entire data transfer time can be further suppressed, the associative memory data transfer method with a shorter transfer time can be realized.

According to the eleventh aspect of the present invention, since the entire data transfer time is suppressed and the amount of hardware is reduced, a high performance two-dimensional PE array device can be realized.

According to the twelfth aspect of the present invention, since the entire data transfer time is suppressed and the amount of hardware is reduced, a high-performance morphological operation processing method can be realized.

According to the thirteenth aspect of the present invention, since the entire data transfer time is further suppressed, it is possible to realize a higher performance morphological operation processing method.

According to the fourteenth aspect of the present invention, since the entire data transfer time is suppressed and the amount of hardware is reduced, a high-performance morphological operation processing method can be realized.

According to the fifteenth aspect of the present invention, since the entire data transfer time is suppressed and the amount of hardware is reduced, a high-performance morphological operation processing method can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of a two-dimensional PE array device PEA1 which is an embodiment of the present invention.

FIG. 2 is a diagram showing an associative memory 11 _(1,1) that constitutes the two-dimensional PE array device PEA1.

FIG. 3 is a diagram showing a case where the right, the lower, the left, and the upper 4 in the above-described embodiment.
Associative memory 1 for data transfer to adjacent PE
It is a figure which shows the allocation method of the word of 1 _(1,1) .

FIG. 4 is a word allocation method of the associative memory 11 _(1,1) in the case of transferring data to eight adjacent PEs on the right, lower right, lower, lower left, left, upper left, upper and upper right in the above embodiment. FIG.

FIG. 5 is a flowchart showing an overall processing procedure in the two-dimensional PE array device PEA1.

FIG. 6 is a flowchart showing a 4-adjacent internal word transfer procedure in the above embodiment.

FIG. 7 is a flowchart showing an 8-adjacent internal word transfer procedure in the above embodiment.

FIG. 8 is a flowchart showing an upper / lower boundary word transfer procedure 53 according to the second embodiment of the present invention.

FIG. 9 is a block diagram showing one word of the lower word group 15 of the odd-numbered associative memory group 91 in four adjacencies in the second embodiment.
FIG. 7 is a diagram showing an example of transfer to an even-numbered associative memory group 92.

FIG. 10 is a diagram showing an example of transferring one word of the lower word group 15 of the even-numbered associative memory group 92 in four adjacent areas to the odd-numbered associative memory group 91 in the second embodiment.

FIG. 11 is a diagram showing an example of transferring one word of the upper word group 13 of the odd-numbered associative memory group 91 in four adjacent to the even-numbered associative memory group 92 in the second embodiment.

FIG. 12 is a diagram showing an example of transferring one word of the upper word group 13 of the even-numbered associative memory group 92 in four adjacent areas to the odd-numbered associative memory group 91 in the second embodiment.

FIG. 13 illustrates a word 24 of the associative memory 11 in the two-dimensional PE array device PEA3 according to the third embodiment of the present invention.
It is a figure which shows the allocation method (in the case of 4 adjacency) to PE.

FIG. 14 is a diagram showing a word allocation method of an associative memory for realizing a two-dimensional PE array device having a data transfer function for four adjacent PEs on the right, bottom, left, and top.

FIG. 15 is a two-dimensional P having a data transfer function for eight adjacent PEs of right, lower right, lower, lower left, left, upper left, upper, upper right.
It is the figure which showed the word allocation method of the associative memory for implement | achieving an E array apparatus.

FIG. 16: Word type identification field I 148 or 1
It is a figure which shows 512.

FIG. 17 is a diagram showing an overall processing procedure for performing various kinds of processing using the two-dimensional PE array device having the above-described configuration.

FIG. 18 is a diagram showing a 4-adjacent internal word transfer procedure regarding internal word transfer 171 of data transfer 173 to an adjacent PE.

FIG. 19 is a diagram showing an 8-adjacent internal word transfer procedure regarding the internal word transfer 171 of the data transfer 173 to the adjacent PE.

20 is a diagram showing a configuration example of a two-dimensional PE array device in the case where two PEs are assigned to one word 24 of the associative memory 11. FIG.

FIG. 21 is a flowchart showing an internal word transfer procedure (52) to four adjacent PEs when two PEs are allocated to one word 24 of the associative memory 11.

FIG. 22 is a diagram showing a basic configuration of a two-dimensional PE array device MS1 which is another embodiment of the present invention.

FIG. 23 is a diagram showing in detail the field configuration of each word 24 in the associative memory 11 used in the two-dimensional PE array device MS1.

FIG. 24 is a diagram defining structural elements of morphology.

FIG. 25 is a flowchart showing the overall output procedure of the morphology calculation processing in the above embodiment.

FIG. 26 is a flowchart showing in detail the transfer calculation processing 351 by taking the processing step 353 (1) shown in FIG. 25 as an example.

FIG. 27 is a flowchart showing in detail an image shift processing procedure 252 by taking a processing step 353 (1) as an example.

FIG. 28 is a diagram showing a conventional two-dimensional PE array device PEA11.

FIG. 29 is a diagram showing a conventional two-dimensional PE array device PEA12.

FIG. 30 is a diagram showing a conventional associative memory M11.

FIG. 31 is a diagram showing a conventional morphological operation processing device.

[Explanation of symbols]

 PEA1, PEA3 Two-dimensional PE array device MS1 Morphology operation processing device 11 Associative memory 12 One word of associative memory 13 Upper boundary word group 14 Internal word group 15 Lower boundary word group 16 Associative memory hit flag shift line

Claims (15)

[Claims] 1. W words (where w is an arbitrary natural number) arranged in one dimension, a hit flag register that can be shifted up and down, and an upper shift input that puts the contents of this hit flag register in and out. Out of the associative memories, q × r associative memories having an output and a lower shift input / output (q and r are arbitrary integers of 2 or more), among the associative memories that are laterally adjacent to each other. A hit flag shift line that connects the lower shift input / output of one associative memory and the shift input / output of the other associative memory among the associative memories that are adjacent in the lateral direction, and w hit lines of the associative memory. Are sequentially allocated to PEs arranged in a zigzag pattern in m columns and n rows (w, m, n are arbitrary natural numbers satisfying w = m × n), and m × q in the vertical direction as a whole, Lateral direction n × r 2-dimensional PE array apparatus being characterized in that a PE of. 2. The two-dimensional PE array device according to claim 1, further comprising a control unit that generates a single control instruction stream for the associative memory array unit including the associative memory and the hit flag shift line. A two-dimensional PE array device characterized in that 3. The two-dimensional PE array device according to claim 1, wherein a plurality of PEs are assigned to one word of the associative memory, and one PE among the PEs has a current state field of its own PE and the PE. A two-dimensional PE array device further comprising a next state field of its own PE and each state field of adjacent PEs. 4. A word data writing / reading means using an address, a hit flag register shift mode means, a word data writing / reading means using the address, and the hit flag register shift mode means. An associative memory having mode means for simultaneously executing and. 5. The two-dimensional PE array device according to claim 1, wherein the associative memory includes means for writing and reading data to and from a word using an address, shift mode means for a hit flag register, A two-dimensional PE array device, which is an associative memory having a means for writing / reading data to / from a word using the address and a mode means for simultaneously executing the shift mode means of the hit flag register. 6. The word w (where w is an arbitrary natural number) is 1
The steps of arranging in a dimension and the contents of the hit flag register that can be shifted up and down between q × r (q and r are arbitrary integers of 2 or more) associative memories are upper shift input / output and lower shift input / output. Transferring data by putting it in and out of the associative memory, a lower shift input / output of one associative memory of the associative memory that is laterally adjacent to the associative memory, and the horizontally adjacent Connecting the shift input / output of the other associative memory with a hit flag shift line, and w words of the associative memory in m columns and n rows (m and n are w = m). A zigzag arrangement in an arbitrary natural number satisfying × n, and a step of allocating each of the w words of the associative memory to a PE. Data transfer method dimension PE array unit. 7. The data transfer method according to claim 6, wherein a plurality of PEs are allocated to one word of the associative memory, and one PE among the plurality of PEs has a current state field of its own PE. And the next state field of my PE,
Providing each current state field of adjacent PEs in said one word. 8. The word w (where w is an arbitrary natural number) is 1
The steps of arranging in a dimension and the contents of the hit flag register that can be shifted up and down between q × r (q and r are arbitrary integers of 2 or more) associative memories are upper shift input / output and lower shift input / output. Of the associative memory arranged in q columns in the vertical direction, from the associative memory group of odd columns to the associative memory group of even columns, or the associative memory group of even columns. A step of simultaneously performing data transfer from the associative memory group to the associative memory group of an odd number of columns, and a step of simultaneously performing the data transfer to all the associative memories arranged in the horizontal direction r rows. Characteristic data transfer method between associative memories. 9. One w (where w is an arbitrary natural number) word.
Arranging in a dimension, performing a mask search for matching the data stored in the word with the search data and ignoring a part of the search data, and searching in the first word specified by the mask search. Transferring the content of the specific bit to a first hit flag register that can be shifted up and down, and shifting up the transferred content of the first hit flag register to the second hit flag register of the second word of the transfer destination or Using the step of downshifting and parallel partial write to write the search data to the bits of the second word corresponding to the unmasked bits of the search data for the second word for which the second hit flag register has a specific value , To a particular bit in the second word
And a step of transferring the contents of the hit flag register. 10. A step of writing and reading data to and from a word using an address, a step in which a hit flag register executes a shift mode, a step of writing and reading data to and from a word using the address, and An associative memory data transfer method, wherein the hit flag register has a step of executing a shift mode and a step of simultaneously executing a shift mode. 11. A w-word (where w is an arbitrary natural number) word arranged in a one-dimensional manner and provided with an original image field, a processed image field and a shift image feed, and a hit flag register capable of shifting up and shifting down. , Q × r associative memories having upper shift input / output and lower shift input / output for putting the contents of the hit flag register in and out, and q × r Out of the associative memories, the lower shift input / output of one of the associative memories that are adjacent in the horizontal direction and the other associative memory of the associative memories that are adjacent in the horizontal direction And a hit flag shift line for connecting the shift input / output of each of the w and w words of the associative memory with m columns, n
PEs arranged in a zigzag pattern in rows (w, m, and n are arbitrary natural numbers that satisfy w = m × n) are sequentially allocated, and m × q PEs in the vertical direction and n × r PEs in the horizontal direction are totally allocated. A two-dimensional PE array device, comprising: an associative memory array section having the same; and a control section for giving a single control instruction stream to the associative memory array section. 12. A step of arranging w words (where w is an arbitrary natural number) in one dimension, and one original image field, one processed image field, one horizontal shift image field and two vertical shifts in each word. The contents of the hit flag register that can be shifted up or down between the step of providing the image field and the qxr number of associative memories (q and r are arbitrary integers of 2 or more) are input to the upper shift input / output and the lower shift input. Using the output to move in and out, the lower shift input / output of one of the associative memories of the q × r associative memories that are laterally adjacent to each other, and the horizontal shift input / output. Connecting the upper shift input / output of the other associative memory of the associative memories adjacent to each other in the direction by a hit flag shift line, and w of the associative memory. Each, m columns of words, n
PEs arranged in a zigzag pattern in rows (w, m, and n are arbitrary natural numbers that satisfy w = m × n) are sequentially allocated, and m × q PEs in the vertical direction and n × r PEs in the horizontal direction are totally allocated. A step of providing an associative memory array section having the step of: the control section giving a single control instruction stream to the associative memory array section; Transfer arithmetic processing step of sequentially transferring to the image field, performing arithmetic processing and storing in the processed image field, and transferring the data of the original image field of the PE in the vertical direction or the data of one vertical shift image field to the other vertical shift image field The image shift up / down processing step, the transfer calculation processing step and the image shift up / down processing step And a step of repeating until all transfer arithmetic processing from the PE in the lower left and right direction is completed, a morphological arithmetic processing method using a two-dimensional PE array device. 13. The morphological operation processing method according to claim 12, wherein the data of each element of the original image is transferred to the original image field of the corresponding PE of the two-dimensional PE array device, and is defined by a structural element. Arbitrary PE in up, down, left and right directions
And a step of performing data processing and arithmetic processing from the morphology arithmetic processing method. 14. The morphological operation processing method according to claim 12, wherein a mask search for a specific bit of the original image field or the vertically shifted image field and m upshifts or downshifts of m times (m is m in the m column). A data transfer processing step in which the processing and parallel partial writing to the corresponding bits of the left and right shift image fields are repeated by the number of bits of data, and when the data in the left and right shift image fields is data from the PE to be processed. Only, the arithmetic processing step of performing arithmetic processing on the processed image field and the left and right shifted image field and storing the result of the arithmetic processing in the processed image field, and the data transfer processing step and the arithmetic processing step from the left and right direction. Repeat until all transfer calculation processing is completed And a morphological operation processing method. 15. The morphological operation processing method according to claim 12, wherein a mask search for a specific bit in the original image field or one of the upper and lower shift image fields and one shift up or shift down process are performed.
By using the internal word transfer step that repeats the parallel partial writing for the corresponding bit of the other vertical shift image field by the number of bits of data, and the function of reading and writing data to the word using the address of the associative memory, All bits of the original image field or one upper shift image field of a particular word of the upper or lower word group of the memory group, and the upper or lower boundary word of the other upper or lower shift image field of the corresponding even or odd associative memory group. And a step of transferring the morphological operation processing method.