JPH09293045A - Data transfer processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transfer data to a hard disk with simple configuration by exchanging the number of bits of writing data stored in a storage means and the number of bits of reading data read from the storage means. SOLUTION: A main memory control circuit 2 alternately writes data for the portion of one sector in the high-order bit FIFO- A- H4 and the low-order bit FIFO- A- L5 of a bank A in FIFO 3 and, then, alternately writes data for the portion of one sector in the same way in the high-order bit FIFO- B- H6 and the low-order bit FIFO- B- L7 of the bank B. A DMA control circuit 9 simultaneously reads data from the high-order bit FIFO- A- H4 and then low- order bit FIFO- A- L5 of the bank A of FIFO 3 and executes DMA transfer to a SCSI-2 protocol controller 10 by word unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer processing device for transferring data to a hard disk used in a video server, for example.

[0002]

2. Description of the Related Art Conventionally, based on the demands of many users,
There has been a video server device that simultaneously supplies various images to individual users. First, an outline of the video server device will be described. The video server device includes a video stream server that performs a process of transmitting a video stream, and an application server that performs non-real-time processing such as a navigation function.

[0003] On the other hand, an application server plays a central role in exchanging information, and has a network protocol processing function necessary for exchanging information. The application server has a management database, and manages applications, management information, customer information, and the like in the management database.

On the other hand, the video stream server has a plurality of hard disks for storing data and a RAID (Redundant Arrays I) for writing and reading data to and from these hard disks.
A disk control circuit having a nexpensive Discs structure and a CPU for supplying an instruction for converting or rearranging data to the disk control circuit
A host computer for controlling the CPU, an encoding circuit for compressing and packetizing data, and a decoding circuit for decompressing data. There are three requirements for this video stream server: time continuity, simultaneous provision of the same video in parallel, and special playback processing.

The term "time continuity" as used herein means the following. That is, it means that the data accumulated in the video stream server is continuously read out once it is output, and there is no interruption. Further, the simultaneous provision of the same video in parallel means the following. That is, many users request one image or various images in parallel to the video stream server. This request is completely asynchronous. Even if the same image is requested, the time point of the request is slightly deviated. That is, hundreds or thousands of video streams must be output at different cue points at the same time. Therefore, real-time performance is required in terms of transmission. The special reproduction process means the following. That is, even if the video is started once, the user has to perform various control of the video stream, such as pause, rewind, and slow playback.

The operation of such a video stream server will be described below. At the time of recording a video, a video signal which has been highly efficient coded by MPEG2 or the like in the encoding circuit in advance is divided into segment data in sector units and packetized. The packetized segment data is stored in a plurality of data storage hard disks. By accumulating data on multiple hard disks,
This is because the number of simultaneous users for the same video can be increased. There are a random layout and a striping layout as methods of this distributed storage.
The random layout is suitable for storing multi-rate video, and the striping layout is characterized by high disk usage efficiency. The segment data distributed and accumulated in the striping layout is called a striping unit.

When reproducing a video, the disk control circuit reads the striping unit from the hard disk according to an allocation table showing a data array indicating on which disk the striping unit is stored. Then, the CPU rearranges the read striping units in the reproduction order, absorbs the fluctuations, expands them in the decoding circuit, and then sends them to the network. Special reproduction functions such as slow reproduction, fast forward, pause, and skip are realized by the disk control circuit adjusting the speed at which the striping unit is read.

Further, the disk control circuit distributes the striping units to a plurality of hard disks at the time of writing the data, and condenses the striping units, which are distributed oppositely at the time of reading the data, into one data stream.

In such a video stream server, the disk control circuit and the hard disk are S
It is connected by a CSI bus, and DMA transfer of data is performed between the disk control circuit and the hard disk based on an instruction from the CPU.

[0010]

However, in such a conventional video stream server, at the time of data recording, the data from the memory is transferred to the D in the disk control circuit.
MA Pre-fetches data to be transferred in a register and prepares for DMA transfer, but when the disk control circuit performs disconnect processing to release the SCSI bus, it is pre-fetched into a register in the disk control circuit. There is an inconvenience that data to be DMA-transferred disappears.

As described above, the reason for erasing the data to be DMA-transferred which has been prefetched in the register in the disk control circuit is that the bidirectional DMA transfer is possible. This is to prepare. Further, this disconnection process is a process based on the SCSI standard and must not occupy a bus that is not used for a certain period. Therefore, it means a process of releasing the bus when it is likely to occupy the bus for a certain period.

In order to prevent such inconvenience, S
By the time the CSI bus is connected, it is necessary to return the address of the memory that supplies the data to be prefetched to the register by the amount of the lost data and keep the data continuous. However, when a memory device such as SRAM or DRAM is used as the memory, it is necessary to always manage the address for returning the read pointer address of this memory device by the amount of the disappeared data. There was an inconvenience that it became complicated.

The data width output from the memory in the disk control circuit is 8 bits wide.
The data width of the SCSI-2 standard of the SCSI bus connecting the disk control circuit and the hard disk is 16-bit width or 32-bit width. Therefore, at the time of data recording, the 8-bit width data supplied from the memory is transferred to the SCSI-2 16-bit disk control circuit.
Data conversion from 8 bits to 16 bits or data conversion from 8 bits to 32 bits is required to be mounted on a SCSI bus having a bit width or a 32 bit width.

However, if this data conversion circuit is configured by using latches, the data transfer from the memory in the disk control circuit to the latch is synchronous transfer, but the SCSI DMA transfer from the latch in the disk control circuit to the hard disk. Is an asynchronous transfer, the interface between synchronous transfer and asynchronous transfer becomes complicated, and since the disconnect processing circuit and the data conversion circuit cannot be shared, the number of components increases and the circuit scale increases. There was an inconvenience that the cost increased.

The present invention has been made in consideration of the above point, and a circuit for performing disconnection processing and a circuit for performing data conversion processing are shared to perform data transfer to a hard disk with a simple configuration. It is an object of the present invention to provide a data transfer processing device capable of performing

[0016]

A data transfer processing device of the present invention stores a data supply source, a storage means for temporarily storing the data supplied from the data supply source, and a storage means for storing the data in the storage means. A data transfer device having a control means for reading the stored data and transferring the data via a transfer line in accordance with a predetermined transfer regulation, in response to a request from the control means, the data is read from the storage means and transferred. Data re-transfer means for re-reading the stored data and re-transferring the data, and data for converting the number of bits of the write data stored in the storage means and the number of bits of the read data read from the storage means And a conversion means.

According to the data transfer processing device of the present invention,
It works as follows. When there is a data transfer request from the control means, data is supplied from the data supply source to the storage means.
In the present invention, in particular, at the time of data transfer, the control means prepares for the transfer by temporarily storing the data to be transferred from the storage means, but when the control means performs the process of releasing the transfer line. The data retransfer means rereads the data read and transferred from the storage means and retransfers the data so that the data to be transferred is not erased.

The data width supplied to the storage means,
The bit width of the data transferred via the transfer line is different based on the transfer rule. Therefore, when transferring data,
In the data conversion means, data conversion processing is performed in order to put the data of the bit width supplied from the storage means on the transfer line based on the transfer regulation, and the data transfer from the data supply source to the storage means is synchronous transfer. Since the transfer from the storage means via the transfer line is an asynchronous transfer,
The processing of synchronous transfer and asynchronous transfer is performed without lowering the transfer rate. That is, the data retransfer processing by the data retransfer means and the data conversion processing by the data conversion means are both performed. In this way, the data supplied from the data supply source is transferred from the storage means via the transfer line without disappearing the data and without lowering the transfer rate.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION This embodiment will be described below. First, the configuration of the AV server system of this embodiment will be described. The AV server system of this embodiment shown in FIG. 8 corresponds to a video stream server in a video server device.

This AV server system includes a hard disk unit 106 for storing a plurality of data of up to 7,
107, 108, 109, 120, 111, 112,
These hard disk units 106, 107, 10
RAID (Redun) that performs data write / read processing for 8, 109, 120, 111, and 112.
dant Arrays Inexpensive D
a disk control circuit 101 having an iscs configuration,
A CPU 104 that supplies a command for converting and rearranging data to the disk control circuit 101;
Host computer 105 for controlling U104 and encoding circuit 10 for compressing and packetizing data
0, a decoding circuit 113 for decompressing data,
And a monitor 114 for reproducing data.

Here, the disk control circuit 101
Is a recording system DMA transfer block 102 and a reproduction system DMA.
And a transfer block 103. There are three requirements for this video stream server: time continuity, simultaneous provision of the same video in parallel, and special playback processing. The three conditions are as described in the related art.

An SDI (serial digital interface) bus 115 is connected to the data input side of the encoding circuit 100. The data output side of the encoding circuit 100 and the data input side of the recording DMA transfer block 102 of the disk control circuit 101 are SDDI.
(Serial digital data interface) Bus 1
16 are connected. The data output side of the reproduction DMA transfer block 103 of the disc control circuit 101 and the data input side of the decoding circuit 113 are SDDI.
It is connected via a bus 120. Decoding circuit 11
The data output side of 3 and the monitor 114 are connected to SDI bus 121
Connected through.

The data output side of the recording DMA transfer block 102 and the data output side of the reproduction DMA transfer block 103 of the disk control circuit 101 and the hard disk units 106, 107, 108 and 109,
120, 111 and 112 are connected via a SCSI bus 119. Host computer 105 and CPU1
04 is connected via Ethernet. CPU
Recording system DM of 104 and disk control circuit 101
The A transfer block 102 and the reproduction DMA transfer block 103 are connected via the RS232C.

The operation of the AV server system of the present embodiment thus constructed will be described with reference to the block diagram of FIG. First, the data write operation will be described. When a write request is issued from the host computer 105 to the CPU 104, a write command is supplied to the CPU 104 via the Ethernet 118 and the SD is sent to the encoding circuit 100.
Video data is supplied via the I-bus. CPU10
4 converts the supplied command into a SCSI command. The video data is digitally formatted in the D1 or D2 format. The video data may be compressed in advance or may not be compressed in advance. When not compressed, the encoding circuit 100 compresses the video data by MPEG2 and packetizes it. The CPU 104 separates the video data compressed and packetized by the encoding circuit 100 and the SCSI command into different phases, and the recording system DM of the disk control circuit 101.
It is supplied to the A transfer block 102.

The recording DMA transfer block 102 of the disc control circuit 101 creates a file system for writing video data. That is, a striping unit for each sector is created to create a file system in which which block size of which video data is transferred to which block address. In this example, in particular, at the time of data recording, a prefetch for temporarily accumulating data to be DMA-transferred from a memory in a register in the disk control circuit is performed to prepare for DMA transfer. When the disconnection process for releasing is performed, the data retransfer process is performed so that the prefetched data to be DMA-transferred in the register in the disk control circuit is not lost.

The data width output from the memory in the disk control circuit is 8 bits wide.
The data width of the SCSI-2 standard of the SCSI bus connecting the disk control circuit and the hard disk unit is 16 bits or 32 bits. Therefore, at the time of data recording, in the disc control circuit,
The 8-bit width data supplied from the memory is SCSI-
Data conversion processing from 8 bits to 16 bits or data conversion from 8 bits to 32 bits for mounting on a 16-bit width or 32-bit width SCSI bus of 2 and from the memory in the disk control circuit to the latch Data transfer is synchronous transfer, but the SCS from the latch in the disk control circuit to the hard disk
Since the DMA transfer of I is an asynchronous transfer, the processing of the synchronous transfer and the asynchronous transfer is performed without lowering the transfer rate.
That is, the disconnection process and the data conversion process are performed by the shared circuit. In this way, the video data is recorded in the recording system DM of the disc control circuit 101.
A transfer block 102 to hard disk unit 10
6, 107, 108, 109, 120, 111, 112
DMA transfer to the SCSI bus 119 is performed.

Next, the data reproducing operation will be described. When there is a read request from the host computer 105 to the CPU 104, a read command is supplied to the CPU 104 via the Ethernet 118, and the CPU 104 converts the supplied command into a SCSI command. The CPU 104 supplies the SCSI command to the reproduction DMA transfer block 103 of the disc control circuit 101. Video data is stored in the hard disk units 106, 107, 10
Playback system DMA from 8, 109, 120, 111, 112
DM to transfer block 103 via SCSI bus 119
A is transferred. The playback DMA transfer block 103 is SC
Converts SI-2 16-bit width or 32-bit width data to 8-bit width data. SDDI bus 1 from reproduction system DMA transfer block 103 to decoding circuit 111
Video data is supplied via 20. The 8-bit video data is expanded by the decoding circuit 113. SDI bus 121 from decode circuit 113 to monitor 114
The video data is supplied via.

Next, the structure and operation of the recording DMA transfer block of this embodiment will be described with reference to FIG. The recording system DMA transfer block shown in FIG. 1 corresponds to A shown in FIG.
It corresponds to the recording system DMA transfer block 102 of the disk control circuit 101 in the V server system.

First, the structure of the recording DMA transfer block of this embodiment will be described. This recording system DMA transfer block includes a main memory 1 for temporarily storing video data supplied via the SDDI 116 shown in FIG. 8, a main memory control circuit 2 for controlling the main memory 1, and a main memory 1 DM for data transfer and data read for writing data
A FIFO 3 that performs disconnection processing and data conversion processing at the time of A transfer, and a three-state buffer 8 that switches between a recording system and a reproduction system of bidirectional DMA transfer.
8, the DMA control circuit 9 for controlling the DMA transfer process, and the hard disk units 106, 107, 108 and 10 shown in FIG.
9, a SCSI-2 protocol controller (SPC) 10 for controlling a protocol of DMA transfer between the terminals 120, 111, and 112. The SCSI-2 protocol controller (SPC) 10 has a register 11 for prefetching data to be DMA-transferred. FI
FO3 is a FIFO for upper bytes forming bank A
A FIFO for H4 and low byte A L5
And a FIFO for the upper bytes that make up bank B B
FIFO for H6 and low byte B L7.

Output side of main memory control circuit 2
And FIFO A H4, FIFO A L5, FIFO
B H6, FIFO B 8-bit data from the L7 input side
It is connected via a data bus 12. FIFO A
H4, FIFO A L5, FIFO B H6, FI
FO B The output side of L7 and the three-state buffer 8
Connected to the input side via a 16-bit data bus 13
ing. Output side and three-state buffer 8
Memory 19 and SCSI-2 protocol controller
The input side of the (SPC) 10 is a 16-bit DMA data bus
It is connected via a switch 13. SCSI-2 protocol
The output side of the controller (SPC) 10 is a SCSI bus
15 is connected. SCSI bus 15 is shown in FIG.
It corresponds to the SCSI bus 119. Also, SCSI-2
Protocol controller (SPC) 10 and DMA controller
A CPU bus 16 is connected to the roll circuit 9. CPU
The bus 16 corresponds to the RS232C117 shown in FIG.
You.

In addition, the FIFO A H4, FIFO A
L5, FIFO B H6, FIFO B To L7
Are 27 [MHz] write clocks 17 and 10.
The read clock 18 of [MHz] is supplied. Also,
From the DMA control circuit 9 to the main memory controller
Data transfer request signal DATA to the circuit 2 Supplied by REQ
Is done. Main memory control circuit 2 to FIFO
A H4, FIFO A L5, FIFO B H6
FIFO B The write enable signal WE is supplied to L7.
A H, WE A L, WE B H, WE B L is
Each is supplied. Also main memory control
Circuit 2 to FIFO A H4, FIFO A L5, F
IFO B H6, FIFO B Light L7
The set signal RSTW is supplied. Also, the DMA controller
Roll circuit 9 to FIFO A H4, FIFO A L
5 is a read enable signal FIFO A RE and
Output enable signal FIFO A OE supply
Is done. DMA control circuit 9 to FIFO B
H6, FIFO B Read enable signal for L7
FIFO B RE and output enable signal
FIFO B OE is supplied. Also, the DMA controller
Roll circuit 9 to FIFO A H4, FIFO A
L5, FIFO B H6, FIFO B For L7,
The read reset signal RSTR is supplied.

Further, the DMA control circuit 9 supplies the three-state buffer 8 with an output enable signal OE for switching to the recording system in the bidirectional DMA transfer. DM from the SCSI-2 protocol controller (SPC) 10 to the DMA control circuit 9
The A transfer request signal DREQ is supplied. A data acknowledge signal DACK and an IO write signal IOWR are supplied from the DMA control circuit 9 to the SCSI-2 protocol controller (SPC) 10.

Here, the main memory control circuit 2
Temporarily stores in the main memory 1 the video data supplied in synchronization with the video frame signal via the SDDI bus 116 shown in FIG. It has an interface function of synchronous transfer and asynchronous transfer for interfacing with. Further, the main memory control circuit 2 receives the data transfer request signal DATA supplied from the DMA control circuit 9. FIFO by REQ A
H4 and FIFO A L5 or FIFO B
H6 and FIFO B The L7 has a FIFO data writing function for writing the data by alternately allocating the video data read from the main memory 1 in units of the write clock to the upper byte and the lower byte.

Further, the FIFO 3 stops the data writing in the bank which is reading data out of the two banks A and B by the read reset signal RSTR supplied from the DMA control circuit 9 during the disconnecting process. Then, it has a disconnect processing function of returning the read address to the head position and retransferring the data at the time of reconnection. Further, when writing data, the FIFO 3 alternately stores 8-bit data in units of the write clock 17 in the bank A alternately with the upper byte and the lower byte.
Further, one sector per bank is written in the upper bit FIFO and the lower bit FIFO of bank B. When reading data, the high-order bit FIFO of one of the two banks A and B
Also, it has a data conversion function from 8 bits to 16 bits for simultaneously reading 16 bits of data from the lower bit FIFO. Here, the FIFO 3 constitutes a data retransfer means and a data conversion means.

Further, the DMA control circuit 9 uses the SC
Data is transferred between the SI-2 protocol controller (SPC) 10 and the SCSI-2 protocol controller by a handshake for confirming the mutual operation using the control signals for data transmission and data reception. (SPC) 10 DMA transfer request signal DR
It has a DMA transfer control function for controlling the data read from the FIFO 3 by the EQ and performing the DMA transfer in units of words (16 bits). Also,
The DMA control circuit 9 sends a data transfer request signal DATA to the memory control circuit 2 every time DMA transfer of data for one sector is performed. It has a data transfer request function for issuing REQ. Further, the DMA control circuit 9 has a read reset signal supply function of supplying a read reset signal RSTR to the FIFO 3 by an instruction from the CPU 104 when the SCSI bus 15 is disconnected. Further, the FIFO 3 constitutes a storage means, and includes the CPU 104, the DMA control circuit 9,
The main memory control circuit 2 and the SPC 10 constitute a control means, the SCSI bus 15 constitutes a transfer line, and the transfer regulation is the SCSI-2 protocol.

The recording system D of this embodiment constructed as described above.
The operation of the MA transfer block will be described below. First, FIG.
The DMA transfer operation of the FIFO 3 will be described with reference to FIG. In FIG. 2, after starting, the initialization processing of the recording DMA transfer block is performed in step S1. When the recording operation is started in step S2, the CPU 104
A standby command is issued to the DMA control circuit 9 via the bus 16. The DMA control circuit 9 which has received the standby command in step S3 sends a data transfer request signal DATA to the main memory control circuit 2. The REQ is issued twice to request the data transfer from the main memory 1 to the FIFO 3 for 2 sectors.

In step S4, the main memory control circuit 2 firstly, the high-order bit FIFO of the bank A of the FIFO3. A FIFO for H4 and lower bits A
Alternately write data for one sector to L5, then
FIFO for upper bits of bank B B FIFO for H6 and lower bits B Similarly, data for one sector is alternately written to L7. This puts the two banks, bank A and bank B, into a standby state in which data for a total of two sectors has been written.

In step S5, the DMA control circuit 9
Is a SCSI-2 protocol controller (SPC) 1
By the DMA transfer request signal DREQ from 0, the FIFO
Two high-order bit FIFOs of bank A of 3 A H4
And low-order bit FIFO A Simultaneous data from L5
To read SCSI-by word (16 bits) units.
2 Protocol controller (SPC) 10 DM
A transfer is performed.

In step S6, the DMA control circuit 9 sends a data transfer request signal DATA to the main memory control circuit 2 when the data read from the bank A of the FIFO 3 has reached one sector. REQ is issued, and data transfer for one sector is requested from the main memory 1 to the bank A of the FIFO 3.

In step S7, the next data is read from the bank B of the FIFO 3 as before, and the DMA transfer of the bank B is performed. In step S8, the DMA control circuit 9 of the main memory control circuit 2 is FIFO.
While data is being read from the bank B of No. 3, data is transferred from the main memory 1 to the bank A and written.

Then, in step S9, the DMA control circuit 9 sends a data transfer request signal DATA to the main memory control circuit 2 when the data read from the bank B of the FIFO 3 has reached one sector. RE
Issue Q, main memory 1 to FIFO 3 bank B
To request data transfer for one sector.

In step S10, the next data is read from the bank A of the FIFO 3 in the same manner as described above, and the bank A is read.
DMA transfer is performed. In step S11, the main memory control circuit 2 determines that the DMA control circuit 9 is FI.
While data is being read from bank A of FO3, data is transferred from main memory 1 to bank B and written.

If the DMA transfer is not completed in step S12, the process returns to step S6 to repeat the processes and determinations of steps S6 to S12. That is, writing and reading are alternately performed for the bank A and the bank B, and processing is performed so that the DMA transfer is continued. When the DMA transfer ends in step S12, the end ends.

The write and read operations for the FIFO 3 are performed based on the SCSI command supplied from the CPU 104. In this way, the data of the striping unit DMA-transferred is transferred to the hard disk units 106, 107, 108, 109, 11
Write at 0, 111, 112. In this case, the plurality of hard disk units 106, 107, 108, 109, 11
A write operation is performed so that striping units are distributed and stored in 0, 111, and 112.

In addition, the write operation to the FIFO3
From the main memory control circuit 2 to the FIFO A
H4, FIFO A L5, FIFO B H6, F
IFO B Write enable signal W supplied to L7
E A H, WE A L, WE B H, WE B
It is performed by controlling L. in this case,
The main memory control circuit 2 is a FIFO 3
Write one sector's worth of data to KU A and Bank B
Write clock 17 to 4096 clocks
It is performed by counting the number of minutes.

The read operation for the FIFO 3 is performed by the DMA control circuit 9 to the FIFO. A H
4, FIFO A Read enable signal FIFO supplied to L5 A RE and output enable signal FIFO A This is done by controlling the OE. Similarly, from the DMA control circuit 9 to FI
FO B H6, FIFO B Read enable signal FIFO supplied to L7 B RE and output enable signal FIFO B This is done by controlling the OE.

Next, referring to FIGS. 3 and 5, SP
The operation of the C disconnection process will be described. In this disconnection process, it is premised that the SPC 10 disconnects the SCSI bus 15 with a data length of a sector unit and does not disconnect in the middle of a sector. Such management is performed by the CPU 104 managing the SPC 10 with software.

Now, the operation mode of the SPC 10 will be described. There are two operation modes of the SPC 10, an initiator and a target. The initiator is an operation mode in which the SPC 10 serves as a control body and controls a partner to be controlled. The target is an operation mode in which the SPC 10 is a control target and is controlled by the CPU 104 of the other party who is the control subject. When in the initiator and target operating modes, the SPC 10 operates as a master and a slave, respectively.

In FIG. 3, start and step L
Recording starts at 1 and data is DMAed as shown in FIG.
Transferred. In step L2, the SPC 10 operates as an initiator, and when the SCSI bus 15 is connected,
For DMA transfer, 32 bytes of data are prefetched into the internal register 11 having a storage capacity of 32 bytes, and the DMA transfer is continued. In FIG. 5A, in the case of recording, 32 bytes of data at the position of the read address 22 in the DMA transfer data 20 of the FIFO of one sector becomes the SPC prefetch data 21.

In step L3, while continuing the recording operation, for some reason, for example, the hard disk units 106, 107, 108, 109, 110 as the targets, 110, 1
When the SCSI bus 15 is temporarily disconnected by the SPC 10 when the recording capacity of the receive buffers 11 and 112 is exceeded, the register 11 in the SPC 10 is temporarily disconnected.
The 32 bytes of data pre-fetched are also cleared and disappear. In FIG. 5B, when a disconnection occurs, the SPC prefetch data 21 of 32 bytes at the position of the read address 22 of the FIFO DMA transfer data 20 of one sector becomes the disappearance data 23.

At this time, in step L4, the CPU 104
Is the DMA control circuit 9 and the SCSI bus 15 is S
CPU bus that is disconnected by PC10
Notify via 16. Receive this notification in step L5
The digit DMA control circuit 9 is a FIFO of the FIFO3.
O A H4, FIFO A L5, FIFO B H
6, FIFO B Read reset signal for L7
Issue RSTR (FIFOREAD RESET)
You. FIFO of FIFO3 in step L6 A H4
FIFO A L5, FIFO B H6, FIFO
B L7 is read by the read reset signal RSTR.
Return the dress to the starting position. In FIG. 5C, the read reset
FI of one sector when the set signal RSTR is issued
Read address 22 of FO DMA transfer data 20
Returns from the reading position of the disappearance data to the head position 24.
In this case, the FIFO3 has two banks A and B.
Data read and data write alternate
The bank that is reading data is
We have stopped writing.

At step L7, the SCSI bus 15 becomes SP.
Reconnected by C10, DMA from SPC10
When the DMA transfer request signal DREQ is supplied to the control circuit 9, the DMA control circuit 9 restarts the DMA transfer from the head position of the sector of the lost data in step L8, and ends at the end. In FIG. 5D, 1
Of the DMA transfer data 20 of the FIFO of the sector, the retransfer data 25 in which the read address 22 is the same as the read position of the disappearance data can be transferred as the SPC prefetch data 21.

In this way, the disconnection process
Since the operation is performed in units of sectors, the 32-byte data that has been prefetched and lost in the register 11 inside the SPC 10 can be read again from the FIFO 3 only by returning the read address of the FIFO 3 to the head position. Further, since the FIFO 3 is provided and the data length of the disconnection process is set to 1 sector, the address management of the FIFO 3 becomes unnecessary, and the process can be performed only by the read reset signal RSTR to the FIFO 3.

Next, referring to FIGS. 4 and 6, FI
The operation of the data conversion process from 8 bits to 16 bits of FO will be described. Start and advance FI in step M1
The FO is initialized and the write address and read address counters are set to zero. When recording is started in step M2, the DMA control circuit 9
Data transfer request signal DATA to the main memory control circuit 2 REQ is issued and the main memory 1 requests the FIFO 3 to transfer data for one sector. In step M4, the main memory control circuit causes the data transfer request signal DATA Every time REQ is supplied, 8-bit data is read from the main memory 1.

In step M5, the F of the bank A of the FIFO 3 is
IFO A H4 and FIFO A 8-bit data on L5
Alternately write the upper and lower bytes of the data
When writing 8-bit data for 1 sector
Stop. Also, in step M6, the FIFO3 van
Ku B FIFO B H6 and FIFO B To L7
Alternate upper byte and lower byte of 8-bit data
When writing and writing 8-bit data for one sector
Stop writing. In this way, one bank
The data for one sector is written alternately. In FIG.
The 8-bit data 30 has 8-bit 31
It has a width and a bank using the write clock 17.
FIFO for upper byte of A or bank B H4
Odd data 33 in (6), FIFO for lower byte
Write even data 34 to L5 (7) by write operation 32
Get in.

In step M7, the SPC 10 supplies the DMA transfer request signal DREQ to the DMA control circuit 9. In step M8, the DMA control circuit 9 makes the FIF
FIFO of bank A of O3 A H4 and FIFO
A 16 bytes from upper byte and lower byte at the same time from L5
Bit data is read and DMA transfer is performed. Step M
In 9 the DMA control circuit 9 is bank B of the FIFO3.
FIFO B H6 and FIFO B 16-bit data of the upper byte and the lower byte are read from L7 at the same time, and DMA transfer is performed. In FIG. 6, the read clock 18 is used to output the FIFO for the upper byte of the bank A or the bank B. H4 (6) odd number data 33, FIFO for lower byte The even data 34 of L5 (7) is simultaneously read by the read operation 35, and the odd data and the even data are combined to have 16 bits 3
16-bit data 37 having a width of 6 is read.

By doing so, the 8-bit data synchronously transferred from the main memory 1 is interfaced to the asynchronous transfer to the SCSI bus 15 without lowering the transfer rate, and the 8-bit data is transferred from the 8-bit data to the 16-bit data. Data conversion can be performed.

Next, referring to FIG. 7, the FI of another embodiment will be described.
The configuration and operation of the FO will be described. As shown in FIG.
The FIFO in this example is a two bank bank, bank A or bank B.
The point that it is the same as the previous example is the same as the previous example, but the difference is that
Bank A in FIFO A 1 (40), FIFO A
2 (41), FIFO A 3 (42), FIFO A
Recording four 8-bit data 48 of 4 (43)
And the bank B is FIFO. B 1
(44), FIFO B 2 (45), FIFO B
3 (46), FIFO B Four 8 bits of 4 (47)
In the point that it is configured to be able to record the data 48
You. Other configurations are the same as the previous example, so the description is omitted
You.

With this configuration, the bank A
FIFO A 1 (40), FIFO A 2 (4
1), FIFO A 3 (42), FIFO A Four
The 32-bit data 49 can be read by simultaneously reading the four 8-bit data 48 of (43). Similarly, the FIFO of bank B is also B 1 (4
4), FIFO B 2 (45), FIFO B 3
(46), FIFO B The 32-bit data 49 can be read by simultaneously reading the four 8-bit data 48 of 4 (47). In this way, 8
Data conversion from bits to 32 bits can be performed.

Also in this example, as in the previous example, the FIF
The write operation to O is the main memory control
Circuit 2 to FIFO A 1 (40), FIFO A
2 (41), FIFO A 3 (42), FIFO A
4 (43), FIFO B 1 (44), FIFO B
2 (45), FIFO B 3 (46), FIFO
B 4 (47), write enable signal W
E A 1, WE A 2, WE A 3, WE A
4, WE B 1, WE B 2, WE B 3, WE
B 4 is controlled. This place
If the main memory control circuit 2
Data for one sector for link A and bank B
Write clock 17 is set to 4096 black so that it can be written.
This is done by counting the number of ticks.

The read operation for the FIFO is as follows:
DMA control circuit 9 to FIFO A 1 (4
0), FIFO A 2 (41), FIFO A Three
(42), FIFO A 4 (43)
Mode enable signal FIFO A RE and output
Enable signal FIFO A Control OE
It is done by doing. Similarly, a DMA control circuit
FIFO from 9 B 1 (44), FIFO B 2
(45), FIFO B 3 (46), FIFO B 4
Read enable signal FIFO supplied to (47)
B RE and output enable signal FIFO
B This is done by controlling the OE.

According to the above example, the disconnect processing circuit and the 8-bit to 16-bit data conversion circuit are FIF.
O3 can be shared, and since it is not necessary to manage the write address and read address of the FIFO3 by using the FIFO3, the circuit can be simplified and the cost can be reduced. Further, according to the above example, the present invention can also be applied to the 32-bit data bus of the SCSI-2 standard by adding the FIFO and changing the control. Further, in the above example, the FIFO 3 is a two-bank system of the bank A or the bank B.
The circuit for arbitrating the conflict between the write address and the read address of 3, that is, the circuit for arbitrating so that the pointer address of the read address does not exceed the pointer address of the write address becomes unnecessary, and the circuit can be simplified. Further, in the above example, with respect to the DMA transfer request signal DREQ from the SPC 10 to the DMA control circuit 9, the transfer can be started within 2 clocks without waiting for the DMA transfer. It is possible to maintain the maximum transfer rate (160 [Mbps]) of the SPC 10 and perform the DMA transfer without dropping.

The data transfer processing apparatus of the above example stores a data supply source, a FIFO 3 as a storage means for temporarily storing the data supplied from the data supply source, and stores the data in the FIFO 3 and stores the stored data. In a data transfer device having a DMA control circuit 9, a main memory control circuit 2, and an SPC 10 as a control means for reading and transferring data through the SCSI bus 15 as a transfer line by the SCSI-2 protocol as a predetermined transfer rule. , DMA control circuit 9 as control means, main memory control circuit 2, SPC
In response to the request of 10, the FIFO 3 as the data retransfer means for rereading the data read and transferred from the FIFO 3 as the storage means and retransferring the data
And a FIFO3 as a data conversion means for converting the number of bits of the write data stored in the FIFO3 as the storage means and the number of bits of the read data read from the FIFO3 as the storage means.

According to the above example, the data retransfer means and the data conversion means can be shared by the FIFO 3, and since the FIFO 3 is used, it is not necessary to manage the write address and read address of the FIFO 3. The circuit can be simplified and the cost can be reduced.

In the data transfer processing device of the above example, the SPC 10 as the control means occupies the SCSI bus 15 as the transfer line for a certain period of time on the basis of the SCSI-2 protocol as the transfer regulation. When the SPC 10 as the control means relinquishes the SCSI bus 15 as the transfer line after abandoning the SCSI bus 15 as the transfer line, which has been occupied by the SPC 10 as the control means, the data retransfer means The data is re-transferred by the FIFO 3 as described above.

According to the above example, the SPC1 as the control means
For the DMA transfer request signal DREQ from 0 to the DMA control circuit 9, without waiting for the DMA transfer,
Since the transfer can be started within 2 clocks in response to the request, the DM can be maintained while maintaining the maximum transfer rate (160 [Mbps]) of the SPC 10 without lowering the transfer rate.
A transfer can be performed.

Further, in the above-described data transfer processing device, in the above description, the FIFO 3 as the data converting means has a plurality of FIFO 3 as the storing means, and the number of bits of the write data is alternately written in the FIFO 3 as the plurality of storing means. Of 8 bits as the storage means, the 8-bit data written in the FIFO 3 serving as the storage means are simultaneously read from the FIFO 3 serving as the storage means, and 16 bits or 32 bits as the number of read data bits are read. It was made to be a bit.

According to the above example, the present invention can be applied to the SCSI-2 standard 32-bit data bus by adding the FIFO and changing the control. In the above example, F
Since the IFO3 has a two-bank system of bank A or bank B, a circuit that arbitrates the conflict between the write address and the read address of the FIFO3, that is, a circuit that arbitrates so that the pointer address of the read address does not exceed the pointer address of the write address. Is unnecessary and the circuit can be simplified.

[0069]

According to the data transfer processing device of the present invention, the data supply source, the storage means for temporarily storing the data supplied from the data supply source, the storage means for storing the data, and the stored data. In a data transfer device having a control unit that reads out and transfers data through a transfer line according to a predetermined transfer rule, in response to a request from the control unit,
Data retransfer means for rereading the data read from the storage means and transferred and retransferring the data, the number of bits of write data stored in the storage means and the number of bits of read data read from the storage means The data re-transfer means and the data conversion means can be shared, and the data re-transfer means can re-transfer the data read from the storage means and transferred. Since the data is read and the data is retransferred, there is no need to manage the write address and the read address of the storage means, so that the circuit can be simplified and the cost can be reduced.

Further, the data transfer processing device of the present invention is
In the above description, when the control means occupies the transfer line for a certain period of time based on the transfer regulation, the control means relinquishes the transfer line after the control means abandoned the transfer line which was occupied for the transfer. In addition, since the data is retransferred by the data retransfer means, the data to be transferred is not erased, and the data transfer can be performed without waiting for the data transfer request from the control means. Since the transfer can be started, the maximum transfer rate can be maintained and the data can be transferred without lowering the transfer rate.

Further, the data transfer processing device of the present invention is
In the above description, the data conversion means has a plurality of storage means, writes data in the plurality of storage means alternately according to the number of bits of write data, and simultaneously writes the data written in the plurality of storage means from the plurality of storage means. Read
Since it is set to the number of bits of read data, it can be applied to the number of bits of all data transferred via the transfer line based on the transfer rule, and arbitration of the conflict between the write address and the read address of the storage means. Circuit, that is, a circuit for arbitrating so that the pointer address of the read address does not exceed the pointer address of the write address becomes unnecessary, and the circuit can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a recording-system DMA transfer block of this embodiment.

FIG. 2 is a flowchart showing an operation of a FIFO DMA transfer according to the present embodiment.

FIG. 3 is a flowchart showing the disconnection processing operation of the SPC of this embodiment.

FIG. 4 is a flow chart showing an 8-bit to 16-bit data conversion process of the FIFO of this embodiment.

5A and 5B are conceptual diagrams of disconnection processing of the present embodiment, FIG. 5A shows during recording, FIG. 5B shows disconnection, FIG. 5C shows RSTR issuance, and FIG. 5D shows recording restart. Is.

FIG. 6 is a conceptual diagram of 8-bit to 16-bit data conversion processing according to the present embodiment.

FIG. 7 is a diagram showing the structure of a FIFO of another embodiment.

FIG. 8 is a block diagram showing a configuration of an AV server system according to the present embodiment.

[Explanation of symbols]

 1 main memory, 2 main memory control times
Road, 3 FIFO, 4 FIFO A H, 5 FIF
O A L, 6 FIFO B H, 7 FIFO B
L, 8 three-state buffer, 9 DMA controller
Circuit, 10 SCSI-2 protocol controller
(SPC), 11 registers, 12 8-bit data buffer
Data bus, 13 16-bit data bus, 14 16-bit D
MA data bus, 15 SCSI bus, 16 CPU bus
17 write clock, 18 read clock, 19
 Read memory, DMA transfer data of 20 FIFO,
21 SPC register prefetch data, 22
Address, 23 disappearance data, 24 start position, 2
5 re-transfer data, 308 bit data, 318 bit
32, write operation, 33 odd data, 34 even
Data, 35 read operation, 36 16 bits, 37
 16-bit data, 40 FIFO A 1,41 F
IFO A 2,42 FIFO A 3,43 FI
FO A 4,44 FIFO B 1,45 FIFO
B 2,46 FIFO B 3,47 FIFO B
4,48 8-bit data, 49 32-bit data
, 100 encoding circuit, 101 disk controller
Roll circuit, 102 Recording system DMA transfer block, 10
3 playback system DMA transfer block, 104 CPU, 10
5 host computer, 106 hard disk unit
G, 107 hard disk unit, 108 hardware
Disk unit, 109 hard disk unit,
110 hard disk unit, 111 hard disk
Disk unit, 112 Hard disk unit, 11
3 decode circuit, 114 monitor, 115 SDI bus
, 116 SDDI bus, 117 RS232C, 1
18 Ethernet, 119 SCSI bus, 120 S
DDI bus, 121 SDI bus

Claims (3)

[Claims] 1. A data supply source, storage means for temporarily storing data supplied from the data supply source, data stored in the storage means, and the stored data is read out according to a predetermined transfer rule. In a data transfer device having a control means for transferring data via a transfer line, in response to a request from the control means, the data read and transferred from the storage means is read again to re-read the data. Data comprising a data retransfer means for transferring, and a data converting means for converting the number of bits of the write data stored in the storage means and the number of bits of the read data read from the storage means. Transfer processor. 2. The data transfer processing device according to claim 1, wherein the control means occupies the transfer line for a certain period of time on the basis of the transfer regulation, whereby the control means occupies for transfer. A data transfer processing device, wherein when the control means reoccupies the transfer line after abandoning the transfer line, the data retransfer means retransfers the data. 3. The data transfer processing device according to claim 1, wherein the data conversion means has a plurality of the storage means, and data is written in the plurality of storage means alternately by the number of bits of the write data. A data transfer processing device, characterized in that the data written in the plurality of storage means are simultaneously read from the plurality of storage means to obtain a bit number of the read data.