JPH09284256A - Spread spectrum communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase amount of information sent by one period of a PN code series and to attain a high information transmission rate. SOLUTION: An MUX 3 selects plural PN code series whose phases are offset from a shift register 2 and the selects signals for their inversion/ noninversion are controlled by a switch section 4. The PN code series from the switch section 4 are added by an adder section 5 and the result is sent as a Q component. On the other hand, the PN code series from a shift register 1 is sent as an I component. The PN code series of the I component is used for a phase reference for the Q component PN code series, and the transmission data are sent by combination of phase offsets, and inverting/noninverting control of them. Thus, the transmission rate is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum communication system capable of improving a transmission rate.

[0002]

2. Description of the Related Art In a spread spectrum communication system, transmission data is multiplied by a PN code or the like to spread its spectrum on the frequency axis and the spread spectrum transmission data is transmitted. In such a spread spectrum communication method, the spectrum of the transmission data is spread to approximate white noise, there are many kinds of spread codes, and the correlation between spread codes is suppressed to a small level. It has excellent confidentiality, high frequency efficiency, and noise resistance. From this, future mobile communications,
This is a promising communication method for wireless LAN and the like.

FIG. 15 shows an outline of a transmission side of a spread spectrum (hereinafter referred to as SS) communication system using QPSK modulation. 15, 102 and 105 are BPSK modulators, 107 is a PN code generator (PN.G) that generates a PN code sequence, and 108 is a carrier wave phase of π /.
It is a phase shifter that shifts the phase by 2. In the transmitting unit shown in this figure, the data generated by the data generating unit (DATA1) 100 is transmitted to the PN. It is added to the PN code generated in G107. Further, the data generated by the data generation unit (DATA2) 103 is transmitted to the PN. It is added to the PN code generated in G107. In this case, one cycle of the PN code is assigned to 1 bit of the data, and in the addition in the adder 101 and the adder 104, for example, when the data is "0", the PN code is output as it is, and the data is "1". In the case of ", an exclusive OR operation for inverting and outputting the PN code is performed.

The output of the adder 101 is the BPSK modulator 10
The carrier wave generated by the carrier wave oscillator 109 is input to the signal 2 and BPSK-modulated. Further, the output of the adder 104 is input to the BPSK modulator 105, and the phase shifter 10
The carrier wave generated by the carrier wave oscillator 109 having a phase shift of π / 2 by 8 is BPSK modulated. This allows
The in-phase component (hereinafter, referred to as I component) of the QPSK modulation output is obtained from the BPSK modulator 102, and the BPSK modulator 1
From 05, the quadrature component (hereinafter referred to as the Q component) of the QPSK modulation output is obtained. And these two BPSK
By adding the modulated outputs in the adder 106, Q
It becomes a PSK modulated wave. This QPSK modulated wave is the antenna 1
Sent from 10. As a result, the spread spectrum QPSK multiplexed signal is transmitted from the transmitter.

Although the configuration on the receiving side is not shown, after receiving the spread spectrum multiplexed signal and separating it into I and Q components, the same PN code as the PN code on the transmitting side is applied to each component. Data is demodulated by using the correlation with the received signal. In this case, the data transmitted with the inverted PN code has a negative correlation output, and the data transmitted with the PN code as it is without being inverted has a positive correlation output.

[0006]

As described above, the conventional spread spectrum communication system has excellent communication confidentiality, high frequency efficiency, and noise resistance. Since one period of PN code is assigned to one bit of transmission data, there is a drawback that the data transmission capacity is small. Further, since the spectrum is spread, the frequency band of the transmission data becomes extremely wide, and the frequency utilization efficiency becomes low. Therefore, an object of the present invention is to provide a spread spectrum communication system capable of improving data transmission capacity and communication speed.

[0007]

In order to achieve the above object, a spread spectrum communication system according to the present invention comprises a first P
In a spread spectrum communication method in which an N code sequence and a second code sequence having the same period as the first PN code sequence are multiplexed and transmitted, the second code sequence has a predetermined phase offset. It is generated by adding a number of basic PN code sequences, and transmission information is defined by a combination of each phase offset sequence of the predetermined number of basic PN code sequences with respect to the reference phase of the first PN code sequence. .

In the spread spectrum communication system, the polarity of the first PN code sequence is controlled according to the content of a predetermined bit of transmission information. Further, the polarities of the respective basic PN code sequences forming the second code sequence are controlled according to the contents of a plurality of predetermined bits of the transmission information. Furthermore, the first PN code sequence and the second code sequence are generated by a single PN code generating means. Furthermore, the first PN code sequence and the second code sequence may be transmitted by carrier waves having different frequencies.

In the spread spectrum communication system as described above, the first phase which gives the reference phase by one of the multiplexed signals
The PN code sequence is transmitted, and the second code sequence obtained by adding a plurality of PN code sequences to which a phase offset is added by the other is transmitted. Then, the information can be defined by the combination of the phase offsets in the second code sequence, and the information can be defined by the polarities of the plurality of PN code sequences. Therefore, more information can be defined in one cycle of the PN code sequence, and a high information transmission rate can be realized.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Next, the spread spectrum (S
S) FIG. 1 shows the configuration of the first embodiment of the transmitting section in the communication system. The SS communication system of the present invention uses QAM modulation, and FIG. 1 shows a configuration up to baseband modulation before QAM modulation. In FIG.
Reference numeral 2 is a shift register having a feedback path, and the stored PN code sequence is a clock CLKm.
It is shifted at every timing, and circulates in the shift register. The PN code sequence circulating in the shift register 1 and the PN code sequence circulating in the shift register 2 may be the same or different code sequences. Of chips, that is, the period of one cycle of the PN code sequence is the same. The PN code sequence output from the shift register 1 is QA
It becomes the input data of the I component when M modulation is performed.

The output PN of each stage of the shift register 2
1 to PNn are input to the multiplexer (MUX) 3, respectively. These outputs PN1 to PNn are PN
Since they are code sequences and given a phase offset, their correlation is very small. Furthermore, MUX3 has (M
-R) bits of input data have been input, and this (M
According to the information of the (R) -bit input data, two or more input PN code sequences PN1 to PNn are combined and output from the MUX 3. The number of outputs of this PN code sequence is R. Next, R output from MUX3
The PN code sequence is input to the switch unit 4. R-bit input data is input to the switch unit 4, and according to each bit of the R-bit input data,
The polarities of the R PN code sequences supplied from the MUX 3 are controlled. For example, the bit of "0" is output without inverting the PN code sequence, and the bit of "1" is inverted and output.

The R PN code sequences thus controlled are added together in the adder circuit 5 and output. This addition output becomes the input data of the Q component when performing QAM modulation. The input data to be transmitted by the transmission unit is input as serial data to the serial / parallel converter (S / P) 6 and the data clock C
At the timing of LKd, one block is converted into parallel data of M bit width. Then, the M-bit width parallel data is divided into R bits and (M−R) bits,
The (M−R) bits are supplied to the MUX 3 as control data, and the remaining R bits are supplied to the switch unit 4 as control data.

The information transmission rate of data in this transmitting section is as follows. First, N PN code sequences PN1
Because you selected R number of ～PNn, it would send a combination of _N C _R. Also, since the polarities of the R PN code sequences are controlled, 2 ^R combinations can be sent. Therefore, the number of bits that can be sent in this case is log ₂ (2 ^R · _{N CR} ) [bit] (1), and the information transmission rate R _N is RN = _N , where N is the number of chips in the PN code sequence. {Log ₂ (2 ^R · _N C _R )} / N [bit / symbol] (2) According to the conventional SS communication method using QAM modulation, the number of bits that can be sent in one cycle of the PN code sequence is
Since the I-phase has 1 bit and the Q-phase has 1 bit, and the transmission rate R _Q thereof is 2 / N, the present invention can remarkably increase the information transmission rate.

For example, when N = 128 and R = 2, the conventional transmission rate R _Q is 1/64, whereas according to the present invention, the transmission rate R _N is about 15/128, about 7 The transmission rate is 5 times. Further, if N is 85, a transmission rate of about 12928 times can be achieved. As described above, in the SS communication system of the present invention, a plurality of offset PN code sequences generated by phase offsetting a single PN code sequence by data to be transmitted are combined according to the data to be transmitted. ,
In addition to improving the data capacity that can be transmitted, the data capacity is further improved by controlling the polarities of the combined PN code sequences in accordance with the data to be transmitted.

In this case, on the receiving side, a plurality of correlation peaks of the number of PN code sequences combined from the Q component are obtained, and the transmission data is decoded at the plurality of correlation peak positions. Therefore, the reference phase of the peak position is required, and this reference phase is obtained by transmitting the PN code sequence output from the shift register 1 by the I component. FIG. 2 shows a configuration example of the receiving side in the SS communication system of the present invention. In FIG. 2, by demodulating and separating the QAM-modulated signal, the I component signal I for obtaining the reference phase and the Q component signal Q modulated by the transmission data are obtained. This signal I is input to the matched filter (MF1) 10 and the PN code sequence is correlated. In this case, the PN code sequence stored in the shift register 1 in the transmission unit is set in the matched filter 10 as a multiplier.

In the matched filter 10, the input signal I is fetched at each timing of the clock CLKm, and when the circulating multiplier and the fetched signal I are correlated, a correlation peak is output. This correlation peak is detected by the peak detection circuit TH11.
This detection signal is supplied to the decoder (DEC) 18 as the first trigger signal (trg1), and the decoder 18 decodes (M−R) bits. Further, the signal Q is a matched filter (MF2) 12 and a matched filter (MF
3) Alternately taken into 13 and taken alternately with the PN code sequence. In this case the matched filters 12, 1
In 3, the PN code sequence stored in the shift register 2 in the transmission unit is set as a multiplier and circulated.

At the timing when the signal Q is taken in the matched filter 12, the matched filter 13
The correlation calculation is performed while the PN code sequence taken in is circulated, and the matched filter 13 receives the signal Q.
At the timing when is taken in, the matched filter 12 is performing the correlation calculation. In this way, the matched filters 12 and 13 alternately take in the signal Q and perform the correlation calculation. At this time, the clock CLKs that alternatively gives the timing of fetching the signal Q
And the clock CLKm for circulating the PN code sequence are supplied to the matched filters 12 and 13.

The correlation output calculated by the matched filters 12 and 13 is the multiplexer (MUX) 1
It is selected from 4 and output. The positive correlation peak of the correlation output output from the MUX 14 is detected by the peak detection circuit 15, and the negative correlation peak is detected by the peak detection circuit 16 and supplied to the OR circuit 17 and the determination circuit 21. The correlation peak output combined in the OR circuit 17 is supplied to the decoder 18 as the second trigger signal (trg2), and the decoder 18 determines the time positions of the R second trigger signals based on the first trigger signal. The decoded data of (M−R) bits is obtained by decoding. This decoded data is input to the P / S converter 22 as 0 bits to (M−R−1) bits.

Further, in the judgment circuit 21, the polarities of the correlation peaks detected in the peak detection circuits 15 and 16 are judged, and the polarities of the R correlation peaks in which the correlation is detected in the PN code sequence of one cycle are determined. Accordingly, R pieces of data are demodulated as "0" or "1". The demodulated R data are input to the P / S converter 22 as (M−R) to (M−1) R-bit data. Then, 0 to (M-1) input to the P / S converter 22
M bits of are converted into serial data and output.
The conversion timing in this case is the data clock CLKd.
Is based on.

As described above, in the receiving section in the SS communication system of the present invention, a plurality of correlation peaks are obtained in one cycle of the PN code sequence, and the transmission data can be decoded according to the number and timing of the correlation peaks. , The transmission data can be decoded according to the polarity of each correlation peak. As a result, the transmission data transmitted at the transmission rate shown in the equation (2) can be decoded.

Next, a second embodiment of the SS communication system of the present invention will be described with reference to FIGS. 3 to 11. FIG. 3 shows the configuration of the transmission unit. In FIG. 3, the PN code sequence for spread spectrum is a shift register R.
This shift register REG1 is stored in EG1.
From the final stage of, the PN code sequence is output and input to the polarity control unit PC (n + 1). Then, in the polarity control unit PC (n + 1), the polarity is controlled by the 1-bit Dpm of the transmission data, and the PN code sequence is output as it is or its inverted signal is output as the I component.

Each stage of the shift register REG1 is connected to the multiplexer MUX30, and the first control signal CTRL11 controls the multiplexer MUX30 to store the PN code sequence stored in the shift register REG1 (from the last stage to the PN code in FIG. 3). Series PN1
, And PN code sequences PN2, ..., PNn whose phases are offset toward the first stage are sequentially output. ) Is phase-offset and R are selected and passed.

PN passed through multiplexer MUX30
The R pieces of data in the code sequence are the polarity control circuits P, respectively.
Input to C1 to PCR. Polarity control circuits PC1 to PC
The second control signal CTRL12 is supplied to each R, and the polarity of the PN code sequence that has passed through the multiplexer MUX30 is controlled according to the second control signal CTRL12. Polarity control circuit PC1-PCR
Have the same configuration, and each of the inverting circuits NOT1
~ NOTR and multiplexers MUX1 to MUXR. In the polarity control circuits PC1 to PCR, inputs (PN code sequences before inversion) and outputs (PN code sequences after inversion) of the inversion circuits NOT1 to NOTR are input to the multiplexers MUX1 to MUXR. For example, the multiplexer MUXl receives the input and output of the inverting circuit NOT1l, and which PN code sequence is output is
It is controlled by the second control signal CTRL12.

On the other hand, the polarity control circuit PC (n + 1) to which the output of the final stage of the shift register REG1 is input.
Is an inverting circuit NOTn + 1 and a multiplexer MUXn to which the input and output of the inverting circuit NOTn + 1 are input.
It is composed of +1. This multiplexer MUX
The n + 1 switching control is controlled according to the signal DPm, and the supplied PN code sequence or its inverted signal is output as the I component. The second control signal CTRL12 is input to each of the multiplexers MUX1 to MUXR, and the control signal C
This multiplexer MUX1 to MU by TRL12
XR is switch-controlled. Multiplexers MUX1 to M
The output of the UXR is input to the adder circuit ADD1, all added in the adder circuit ADD1, and output as the Q component.

That is, the Q component is a superposition of a predetermined number R of PN code sequences, and in the present invention, the offset P is used.
Transmission data is transmitted by a plurality of combinations of N code sequences and inversion and non-inversion of each PN code sequence. Next, from the transmission data, the first control signal CTRL11 and the second control signal CTRL1
2. The configuration for generating the signal DPm is shown in FIG. In FIG. 4, the serial data DS to be transmitted is synchronized with a predetermined data clock CLKd, and the serial / parallel conversion circuit (S / S
P2) allows 1 block of m-bit parallel data D
It is converted to Pl to DPm. Of these, r-bit data DP1 to DPr are input to the decoder DEC21 and
The control signal CTRL12 is generated, and (m-r-
1) Bits DPr + 1 to DPm-1 are decoders DEC
The first control signal CTRL11 is generated by being input to the control circuit 22. The remaining 1-bit DPm is input to the multiplexer MUXn + 1 as the third control signal.

In this case, for example, the number of chips n in the PN code sequence is n = 16, and the number of bits m of parallel data is m =
9 and P selected by the multiplexer MUX30
When the number R of N code sequences is R = 2, the serial data DS to be transmitted is converted into parallel data every 9 bits, and the I component is inverted by the most significant 1 bit DPm,
The next 6 high-order bits are input to the decoder DEC22 and the first
The control signal CTRL11 is generated and control is performed so that the PN code sequence passes through two of the multiplexers MUX30. Also, the lower 2 bits are used for the decoder DEC21.
To generate the second control signal CTRL12, and the two series of PNs passed through the multiplexer MUX30.
Controls the inversion and non-inversion of the code sequence.

In this case, 6 <log ₂ ( ₁₆ C ₂ ) <7 (3), and the combination of two PN code sequences (peak position on the receiving side) in 16 chips causes transmission of the upper 6 bits. Sufficient to represent the data. Further, inversion / non-inversion control of each polarity (peak polarity on the receiving side) of the selected two PN code sequences may be performed by assigning the lower 2 bits of data to each PN code sequence. I understand.

Next, FIG. 5 shows a configuration example of the adder circuit ADD1. As shown in this figure, the adder circuit ADD1 outputs the outputs from the multiplexers MUX1 to MUXR to the input voltage Vi.
n31 to Vin3R, and these input voltages are integrated by the capacitive coupling CP3 composed of capacitors C31 to C3R. The output of the capacitive coupling CP3 is input to an inverting amplifier circuit including three-stage MOS inverters I31, I32, and I33, and the output of the inverter I33 is the feedback capacitance CF.
It is fed back to the input of the inverter I31 via the input terminal 3.
This inverting amplifier circuit has a sufficiently high open loop gain and operates as an operational amplifier. Therefore, by forming a feedback system with this inverting amplifier circuit, the output Vout3 represented by the following equation (4) can be output from the inverter I33 with high linear characteristics.

[Equation 1] Here, C31 = C32 = ... = C3R = CF3 / R (5) is set, and the equation (4) is rewritten as the following equation (6).

[Equation 2]

That is, the adder circuit ADD1 is Vin31.
Outputs a voltage corresponding to the addition result of Vin3R. This output is appropriately subjected to processing such as inversion and scaling, and is transmitted from the transmission unit. When performing digital processing in the transmitter, the adder circuit ADD1 may be configured by a known digital circuit to generate a digital output.

Next, FIG. 7 shows a configuration for decoding the PN code sequence in the receiving section of the second embodiment of the SS communication system of the present invention. The receiving section shown in FIG. 7 receives the IAM component and the Q component which have been QAM-modulated and transmitted and then demodulated by a receiving section (not shown) and separated. This I
The component is input to the matched filter MF1, and the Q component is input to the matched filters MF2 and MF3. The same PN code sequence as the I component PN code sequence in the transmitting unit is set as a multiplier in the matched filter MF1,
When the input signal of the I component and the multiplier of the matched filter MF1 match, the matched filter MF1 produces a correlation peak. The output of the matched filter MF1 is input to the peak detection circuits TH1 and TH2, and the peak detection circuit TH1 detects a positive (non-inverted) peak and the peak detection circuit TH2 detects a negative (inverted) peak.

The outputs of the peak detection circuits TH1 and TH2 are input to the OR circuit OR41, and when either one detects a peak, the first trigger signal TG1 is generated. Furthermore, the outputs of the peak detection circuits TH1 and TH2 are input to the first determination circuit J41, and when the peak detection circuit TH2 does not detect the peak and the peak detection circuit TH1 detects the peak, the first determination circuit J41 is at the low level. The first determination signal Jo1 of is generated. Further, when the peak detection circuit TH1 does not detect a peak and the peak detection circuit TH2 detects a peak, the first determination circuit J41 outputs the high-level first signal.
The determination signal Jo1 is generated. As described above, the first determination signal Jo1 corresponds to the transmission data DPm in the transmission unit, and the first determination signal Jo1 is the decoded data of the data DPm.

Data of the Q component is input to one of the matched filter MF2 and the matched filter MF3, and the input of the Q component is stopped when the OR circuit OR41 outputs the first trigger signal TG1. Then, the input of the Q component to the other matched filter (MF3 or MF2) is started. Then, the PN code sequence is circulated in the matched filter in which the input of the Q component is stopped, and the correlation peak signal is output at the timing when the correlation is obtained.
In this case, since a plurality of PN code sequences are combined and transmitted from the transmission unit, a plurality of correlation peak signals are obtained from the matched filter that performs the correlation calculation.

The multiplexer MUX10 is supplied with a clock CLKm for giving a data fetch timing, and the matched filters MF2 and MF3 are alternatively supplied with the clock CLKs generated from the clock CLKm.
Is entered. This is a flip-flop FF4
1, FF42 and the multiplexer MUX10, the clock CLKm is input to the multiplexer MUX10, and the control signal CTRL4 is used as a selection signal from the multiplexer MUX10.
The clock CLKs is supplied to either one of the matched filters MF2 and MF3.

Then, according to the clock CLKs, one of the matched filters MF2 and MF3 fetches the input Q component data. The multiplexer MUX10 is switched and controlled by the control signal CTRL4, and the control signal CTRL4 is triggered by the operation of the two-stage flip-flops FF41 and FF42.
It is inverted every time 1 is input. The flip-flop FF41 has a clock input (CK) terminal to which the trigger signal TG1 is input, and a data input (D) terminal to which the inverted output (Q bar) of the flip-flop FF42 is input. The flip-flop FF42 has its data input (D) terminal to which the inverted output (Q bar) of the flip-flop FF41 is input, and its clock input (C
The first trigger signal TG1 is input to the (K) terminal.
As a result, the output of the flip-flop FF42 is
Each time the first trigger signal TG1 is input, the high level state and the low level state are alternately repeated.

With the above configuration, when the first trigger signal TG1 is output at a certain point in time, it is assumed that the clock CLKs has been input to the matched filter MF2 until then.
The multiplexer MUX10 is switched so that the clock CLKs is supplied to the matched filter MF3. After that, the data taken in the matched filter MF2 is held as it is, and the PN code sequence of the matched filter MF2 is circulated. On the other hand, the selector SEL4 has the matched filter MF2 when the first trigger signal TG1 is output.
It is switched to the side. This switching control is performed by the control signal CTRL4. The output of the selector SEL4 is input to the peak detection circuits TH3 and TH4, and the second trigger signal TG2 is output when the peak detection circuit TH3 that detects a positive peak or the peak detection circuit TH4 that detects a negative peak detects a peak. Is output. The second trigger signal TG2 is output from the OR circuit OR42 to which the outputs of the peak detection circuits TH3 and TH4 are input.

Further, the outputs of the peak detection circuits TH3 and TH4 are inputted to the second judgment circuit J42, and the peak detection circuit T42 is inputted.
When H3 detects a peak and the peak detection circuit TH4 does not detect a peak, the second determination circuit j42 determines that a positive peak has been detected. Also, the peak detection circuit T
When H3 does not detect a peak and peak detection circuit TH4 detects a peak, second determination circuit J42 determines that a negative peak has been detected. In this case, the second determination circuit J42
The second determination signal Jo2 becomes low level when a negative peak is detected, and maintains high level when a positive peak is detected.

Next, the first trigger signal TG output by decoding the PN code sequence in the configuration shown in FIG.
FIG. 6 shows a configuration for obtaining decoded serial data from the first determination signal Jo1, the second trigger signal TG2, and the second determination signal Jo2. In FIG. 6, the second trigger signal TG2 is input to the data input (D) terminal of the shift register SREG1, and the clock CLKm is supplied to the clock input (CK) terminal. In addition, the reset input (RS) of the shift register SREGl has a first
The trigger signal TG1 is input, and the first trigger signal T
When G1 is supplied, the shift register SREG1 is reset, and then the second trigger signal TG2 is sequentially written to the shift register SREG1 at the timing when the second trigger signal TG2 is output in synchronization with the clock CLKm.

Since the second trigger signal TG2 is at the high level only when the peak detector TH2 or the peak detector TH3 detects the peak, the shift register SRE is set.
A data string including R "1" s in n bits is written in G1. This shift register SREGl
Output is input to the encoder E5, and the encoder E5
However, by performing the reverse processing of the decoder DEC22 shown in FIG. 4, DPR + 1 to DPm-1 are decoded. Further, as described above, the data DPm is decoded as the first determination signal Jo1.

Further, the second determination signal Jo2 is connected to the data input (D) terminal of the shift register SREG2, and the second trigger signal TG2 is input to the clock input (CK) terminal thereof. The first trigger signal TG1 is input to the reset input (RS) of the shift register SREG2. That is, when the first trigger signal TG1 is input to the shift register SREG2, the shift register SREG2 is reset. Then, thereafter, each time the second trigger signal TG2 is input to the shift register SREG2, the output of the second determination signal Jo2 is sequentially written to the shift register SREG2. Therefore, the shift register S
REG2 has an R-bit binary data string, that is, DP1
~ The DPR will be decoded. This is the lower R
The bits have been decoded.

Furthermore, the encoder E5, the output of the shift register SREG2, and the first determination signal Jo1 are input to the shift register SREG3 as a series of bit strings. These data are PN code sequences of one cycle,
That is, since it is determined every generation cycle of the first trigger signal TG1, by inputting the first trigger signal TG1 to the data load control terminal (LOAD) of the shift register SREG3, the shift register is shifted at the timing of the first trigger signal TG1. The above data is captured in SREG3. That is, the encoders E5 and the outputs DP1 to D of the shift register SREG2 are generated when the first trigger signal TG1 is generated.
Pm−1 and the first determination signal Jo1 (DPm) are captured by the shift register SREG3.

Since the data clock CLKd is constantly input to the shift register SREG3, the transmission signals DP1 to Dpm are sent from the shift register SREG3.
Serial output is performed at each timing of the data clock CLKd. As a result, demodulated data obtained by demodulating the transmitted signal can be obtained.

Next, FIG. 8 shows an example of the configuration of the matched filters MF2 and MF3. The control signal CTRL6 that is the logical product of the first trigger signal TG1 and the inverted signal of the control signal CTRL4 is the down counter (D_
It is indicated by COUNTER. The number n of chips for one cycle of the PN code sequence which is input to the data load control input terminal (LOAD) and is supplied to the data input terminal (Din).
Are loaded into D_COUNTER. Also, D-C
The binary output of the OUNTER (f bit) is input to the AND gate (AND) 6 after all ORs are taken by the OR gate (OR) 6, and the clock C
The logical product with LKm is taken. Therefore, AND6 is D_
It is opened when the counter value of COUNTER is 1 or more, and the clock CLKm passes through AND6. As a result, MF2 does not sample the input signal and D_CO
The AND6 is opened only while the UNTER counts the n clocks CLKm.

The f bits are the number of bits corresponding to the number of chips n and have the value shown in the following equation (7). log ₂ n ≦ f <log ₂ n + 1 (7) As described above, the AND6 is opened for only one period of the PN code sequence, so that the first trigger signal TG1 is generated and sampling of the sampling hold SH is completed. From the time point, the reception data stored in the shift register REG6 is circulated once. Then, every time the shift register REG6 is shifted, the data held in the sampling hold SH is multiplied by the PN code sequence set in the REG6. The multiplied data are added in the adder circuit ADD6 to generate a correlation output.

When n clocks CLKm are input to D_COUNTER after the output of the first trigger signal TG1, the count value of D-COUNTER becomes "0",
AND6 is closed. Then, the next correlation calculation process is prepared. Since the matched filter that circulates the PN code sequence as described above cannot take in the Q component that is new reception data, the supply of the clock CLKs is stopped and the other matched filter (MF2) is used as described above. Or clock CLKs to MF3)
Is supplied to take in the Q component.

Matched filter MF operating in this way
The operation timings of 2 and MF3 are shown in FIG. As shown in this figure, when the first trigger signal TG1 is generated at the time point t1, the PN code sequence stored in the matched filter MF2 is circulated to perform the correlation calculation. As a result,
Correlation outputs are obtained at time t2 and time t3.
The second trigger signal TG2 is generated by this correlation output. During this period, the received data is taken into the matched filter MF3 for one period of the PN code sequence. When the first trigger signal TG1 is generated again at the time point t4, the PN code sequence in the matched filter MF3 is circulated and the correlation calculation is performed. As a result, correlation outputs are obtained at time points t5 and t6. The second trigger signal TG2 is generated by this correlation output.

Such an operation is repeated in the matched filter MF2 and the matched filter MF3 to obtain the second trigger signal TG2 as shown.
Next, the above description will be described in more detail with reference to FIG. 10, and in this example, one cycle of the PN code sequence is 13 chips, and R = 2, that is, the Q component is two offset PN code sequences. Shall be the sum of Then, the first trigger signal TG1 is generated every 13 chips, and the first determination signal Jo1 indicating the polarity of its peak is generated in synchronization with the first trigger signal TG1. This first
The data DPm is generated by the determination signal Jo1 as illustrated.

Further, when the correlation calculation of the Q component is performed, since two offset PN code sequences are included, two second trigger signals TG2 are generated in one cycle as shown in the figure. When the second trigger signal TG2 is taken into the shift register SREG1, it becomes "0010000001000" as shown in the figure. When the data stored in the shift register SREG1 is input to the encoder E5, for example, 6 bits of "000101" are decoded. This decoded data is output in parallel from the encoder E5. Further, if the second determination signal Jo2 generated in synchronization with the second trigger signal TG2 is generated as shown in the figure, the shift register S
As shown in the figure, the data "10" is taken into REG2.

Then, the output of the encoder E5, the output of the shift register SREG2, and the signal DPm are loaded into the shift register SREG3, and the data clock CLKd.
The 9-bit serial data DS1 shifted and decoded based on the above is obtained as shown in the figure. In this case, 9
In the bit serial data DS1, the first bit is the signal DPm, the subsequent 6 bits are the encoder E5 output, and the last 2 bits are the shift register SREG2 output.

As described above, the information to be transmitted is I
When the peak phase difference between the component and the Q component and the peaks are inverted and non-inverted, the information rate Rn in n chips (one chip time is Tc) is Rn = log ₂ (2 ^{R + 1} · _{n CR} ) / n · Tc (8) However, R is the peak number of the Q component, that is, the number of offset PN code sequences to be transmitted. On the other hand, the information rate R when the I channel and the Q channel respectively transmit 1-bit information by the conventional n chip
q is Rq = 2 / n · Tc ( 9), the ratio of the two (hereinafter, referred to as the information rate ratio.) _{is, Rn / Rq = log 2 (} 2 R + 1 · n C R) / 2 (10 ).

The information rate ratio Rn / Rq when the number of chips n and the number of peaks are changed with respect to the equation (8) is as shown in FIG. 11, and it can be seen that the amount of information is increased to several times that of the conventional case.
This is synonymous with increasing the communication speed. In the above embodiments, the transmission and reception were performed under the condition that the peak number R of the Q component was constant, but it is also possible to make R variable, and such an embodiment also has a circuit configuration similar to that described above. You can send and receive by. The outline of the third embodiment will be described below.

For example, the number of chips n = 16, 1 to be transmitted
The number of bits of the block is m = 10, 1 ≦ R (the peak number of Q component) ≦ 2, and the value p of the data block is “0” to “1”.
When 11111 ″ (binary), R = 1 is set, the inversion and non-inversion of the I component are defined by the MSB of the data block, the inversion and non-inversion of the peak are defined by the LSB of the data block, and the peak position (16 When p> “1111111” (“0001000000” to “111111111”)
1 ″), R = 2, and the inversion and non-inversion of the I component depending on the MSB of the data block
Definition of peak inversion and non-inversion is defined by bits. The information Ifn that can be transmitted under such a condition is Ifn = log ₂ (2 ³ × ₁₆ C ₂ +2 ² × ₁₆ C ₁ ) ≧ 10 (11), and the information amount of 10 bits in one cycle of the PN code sequence. It will be possible to transmit.

13 and 14 show the configurations of a decoder and an encoder for realizing the third embodiment. In FIG. 13, serial data DS to be transmitted is converted into m-bit parallel data blocks DP1 to DPm by a serial / parallel conversion circuit (S / P) 8 in synchronization with the data clock CLKd. DPm, which is 1 bit in this parallel data, controls the inversion of the I component, and the remaining (m-1) bit data is decoded by the decoder DEC.
8 converts the first control signal CRTL81 and the second control signal 82 into the second control signal 82. The first control signal CTRL81 is the first control signal CTRL1.
The second control signal CTR is used to open and close a gate that allows the offset PN code sequence to pass therethrough.
L82 is used for the polarity control of the polarity control units PC1 to PCn similarly to the second control signal CTRL12.

On the other hand, on the receiving side, as shown in FIG. 14, the shift register SREG4 captures the second trigger signal TG2 in synchronization with the clock CLKm, and the shift register SREG5 uses the second trigger signal TG2 as a clock to make a determination signal Jo. Is taken in to generate a bit string indicating peak inversion, non-inversion, and the number of peaks and peak positions. Shift register SREG
4 and the data of the shift register SREG5 are input to the encoder E9 and converted into transmitted one block of parallel data DP1 to Dpm. Parallel data D
P1 to DPm are taken into the shift register SREG6 in synchronization with the first trigger signal TG1 and then output as serial data DS in synchronization with the data clock CLKd.

Generally, when the number of peaks is 0 to R, 1
If the chip time is Tc, the information rate is given by the following equation (12).
Is expressed as

(Equation 3) Therefore, the information rate ratio Rn / Rq is given by the following equation (13).

(Equation 4) Here, an example of the information rate ratio Rn / Rq in the case where the number of peaks of the Q component R = 4 is shown in FIG.

[0055]

As described above, according to the spread spectrum communication system of the present invention, a first reference phase is provided by one of the multiplexed signals.
The PN code sequence is transmitted, and the second PN code sequence obtained by adding a predetermined number of PN code sequences to which a phase offset has been added is transmitted. As a result, it is possible to combine the PN code sequence given the phase offset with the data to be transmitted and to control the polarity according to the data to be transmitted. Therefore, it is possible to increase the amount of information that can be transmitted in one cycle of the PN code sequence, and it is possible to achieve an excellent effect that the information transmission rate can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a transmission unit in a first embodiment of a spread spectrum communication system of the present invention.

FIG. 2 is a block diagram showing a configuration example of a receiving unit in the first embodiment of the spread spectrum communication system of the present invention.

FIG. 3 is a block diagram showing a configuration example of a transmission section in a second embodiment of a spread spectrum communication system of the present invention.

FIG. 4 is a block diagram showing a configuration for generating a control signal in a transmission unit according to the second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of an adder circuit in a transmission unit according to a second embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration for converting decoded data into serial data in a receiving unit according to the second embodiment of this invention.

FIG. 7 is a block diagram showing a configuration example of a receiving section in the second embodiment of the spread spectrum communication system of the present invention.

FIG. 8 is a block diagram showing a configuration of a matched filter in a receiving section according to the second embodiment of the present invention.

FIG. 9 is a timing chart of the receiving unit according to the second embodiment of this invention.

FIG. 10 is an example of a more detailed timing chart of the receiving unit according to the second embodiment of the present invention.

FIG. 11 is a chart showing the relationship of the information rate ratio with respect to the number of chips and the number of Q component peaks.

FIG. 12 is a table showing a relationship of information rate ratios when the number of Q component peaks is 4.

FIG. 13 is a block diagram showing a configuration example of a control signal generation unit of a transmission unit of the third embodiment of the spread spectrum communication system of the present invention.

[Fig. 14] Fig. 14 is a block diagram illustrating a configuration example of converting decoded data of a receiving unit of the third embodiment of the spread spectrum communication system of the present invention into serial data.

FIG. 15 is a block diagram showing a configuration of a conventional spread spectrum communication system.

[Explanation of symbols]

1, 2, REG1, REG6, SREG1 to SREG5
Shift register 3, MUX multiplexer 4, switch unit 5, ADD1 adder circuit 6, serial / parallel conversion circuit 10, 12, 13 matched filter 11, 15, 16, THl, TH2, TH3, TH4
Peak detection circuit 17 OR circuit 18 Decoder 21 Judgment circuit 22 Parallel / serial conversion circuit G1 to Gn Gate NOT1 to NOTn Inversion circuit MF1, MF2, MF3 Matched filter D-COUNTER Down counter DEC21, DEC22, DEC8 Decoder E5, E9 Encoder S / P2, S / P8 serial / parallel conversion circuit

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Zhou Asahihira 3-5-18 Kitazawa, Setagaya-ku, Tokyo Takayama Building Co., Ltd. (72) Inventor Nao Takatori 3-5-18 Kitazawa, Setagaya-ku, Tokyo Takayama Building Takayamauchi Co., Ltd.

Claims (6)

[Claims] 1. A spread spectrum communication system in which a first PN code sequence and a second code sequence having the same period as the first PN code sequence are multiplexed and transmitted, wherein the second code sequence is provided. Is generated by adding a predetermined number of basic PN code sequences to which a phase offset is given, and a combination of each phase offset sequence of the predetermined number of basic PN code sequences with respect to the reference phase of the first PN code sequence. A spread spectrum communication method characterized in that transmission information is defined by. 2. The spread spectrum communication system according to claim 1, wherein the polarity of the first PN code sequence is controlled according to the content of a predetermined bit of transmission information. 3. The polarity of each basic PN code sequence forming the second code sequence is controlled according to the contents of a plurality of predetermined bits of transmission information. The spread spectrum communication system according to claim 2. 4. The spread spectrum communication system according to claim 1, wherein the first PN code sequence and the second code sequence are generated by a single PN code generating means. 5. The spread spectrum communication system according to claim 1, wherein the multiplexing is orthogonal multiplexing using QAM modulation. 6. The spread spectrum communication system according to claim 1, wherein the first PN code sequence and the second code sequence are transmitted by carrier waves having different frequencies.