JPH09284124A - Logic module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a field programmable gate array module with flexibility and an excellent space efficiency by selectively revising the configuration so that a sequential function of a D latch or a D flip-flop is executed. SOLUTION: The logic module 400 has interconnected logic elements M1-M6 having a plurality of 2-input multiplexer functions. The multiplexers M1, M5, M6 have one inverting input and the others have two inverting inputs. Data and control signals generated at the outside of the logic module 400 are received by a plurality of input terminals 411-418 and 421-422. An output signal to the outside of the logic module 400 is generated from two output terminals 431-432. Since lots of complicated digital logic functions are generated and the chip area is effectively reduced, number of functions executed by each logic module is advantageously increased.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to electronic circuits, and more particularly, field programmable gate array (FPGA) logic modules that achieve improved performance and silicon area efficiency characteristics, and such modules. To a method of forming.

[0002]

[Prior art and problems] Field programmable
Gate arrays (FPGAs) are integrated circuits that can be configured or programmed by the user to form complex logic circuits. Programming is typically done at the purchaser's location or "on site" after the FPGA is manufactured. FPGAs have many of the advantages of custom integrated circuits, such as having complex functions in one package and low power consumption. FPG
By using A, small quantities of these circuits can be made much cheaper than custom integrated circuits. FPGA
Combines the flexibility of a mask programmable gate array with the convenience of being field programmable.

FPGAs have two main components.
That is, (1) a two-dimensional array of universal logic modules and (2) an array of corresponding programmable interconnects that form selectively programmable connections between the logic modules. The universal logic module consists of a number of functional devices such as diodes, transistors, logic gates, multiplexers, etc. Logic modules are interconnected by selectively programming programmable interconnects to establish a connection between the output of one logic module and the input of another logic module. The programmable interconnect may be a fuse, antifuse or other means. Signals generated external to the FPGA are also connected by antifuses to the inputs of the various logic modules. The output signal from the selected logic module is FPG by antifuse.
It is connected to the output of A. The output of each logic module is a logical combination of the inputs of that logic module and may correspond to digital logic devices such as, for example, NAND gates, AND gates and OR gates. A canonical logic module has roughly eight inputs,
Any one of the hundreds of Boolean algebra combinations of 1-8 input signals can be connected so that they are produced at the output.

FIG. 1 showing the prior art is a typical FPGA.
A portion of 100 is shown. Six logic modules 101 are shown arranged in two rows of three. A typical FPGA array size may be, for example, 12 × 40 or larger. Each logic module has a plurality of inputs 102a-102h and an output 104. Interconnect circuits composed of vertical and horizontal tracks are described in US Pat. No. 5,166,557, entitled "Gate Array with Embedded Programming Circuits", by programming fuses or antifuses. Interconnect the logic modules,
It can be selectively configured. Typically, the horizontal track is divided into smaller segments to allow flexibility in setting up the chosen connection.

Referring further to FIG. 1 showing the prior art, a plurality of external input signals are connected to a plurality of external pins such as pins 116 and are buffered by a receiver such as receiver 118. It is mounted on a horizontal track segment, such as segment 112a. Horizontal segment 112
a can be connected to horizontal segment 114a by programming antifuse 108 to conduct. Other horizontal segments can be interconnected as well. Multiple horizontal track segments 11
One of the 2a-112d is connected to the antifuse 106a.
By programming one of -106d to be conductive, it can be selectively connected to an input of a logic module, such as input 102a. Each logic module 101 has an output, such as output 104, which is connected to a vertical track, such as track 110. Output 1
Reference numeral 04 denotes antifuses 107a-107d and 109.
Segments 112a-112d by respectively programming any of a-109d to conduct.
And a plurality of horizontal segments such as 124a-124d. A plurality of drivers, such as driver 122, are connected to a plurality of output pins, such as pin 120, to drive a plurality of external signals.

FIG. 2 showing the prior art shows an FPGA logic module 101 composed of multiplexers 210, 212, 214, an AND gate 216 and a NOR gate 218. Various combinations of the signals applied to the input terminals 102a-102h can be formed and output on the output terminal 104. For example, 102e and 1
02f, 102e and 102f and 102d, 10
2g Noah 102h, etc., which is well known. Typically, a few hundred logical combinations of input terminals 102a-102h can be formed. An interconnector circuit can be formed by interconnecting the three modules 101.

FIG. 3 showing the prior art shows an FPGA logic module 300 constructed by connecting a logic module 101 of the type shown in FIG. 2 to a logic module 302. The logic module 302 is typically the module 101.
It has a latch and / or flip-flop function that allows a signal that exits to be latched or passed without being latched. Control signals 304a, 304d control what function module 302 performs. As a final result, logic module 300 can be reconfigured to perform various combinatorial logic functions or sequential latch functions.

When a complex logic circuit is constructed using an FPGA, it is typical that one part of the logic circuit needs a combinatorial logic function and another part of the logic circuit is typically a sequential logic. Need functionality. However, if the logic module 300 is used for combinatorial logic functions, then the module 30
2 is virtually unused. Similarly, the logic module 30
If 2 is used for the sequential latch function, then the logic module 101 is substantially unused. For any given purpose,
Since a large number of logic modules may not be usable, FP
GA space may be wasted. In addition, some logic modules 300 may be needed to create commonly used logic functions such as adders, thus providing a logic circuit that can be built on a single FPGA 100 by the user. The maximum dimension is reduced, which is undesirable.

Therefore, the object of the present invention is to provide a predetermined FPG.
A is to create a logic module that consumes less space so that more logic modules can be loaded.

Another object of the present invention is to create a logic module that can perform more logic functions than conventional modules.

Another object of the invention is to create a logic module that can be configured either in combination or in sequential form, thus providing flexibility in the combination of combination and sequential logic in FPGAs. Is.

Other objects and advantages will be apparent to those skilled in the art from the following description of the drawings.

[0013]

According to the present invention,
To perform more than 2,200 Boolean algebra combination functions, to operate as a full adder with sum and carry outputs, or to perform sequential functions of D-type latches or D-type flip-flops. Provides a logic module for a field programmable gate array that can be selectively reconfigured. The logic module has 10 input terminals and 2 output terminals.

Another aspect of the present invention is space utilization efficiency. The logic module consists entirely of two input multiplexers, which can be advantageously used to perform both combinatorial and sequential functions.

Other features and advantages of the present invention will be apparent from the following detailed description of the drawings. Corresponding numerals and symbols used in some figures and tables refer to corresponding parts unless otherwise indicated.

[0016]

DETAILED DESCRIPTION OF THE INVENTION Prior Art FIG. 1 shows a portion of a field programmable gate array (hereinafter referred to as an FPGA), which includes a number of logic modules 101 and interconnect circuitry. Logic module 10
1 is shown in FIG. 2 showing the prior art. The interconnect circuitry is vertical track 110, horizontal track segment 1
It consists of vertical and horizontal tracks such as 06a-106d and 114a-114d. The interconnect circuit can be programmed to selectively interconnect the output terminal 104 of one module 101 with the input terminals 102a-102h of various other logic modules 101. This programming is accomplished by conducting antifuses, such as antifuses 106a-106d, 107a-107d and 108, in response to voltage pulses that program each selected antifuse, as is well known. This invention is intended to enhance the functionality of the FPGA 100 in an advantageous manner, such as FPGA 100
Provides a new logic module that can be used for
Compared to the chip area used in conventional FPGAs,
By advantageously increasing the number of functions that can be performed by each logic module, in order to advantageously reduce the chip area utilized to form the circuitry for performing a large number of desired complex digital logic functions. Functionality is enhanced.

FIG. 4 shows a logic module 400 formed in accordance with the present invention. The logic module 400 is composed of a plurality of logic elements M1 to M6 connected to each other. Each logic element M1-M6 is a 2-input multiplexer. The multiplexers M1, M5, M6 have one inverting input and the rest have two non-inverting inputs. A plurality of input terminals 411-418 and 421-422 receive data and control signals generated external to logic module 400. Two output terminals 431-432 generate output signals for use outside logic module 400.

5A-5C show a two-input multiplexer 500 that is representative of the single inverting input multiplexer shown in FIG. FIG. 5A shows 0-input 510, inverted 1
-Shows input 511, selection control 530 and output 520. FIG. 5B shows a digital logic truth table for multiplexer 500. FIG. 5C shows the configuration of the multiplexer 500. The selection control unit 530 is connected to the inverter 540, the gate of the transistor N1 and the gate of the transistor P2. The output of the inverter 540 is the transistor P1.
And the gates of N2. Inverter 550 inverts the signal connected to inverting 1-input 511. The output 551 of the inverter 550 is connected to one ends of the transistors N1 and P1, and the output 520 of the multiplexer 500 is connected to the other ends of the transistors N1 and P1. Similarly, the signal connected to the 0-input terminal 510 is connected to one ends of the transistors N2 and P2, and the output 520 is connected to the other ends of the transistors N2 and P2. When a low binary signal is applied to the selection controller 530, the multiplexer 500 is configured to provide a binary signal at the output 520 corresponding to the signal applied to the 0-input 510. Similarly,
When a high binary signal is applied to the selection controller 530, the multiplexer 500 will invert 1-input 5 as shown at 5B.
It is arranged to output at output 520 a binary signal corresponding to the inversion of the signal applied to 11.

6A-6C show a multiplexer 600 representative of the multiplexer shown in FIG. 4 with two non-inverting inputs. The operation of multiplexer 600, apart from the inverting of one input of multiplexer 500, is
The operation is the same as that of the multiplexer 500. 6A is 0
-Input 610, 1-input 611, select input 630 and output 620 are shown. FIG. 6B shows a truth table representing the operation of multiplexer 600. FIG. 6C shows a configuration of a multiplexer 600 using four transistors N1, N2, P1 and P2 and an inverter 640.

Returning to FIG. 4, the multiplexer M1 has an inverting 0-input connected to the input terminal 411, a 1-input connected to the input terminal 412, and the multiplexer M1.
4 of the selection control section connected to the output 444, and the output 441 connected to the output terminal 432.

Multiplexer M2 has a 0-input connected to input terminal 416, a 1-input connected to input terminal 417, a selection controller connected to output 446 of multiplexer M6, and an output 442.

The multiplexer M3 is the multiplexer M1.
0-input connected to the output 441 of the multiplexer M
1-input, input terminal 418 connected to output 442 of 2
, And an output 443 connected to the output terminal 431.

The multiplexer M4 is the multiplexer M6.
0-input, multiplexer M connected to output 446 of
1-input, control input terminal 4 connected to output 443 of 3
21 and an output 444.

Multiplexer M5 has a 0-input connected to input terminal 413, an inverted 1-input connected to output 442 of multiplexer M2, a selection controller connected to control input terminal 442, and an output 445.

The multiplexer M6 is the multiplexer M5
0-input, input terminal 41 connected to output 445 of
4 has a 1-input connected to it, a selection controller connected to an input terminal 415, and an output 446.

The control input terminals 421 and 422 have the following four different logical functions, that is, various input terminals 411-4.
18 Boolean algebraic combinatorial logics, full adders with carry outputs, preset and clear inputs, and D-type latches with high or low enable clock, and low and high with preset and clear inputs. Input terminal 411-in that it is used to reconfigure logic module 400 to act as one of the D-type flip-flops having a high or low to high clock triggering action.
418. These functions will be described in more detail below. Typically, the signals applied to the control inputs 421-422 are:
It is fixed at either a logic 0 or a logic 1 and therefore has two antifuses, namely a logic low such as ground, and V _CC.
May require only two antifuses to a logic high such as. However, this is not a requirement of the invention. Reducing the number of antifuses saves space on the integrated circuit and reduces capacitive loading on the affected tracks. Inputs 421-422 are inputs 411-41
It can be handled in the same way as 8. Control input 421-42
If 2 is treated as data input, module 100
The logic functions performed by can be dynamically reconfigured in response to the states of inputs 421-422.

7A-7B show logic module 400 configured as a pure combinatorial block. Control signals S1 and S2 are set to logic 0, and control inputs 421 respectively
And 422. As a result, the multiplexers M4 and M5 form a logic module 400 as shown in FIG. 7B. In FIG. 7B, multiplexer M4
And M5 are not shown, but are still present in practice, to allow the resulting format to be more visible. Multiplexer M4 passes signal 446 to the select input of M1. Multiplexer M
5 passes the signal applied to input terminal 413 to the 0-input of M6. The signal propagation delay introduced by multiplexers M4 and M5 can be minimized by well known suitable design techniques, such as optimizing the width / length ratio of the transistors that make up the multiplexer. As is well known, various input signals A-H are input to the input terminal 411-4.
In addition to 18, various logical combinations of input signals can be generated at outputs 431 and 432.

As shown in Table 1, the present invention allows any one of more than 2,200 combinatorial functions of one to eight inputs 411-418 to be produced at output 431. Advantageously, the use of multiplexers for all logic elements in logic module 400 provides much more logical functionality than was previously possible.

[0029]

[Table 1] FIG. 8A shows logic module 400 configured as a full adder circuit. Control signals S1 and S2 are set to logic 0 and applied to control inputs 421 and 422, respectively. Input signal H is set to a logic one and applied to input 418. Input signal C at input 413 and signal D at input 414 are connected together and represent the first addend X. Second addend Y
Are applied to inputs 415, 417. Carry input signal C
_i is applied to inputs 411, 412, 416. X + Y
The + C _iu sum signal S is generated at output terminal 432 and the carry output signal C _o is generated at output 431.

To better understand the operation of the adder, see FIG.
XOR gates 452, 453 and multiplexer 4 at B
An adder circuit 450 using 51 is shown. If either or both co logic 0 is signal X and Y are both logic 1, a gate 453, the multiplexer 451 as an output signal C _o, 2 of the signal Y is the same state as the signal X
Reproduce the progress state. This follows the behavior of the adder that a carry output occurs when both addends are one. Similarly, if both addends are 0, no carry output occurs. If only one addend X or Y is the number one, the multiplexer 451 reproduces the binary state of the signal C _i as the output signal C _o . This is consistent with the fact that if the carry input C _i is a logical one and one of the addends X or Y is a logical one, it is necessary to generate a carry output C _o equal to a logical one. There is. FIG. 8C shows a truth table for the adder circuit 450. FIG. 8D shows an adder circuit 460 similar to adder circuit 450. The adder circuit 460 is composed of XNOR gates 457 and 458 and a multiplexer 451. Note that signal C _i and signal Y are inverted in multiplexer 451. Adder circuit 460
Generates the same signals S and C _o and the adder circuit 450.
In FIG. 8E, the multiplexer 455 has the XNOR gate 45.
It shows why it is logically equivalent to 6.

With reference to the above, please refer to FIG. 8F. Although this figure shows a circuit that can be a logic module 400 configured as an adder circuit, the multiplexers M3-M5 are not shown for the sake of clarity. The multiplexer M1 corresponds to the gate 457,
The multiplexer M6 corresponds to the gate 458, and the multiplexer M2 corresponds to the multiplexer 451 of FIG. 8D. Therefore, logic module 400, configured as a full adder, produces sum signal S at output 432 and carry output signal C _o at output 431 according to the truth table shown in FIG. 8C.

FIG. 9A shows logic module 400 configured as a D-type latch circuit. The control signal S1 is set to logic 1 and applied to the input terminal 421. Control signal S2
Are set to logic 0 and applied to input 422. Input signal C is set to logic 0 and applied to input terminal 413. Input signals D and E are set to logic 1 and input terminal 4
14-415. Input signal CE, S1-S
With such a selection of 2, multiplexers M2 and M4
-M6 configures module 400 as a D-type latch. The logic module 400 is shown in FIG. 9C. The multiplexers M2 and M4-M6 are not shown, but are actually present and are not shown in order to make the resulting form more visible.

To better understand the operation of the D-type latch,
See FIG. 9B showing a simple D-type latch 460 made up of multiplexer 461 and multiplexer 462. Signal 463 provides a feedback path that feeds the output of multiplexer 461 to the 0-input of multiplexer 462. When the clock signal CLK is high, the data signal DATA is enabled and the multiplexer 462 is
Through, which is represented as signal X connected to the select input of multiplexer 461. The signal 463 of the multiplexer 461, which is also called the signal Q, can be expressed in Boolean algebra as follows.

[0034]

## EQU1 ## Q = ((PRE) AND (X /)) OR ((C
LR /) AND (X)) Here, the symbol “/” means “inversion” or “negation”. Thus, when signals PRE and CLR are both logic zero, output signal Q = signal X. Clock signal CLK
Goes low, the feedback signal 463 is selected from the 0-input of multiplexer 462 and the state of signal DATA is latched in D-type latch 460.

When the preset signal PRE is set to a logic one, the output signal Q and the feedback signal 463 are also a logic one and the D-type latch 460 is "set" to a logic one state.
Is done. Similarly, when the clear signal CLR is set to a logic one, the output signal Q and the feedback signal 463 will be a logic zero and the D-type latch 460 will be "cleared" to a logic zero state.
Is done.

The D-type latch circuit made up of module 400 and shown in FIG. 9C operates similarly to latch 460 of FIG. 9B. The data signal DATA is applied to the input terminal 417. The clock signal CLK / is applied to the input terminal 418. The inverted preset signal PRE / is applied to the terminal 411, and the inverted clear signal CLR / is applied to the terminal 412. The multiplexer M3 outputs the signal CLK at the terminal 418.
When / is a logic one, it passes the state of signal DATA to multiplexer M1. The multiplexer M1 receives the signal C
If LR and PRE are both logic 0, signal DATA
The state of is reproduced in the output 441. The output 441 is fed back to the 0-input of the multiplexer M3. Therefore, when the signal CLK / at the terminal 448 becomes a logic 0, the state of the signal DATA is latched in the D-type latch formed by the logic module 400, and the output terminal 432 becomes the signal DAT.
Generate a signal Q representing the latched state of A. The output terminal 431 also produces a signal 441 which roughly corresponds to the signal Q.

Referring to FIG. 9D, multiplexers M2 and M5-M6 may be advantageously used to form the combinatorial function of inputs 413-417 prior to latching. This is accomplished by using some or all of the signals C-G as logic signals.

FIG. 10A shows logic module 400 configured as a D flip-flop. Control signal S1
Is set to logic 1 and applied to input terminal 421.
Control signal S2 is set to a logic one and applied to input 422. By selecting the input signals S1-S2 in this way, the multiplexers M4-M5 allow the modules 4
00 is configured as a D-type flip-flop. FIG.
D does not show multiplexer M4, but logic module 40 shows multiplexer M5 as an inverter.
Indicates 0. Not shown is to make the resulting configuration easier to see and is actually present.

To better understand the operation of the D-type flip-flop, please refer to FIG. 10B, which shows a D-type flip-flop 470 composed of D-type latches 471 and 472. D-type latch 47 operating at high clock signal CLK
Connected to 1. Data signal DATA is connected to latch 471 and appears at output DATA1 when signal CLK is high. The inverted signal CLK / is also connected to a high acting D-type latch 472. When signal CLK is a logic high, signal CLK / is a logic low and vice versa. Therefore, when the signal CLK changes from a logic high to a logic low, the binary state of the signal DATA is latched in the latch 471, at which time the latch 472 transfers the state of the latched signal DATA1 to the output Q. This order is called "triggering" the flip-flop on the "negative edge". The preset signal PRE sets the state of the flip-flop 470 to a logic one, as represented by the output Q when the signal PRE is a logic high, and when the signal CLR is a logic high,
The clear signal CLR clears the state of the flip-flop 470 to logic zero.

FIG. 10C shows a simple D-shaped latch 481,4.
Two multiplexers 481, 4 also acting as 82
A simple D-type flip-flop 480 configured at 82 is shown. The clock signal CLK is applied to the multiplexer 482, and the inverted clock signal CLK / is applied to the multiplexer 4
81 is applied. Flip-flop 480 operates similarly to flip-flop 470, except that it does not have preset and clear functions. Flip-flop 480 illustrates the operation of the flip-flop when signal CLK / is applied to first D-type latch 481 and CLK is applied to second D-type latch 482. In this case, the flip-flop is triggered by the low-to-high transition of the signal CLK, which is called the positive edge triggering action.

The D-type flip-flop circuit configured in module 400 and shown in FIG. 10D operates similarly to flip-flop 470 of FIG. 10B. Data signal DAT
A is applied to the input terminal 414. Clock signal CLK
Is applied to the input terminal 415. Inverted clock signal CL
K / is applied to input terminal 418. Preset signal P
RE is applied to the terminal 416 and the inverted preset signal PR
E / is applied to input 411. Inversion clear signal CLR
/ Is applied to terminals 412 and 417. Multiplexers M6 and M2 act as a D-type latch as previously described, with multiplexer M5 providing a feedback action, and act as a first D-type latch similar to latch 471. Multiplexers M1 and M2 act as a second D-type latch similar to latch 472. Clock signal C
LK is applied to multiplexer M6. The inverted clock signal CLK / is applied to the multiplexer M3. Signal 443 is output via output terminal 431 as signal Q, which represents the state of the D flip-flop of module 400.

Returning to FIG. 10D, the D-type flip-flop of the module 400 uses the clock signal CLK.
Is advantageously triggered when changes from high to low or from low to high. This feature is the signal CLK and CLK
It is realized by connecting / in different orders. Signal CLK is connected to input 415 and CLK / is input 41
When connected to 8, the D-type flip-flop of module 400 acts as a negative edge triggered flip-flop. That is, the input signal DATA passes through and outputs the output signal Q when the clock signal CLK changes from high to low.
become. Similarly, signal CLK is connected to input 418,
When CLK / is connected to input 415, module 40
The 0 D flip-flop acts as a positive edge triggered flip-flop, passing the signal DATA to the output Q when the signal CLK changes from low to high.

FIG. 11D illustrates a core logic module 703 that can be modified in several ways to result in an inductive module constructed in accordance with the present invention.

The multiplexer M71 has the input terminal 415
0-input connected to, 1 connected to input terminal 416
It has an input, a selection control connected to the output 752 of the gate G2, and an output 741.

The multiplexer M72 has the input terminal 411.
Has a 0-input connected to the input terminal 412, an inverting 1-input connected to the input terminal 412, a selection control unit connected to the output 752 of the gate G2, and an output 742 connected to the output terminal 432.

The multiplexer M73 has a 0-input connected to the output 742 of the multiplexer M72, a 1-input connected to the output 741 of the multiplexer M71, a selection control unit connected to the output 751 of the gate G1, and the output terminal 431. Has an output 743 connected to.

NOR gate G1 has a first input connected to input terminal 417 and a second input connected to input terminal 418.
Input and output 751.

XOR gate G2 has a first input connected to input terminal 413 and a second input connected to input terminal 414.
Input and output 752.

Still referring to FIG. 11D, logic module 703 can be reconfigured to form pure combinatorial logic circuits and full adder circuits, as shown in Table 2. As shown in Table 3, any one of the 1364 combinatorial functions of the input terminals can be formed at output 431.

[0050]

[Table 2]

[0051]

[Table 3] FIG. 11A shows a logic module 700 constructed in accordance with the present invention. The multiplexer M74 functions as a feedback function for the multiplexer M71, and the multiplexer M75 functions as a feedback function for the multiplexer M73.

The multiplexer M71 has the input terminal 415
0-input connected to, output 7 of multiplexer M74
It has a 1-input connected to 44, a selection control connected to the output 752 of the gate G2, and an output 741.

The multiplexer M72 has the input terminal 411
Has a 0-input connected to the input terminal 412, an inverting 1-input connected to the input terminal 412, a selection control unit connected to the output 752 of the gate G2, and an output 742 connected to the output terminal 432.

The multiplexer M73 has a 0-input connected to the output 745 of the multiplexer M75, a 1-input connected to the output 741 of the multiplexer M71, a selection control unit connected to the output 751 of the gate G1, and the output terminal 431. Has an output 743 connected to.

The multiplexer M74 has an input terminal 416
0-input connected to, output 7 of multiplexer M71
It has a 1-input connected to 41, a selection control connected to a control input 421, and an output 744.

Multiplexer M75 has a 0-input, output 743 connected to output 742 of multiplexer M72.
Has a 1-input connected to the control input 421, a selection control connected to the control input 421, and an output 745.

NOR gate G1 has a first input connected to input terminal 417, a second input connected to input terminal 418, and an output 751.

The XOR gate G2 has a first input connected to the input terminal 413 and a second input connected to the input terminal 414.
Input and output 752.

Referring further to FIG. 11A, logic module 700 uses control input signal S1 as shown in Table 4.
In response to, can be reconfigured to form any one of a pure combinational logic circuit, a full adder, a D-type latch and a D-type flip-flop.

[0060]

[Table 4] FIG. 11B shows a logic module 701 constructed in accordance with the present invention. The multiplexer M74 functions as a feedback function for the multiplexer M72, and the multiplexer M75 functions as a feedback function for the multiplexer M73.

The multiplexer M71 has the input terminal 415
0-input connected to, 1 connected to input terminal 416
It has an input, a selection control connected to the output 752 of the gate G2, and an output 741.

The multiplexer M72 has the input terminal 411
0-input connected to, output 7 of multiplexer M74
Inverting 1-input connected to 44, output 75 of gate G2
2 has a selection controller connected to the output terminal 432 and an output 742 connected to the output terminal 432.

The multiplexer M73 has a 0-input connected to the output 745 of the multiplexer M75, a 1-input connected to the output 741 of the multiplexer M71, a selection controller connected to the output 751 of the gate G1, and the output terminal 431. Has an output 743 connected to.

The multiplexer M74 has an input terminal 412.
0-input connected to, output 7 of multiplexer M72
It has an inverting 1-input connected to 42, a selection control connected to control input 421, and an output 744.

Multiplexer M75 has 0-input, output 743 connected to output 742 of multiplexer M72.
Has a 1-input connected to the control input 421, a selection control connected to the control input 421, and an output 745.

NOR gate G1 has a first input connected to input terminal 417, a second input connected to input terminal 418, and an output 751.

XOR gate G2 has a first input connected to input terminal 413, a second input connected to input terminal 414, and an output 752.

Still referring to FIG. 11B, logic module 701 is responsive to control input signal S1 to provide pure combinational logic circuits, full adders, D-type latches and D-type flip-flops, as shown in Table 5. Can be reconfigured to form any one of

[0069]

[Table 5] FIG. 11C shows a logic module 702 constructed in accordance with the present invention. The multiplexer M74 functions as a feedback function for the multiplexer M71, and the multiplexer M75 functions as a feedback function for the multiplexer M73. Multiplexer M76 controls the select input of multiplexer M71.

The multiplexer M71 has the input terminal 415
0-input connected to, output 7 of multiplexer M74
It has a 1-input connected to 44, a selection control connected to the output 746 of the multiplexer M76, and an output 741.

The multiplexer M72 has the input terminal 411
Has a 0-input connected to the input terminal 412, an inverting 1-input connected to the input terminal 412, a selection control unit connected to the output 752 of the gate G2, and an output 742 connected to the output terminal 432.

The multiplexer M73 has a 0-input connected to the output 745 of the multiplexer M75, a 1-input connected to the output 741 of the multiplexer M71, a selection control unit connected to the output 751 of the gate G1, and the output terminal 431. Has an output 743 connected to.

The multiplexer M74 has the input terminal 416
0-input connected to, output 7 of multiplexer M71
It has a 1-input connected to 41, a selection control connected to a control input 421, and an output 744.

Multiplexer M75 has a 0-input connected to output 742 of multiplexer M72, a 1-input connected to output 743 of multiplexer M73, a selection controller connected to control input 421, and an output 745.

Multiplexer M76 receives 0-input connected to output 752 of gate G2, output 75 of gate G1.
It has an inverting 1-input connected to 1, a selection control connected to control input 421, and an output 746.

NOR gate G1 has a first input connected to input terminal 417 and a second input connected to input terminal 418.
Input and output 751.

XOR gate G2 has a first input connected to input terminal 413, a second input connected to input terminal 414, and an output 752.

Still referring to FIG. 11C, logic module 702 responds to control input signal S1 as shown in Table 6 by combining pure combinational logic circuits, full adders, D-type latches and D-type flip-flops. Can be reconfigured to be any one of

[0079]

[Table 6] We have shown that logic modules advantageously provide a rich set of combinatorial functions with full adders. The availability of full adder circuits in the logic module aids in the easy assembly of adders, subtractors and multipliers. The logic module is well suited for digital signal processing applications.

The advantage of this logic module is that the dimensions of the module are minimized by reconfiguring the logic elements to perform both combinatorial and sequential functions. Furthermore, instead of interconnecting two or more conventional modules, by configuring the sequential functions of latches and D flip-flops within the modules, the output signal propagation delay is advantageously reduced.

A shift register can be efficiently formed by using a plurality of logic modules configured as D-type latches or D-type flip-flops.

The preset and clear functions of the D-latch and D-flip of module 400 are advantageous in many applications of the module.

The combined function for signal DATA when the module is configured to be a D-type latch may be advantageous in many applications. Another advantage of modules is that
There is flexibility in configuring the D-type flip-flop to be positively or negatively triggered.

Another advantage of the logic module is that inputs S1 and S2 are selected as control inputs. By limiting its usage to high or low after programming, only two antifuses are required for each of the inputs S1 and S2. In addition, multiple modules
Connect inputs S1 and S2 together in one FPGA,
In order to configure a plurality of modules, it is possible to require only two antifuses for each control line, which advantageously reduces the total number of antifuses in the FPGA and its effect. The capacitive load on the received signal can be advantageously reduced.

The terms "application" and "connection" in this specification mean that they are electrically connected, including the case where another element is contained in the electric connection passage.

Although the present invention has been described with reference to embodiments, this description should not be construed as limiting the invention.
From the above description, those skilled in the art will easily think of other various embodiments of the present invention. Therefore, it is to be understood that the appended claims are intended to cover all such modifications of the embodiments that fall within the scope of this invention.

(1) In the logic module used in the field programmable gate array integrated circuit,
A plurality of input terminals, a plurality of output terminals, a plurality of logic elements, and an interconnection circuit interconnecting the input terminals, the logic elements and the output terminals, wherein the logic elements have certain input terminals A logic module that is configurable to form a preselected type of sequential and combinational logic functions in response to a predetermined combination of control signals applied to the.

(2) The logic module of claim 1, wherein the interconnection circuit and the logic element form a Boolean combinational circuit in response to a first combination of control signals.
The interconnection circuit and the logic element form a full adder circuit in response to a second combination of control signals, and the interconnection circuit and the logic element are D-shaped in response to a third combination of control signals. A logic module forming a latch circuit, the interconnection circuit and the logic element forming a D-type flip-flop circuit in response to a fourth combination of control signals.

(3) The logic module according to claim 1, wherein each logic element has a multiplexer having first and second inputs, a selection controller and an output.

(4) The logic module of claim 1, wherein the interconnection circuit and the logic element are responsive to a first combination of control signals to provide at least one Boolean combination of other input terminals. Forming at the output terminal, the interconnection circuit and the logic element forming at one output terminal the arithmetic sum of some other input terminals in response to the second combination of control signals. Forming a carry at the second one output terminal, the interconnection circuit and the logic element comprising:
In response to the third combination of control signals, a D-type latch is formed which is responsive to the logic levels of the clock signal and the inverted clock signal at the two other input terminals.
Sequentially latching an indication of a signal at one input terminal and placing the resulting latched signal on the one output terminal, the interconnection circuit and the logic element comprising a fourth combination of control signals. To form a D-type flip-flop, the D-type flip-flop being responsive to a logic change of a clock signal and an inverted clock signal at another two input terminals, the signal at a certain one input terminal. A logic module that sequentially latches the display of, and places the resulting latched signal on one output terminal.

(5) The logic module according to claim 1, 2 or 3, wherein a plurality of the logic modules are interconnected with a second interconnection circuit to selectively interconnect the logic modules. Logic module.

(6) In the logic module according to claim 3, the interconnection circuit and the logic element further include 1
Inverting 0-input connected to the second input terminal, 1-input connected to the second input terminal, a selection control unit connected to the output of the fourth multiplexer, and an output connected to one output terminal , A 0-input connected to the sixth input terminal, a 1-input connected to the seventh input terminal, a selection controller connected to the output of the sixth multiplexer, and an output A second multiplexer having a 0 and a 0 connected to the output of the first multiplexer.
An input, a 1-input connected to the output of the second multiplexer, a selection controller connected to the eighth input terminal,
And a third multiplexer having an output connected to another output terminal, a 0-input connected to the output of the sixth multiplexer, a 1-input connected to the output of said third multiplexer, a control input terminal A selection multiplexer connected first to one of the selected input terminals and a fourth multiplexer having an output, and a 0-input connected to a third input terminal of the second multiplexer. A fifth multiplexer having an inverting 1-input connected to the output, a selection controller connected second to one of the input terminals selected as the control input terminal, and an output; A logic module comprising: an inverting 0-input connected to an output, a 1-input connected to a fourth input terminal, a selection controller connected to a fifth input terminal, and a sixth multiplexer having an output.

(7) In the logic module according to claim 1, the interconnection circuit and the logic element further include 5 elements.
A 0-input connected to the th input terminal, a 1-input connected to the output of the fourth multiplexer, a selection control connected to the output of the exclusive-OR gate, and a first having an output
Multiplexer and 0 connected to the first input terminal
-Input, inverting 1-input connected to the second input terminal,
A selection control connected to the output of the exclusive OR gate, and a second having an output connected to the second output terminal
, A 0-input connected to the output of the fifth multiplexer, a 1-input connected to the output of the first multiplexer, a selection control connected to the output of the NOR gate, and a first A third multiplexer having an output connected to the output terminal, a 0-input connected to the sixth input terminal, a 1-input connected to the output of the first multiplexer, and a control input terminal are selected. A fourth multiplexer having a selection controller connected to one input terminal and an output; a 0-input connected to the output of the second multiplexer; connected to the output of the third multiplexer 1-input, a selection control unit connected to the control input terminal, and a fifth multiplexer having an output, the NOR gate having a first input connected to a seventh input terminal Eighth connected to an input terminal of the the second
Has an input and an output of
A logic module having a first input connected to a third input terminal and a second input and output connected to a fourth input terminal.

(8) In the logic module according to claim 1, the interconnection circuit and the logic element further include 5
A first multiplexer having a 0-input connected to the th input terminal, a 1-input connected to the sixth input terminal, a selection control connected to the output of the exclusive-OR gate, and an output; 0-input connected to the first input terminal, inverting 1-input connected to the output of the fourth multiplexer,
A selection control connected to the output of the exclusive OR gate, and a second having an output connected to the second output terminal
, A 0-input connected to the output of the fifth multiplexer, a 1-input connected to the output of the first multiplexer, a selection control connected to the output of the NOR gate, and a first A third multiplexer having an output connected to the output terminal, a 0-input connected to the second input terminal, an inverting 1-input connected to the output of the second multiplexer, and a control input terminal are selected. A selection control unit connected to a certain one input terminal, and a fourth multiplexer having an output, a 0-input connected to the output of the second multiplexer, and an output of the third multiplexer. 1-input, a selection controller connected to the control input terminal, and a fifth multiplexer having an output, the NOR gate having a first input connected to a seventh input terminal. Force, a second input connected to the eighth input terminal, and an output, the exclusive OR gate being connected to the first input connected to the third input terminal and the fourth input terminal. A logic module having a second input and an output that are made available.

(9) In the logic module according to claim 1, the interconnection circuit and the logic element further include:
A first multiplexer having a 0-input connected to a th input terminal, a 1-input connected to an output of a fourth multiplexer, a selection control unit connected to an output of a sixth multiplexer, and a first multiplexer having an output; 0-input connected to the first input terminal, inverting 1-input connected to the second input terminal, selection control connected to the output of the exclusive OR gate, and connected to the second output terminal A second with a rendered output
, A 0-input connected to the output of the fifth multiplexer, a 1-input connected to the output of the first multiplexer, a selection control connected to the output of the NOR gate, and a first A third multiplexer having an output connected to the output terminal, a 0-input connected to the sixth input terminal, a 1-input connected to the output of the first multiplexer, and a control input terminal are selected. A fourth multiplexer having a selection controller connected to one input terminal and an output; a 0-input connected to the output of the second multiplexer; connected to the output of the third multiplexer A fifth multiplexer having a 1-input, a selection control connected to the control input terminal, and an output, and a 0-input connected to the output of the exclusive OR gate, the NOR gate 1-input connected to the output of the first input, a selection controller connected to the first control input terminal, and a sixth multiplexer having an output, the NOR gate connected to the seventh input terminal. The exclusive OR gate has a first input connected to the eighth input terminal, a second input connected to the eighth input terminal, and an output, and the exclusive OR gate has a first input connected to the third input terminal, 4 A logic module having a second input and output connected to the second input terminal.

(10) Field programmable
A logic module 100, such as that shown in FIG. 4, for use in a gate array 100, has a full adder with sum and carry outputs at its output 431 to perform the combined function of more than 2,200 Boolean algebras. Can be selectively reconfigured to operate as or as to perform the sequential function of a D-type latch or D-type flip-flop. Logic module 100 consists of a two-input multiplexer, which is used to form both combinatorial and sequential circuits, thus efficiently utilizing space on gate array 100.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a conventional FPGA showing logic modules and interconnect circuits.

2 is a circuit diagram of a conventional logic module showing logic elements within the logic module of FIG.

FIG. 3 is a circuit diagram of a conventional logic module showing the alternative logic module of FIG. 1 having both a combining portion and a separate sequential portion.

FIG. 4 is a circuit diagram of a logic module formed in accordance with the present invention.

5 is a diagram showing the configuration and operation of an inverting input multiplexer used in FIG.

FIG. 6 is a diagram showing the configuration and operation of the non-inverting multiplexer used in FIG.

7 is a circuit diagram of the logic module of FIG. 4 configured as a pure combination block.

FIG. 8 shows the logic module of FIG. 4 configured as a full adder circuit.

9 is a diagram showing the logic module of FIG. 4 configured as a D-type latch circuit.

FIG. 10 shows the logic module of FIG. 4 configured as a D flip-flop circuit.

FIG. 11 is a circuit diagram of another embodiment logic module formed in accordance with the present invention.

[Explanation of symbols]

 411-422 input terminal 431-432 output terminal M1-M6 logic element (multiplexer) 441-446 output

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Manisha Aguawara, Fox Creek Drive, Richardson, Texas, USA 2508 (72) Inventor Mark Gregory Howard, Winchester Drive, Dallas, Texas, USA 7031 (72) Inventor, Robert James Landers 3228 Cross Bend, Plano, Texas, United States

Claims (1)

[Claims] 1. A field programmable gate
In a logic module used in an array integrated circuit, a plurality of input terminals, a plurality of output terminals, a plurality of logic elements, and an interconnection circuit interconnecting the input terminals, the logic elements and the output terminals are provided. A logic module, the logic element being configurable to form a preselected type of sequential and combinational logic functions in response to a predetermined combination of control signals applied to an input terminal.