JPH09284057A - Unbalanced fet mixer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the high frequency mixer requiring a low local oscillator drive level and having a high tertiary intercept. SOLUTION: An Lo signal is given to a gate G of a transistor(TR) 12 of a mixer 10 from a port 16 via a reactance 28. An RF signal is given to a drain of the TR 12 via a diplexer 22 from a port 18 and an IF signal is outputted from a port 20 of the diplexer 22. Moreover, a separate reactance 32 is connected between a gate and a drain of the TR 12, the inductive component and an capacitance of the TR 12 (Cgd) form a separation resonator to prevent a command to the gate G of the RF signal, and a capacitive component in the separator reactance 32 provide a required low frequency separation between an IF signal port 20 and the gate G. Furthermore, a matching element 24 and a clamp 30 are connected between an Lo input port 16 and a point of VREF.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates generally to high frequency mixers, and more particularly to mixers that require low local oscillator drive levels and have high third order intercepts.

[0002]

2. Description of the Prior Art The dynamic range of many known microwave front ends is controlled by the mixer's single and two-tone intermodulation levels. A typical high performance mixer obtains a third order intercept point that is approximately equal to the local oscillator (LO) power-conversion loss +10 dB. Even in many complex devices that try to improve isolation, bandwidth, and single-tone intermodulation levels, it is inevitable to compromise between LO power levels and third-order intercept and 1 dB compression points.

It has been shown that low distortion mixing is possible even at moderate LO power levels when the channel of a field effect transistor (FET) contains a mixing element. (1987 IEEE MTT-S Dige
Stefan A. Mas, “GaAs ME with very low intermodulation,” published on page 895-986 of st.
SFET balanced mixer (A GaAs MESFET Balanced Mixer
With Very Low Intermodulation) ". )
Recently, a relatively wide frequency range (for example, 2-8GH)
Both "single-balanced" and "double-balanced" FET mixers operating over z) have been designed. The characteristic of the mixer as "single balanced" is that the balun circuit is connected to one of the mixer's ports (eg the LO port), while the "double balanced" mixer has three ports. There are two balun circuits. Balun circuits advantageously improve the isolation between the Miku supports, but are often implemented as separate pieces of bulky coiled wire.
When implemented as an integrated circuit, balun circuits tend to require a large wafer area, thus undesirably increasing cost and circuit size.

[0004]

The dynamic range of existing FET mixers is based on both the DC operating characteristics of the FET devices contained therein and the LO drive level. Conventional DC bias techniques, including those involving the application of an externally supplied DC gate voltage, required significant LO drive levels in applications requiring large dynamic range. This generally requires the inclusion of relatively high power RF amplifiers in the "pumping" circuit used to generate the LO drive signal, often increasing the cost and complexity of the circuit. Therefore, there is interest in reducing the LO drive level that needs to be provided to the FET mixer.

Therefore, it is an object of the present invention to produce a high frequency mixer that does not rely on a balun circuit to obtain a high third order intercept.

Yet another object of the present invention is to produce a high frequency mixer that operates at low LO drive levels over a wide dynamic range.

Yet another object of the present invention is to produce a high frequency mixer that can operate in the absence of DC bias.

[0008]

SUMMARY OF THE INVENTION Briefly stated, the present invention provides an unbalanced mixer that can operate in the absence of DC bias. The mixer includes an input port or local oscillator (LO) port for receiving an input signal.
The first transistor has a control terminal connected to the input port of the mixer and an output terminal connected to the first signal port of the mixer. Further, the mixer is provided with a resonance circuit connected between the control terminal and the signal terminal of the transistor and for providing signal isolation between the LO port and the signal port of the mixer. In a preferred embodiment, the resonant circuit comprises an inductive element in parallel with the first intrinsic capacitance of the transistor.

Further, the mixer couples the signal energy of the first frequency between the output terminal and the first signal port and the signal energy of the second frequency between the output terminal and the second signal port. It also has a diplexer circuit. There is also provided a series resonant circuit connected between the input or LO port and the control terminal of the transistor to amplify the input signal. In a preferred embodiment, this series resonant circuit comprises an input inductive element and the input intrinsic capacitance of the first transistor.

An advantage of the present invention is that the isolation of LO ports from other mixer signal ports is achieved without the use of balun circuits.

Another advantage of the present invention is that the mixer can operate in the absence of DE bias.

Yet another advantage of the present invention is that the resonant circuit improves the third order intercept point by preventing signal energy from being connected from the mixer signal port connected to the output port of the transistor to the control terminal of the transistor. It is to be.

Yet another advantage of the present invention is the reduced LO.
Operation over a wide dynamic range at the drive level is to be demonstrated.

These and other objects and advantages of the present invention are
It will be apparent to those skilled in the art from the following detailed description of the preferred embodiments with reference to the accompanying drawings.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows an unbalanced mixer 1 according to the present invention.
FIG. 3 is a block diagram showing a preferred embodiment of No. 0. The mixer 10 comprises a transistor 12, which in the illustrated embodiment is a field effect transistor (FET) having a control or gate (G) terminal, a drain (D) terminal, and a source (S) terminal. Is carried out. The mixer 10 also includes an LO input port 16 to which a local oscillator (LO) input signal is applied and high frequency (RF) and intermediate frequency (IF) signal ports 18 and 20. The diplexer 22 interposed between the drain (D) and the signal ports 18, 20 serves to couple the signal energy between these ports and the drain (D). Mixer 10
When operating as a frequency upconverter, the input signal is applied to the LO and IF ports 16 and 20, and the output signal is connected from the RF signal port 18. When operating as a frequency down converter, the input signal is applied to the LO and RF ports 16 and 18 and the output signal is taken from the IF signal port 20.

In the illustrated embodiment, the LO input port 16 receives the LO input signal via a 50Ω transmission line (not shown), so the reactance of the matching element 24 also causes the impedance to the LO port 16 to be 50.
It is selected to ensure that it is Ω. As shown in FIG. 1, the LO input signal is connected to the FET 12 via the series reactance 28. According to one feature of the invention, the input LO signal is generated by a series resonator composed of (i) an inductive element in series reactance 28 and (ii) the intrinsic gate / source capacitance (C _gs ) of FET 12. Is amplified. This series resonator becomes resonant at the frequency of the LO input signal, thus reducing the required magnitude of the LO input signal. Clamp circuit 30
Clamps the gate voltage below the reference potential V _REF by approximately one diode drop to prevent the negative half cycle of the amplified LO input signal from causing reverse breakdown at the gate (G) of the transistor. To do.

Furthermore, the mixer 10 also comprises a separate reactance 32 connected between the gate (G) and the drain (D) of the transistor 12. According to one feature of the invention, the inductive component of the isolation reactance 32 and the intrinsic gate / drain capacitance (C _gd ) of the transistor 12 form a “isolation resonator”, which is the gate of the transistor ( G) is effectively decoupled from the drain (D) at the RF signal frequency. In particular, the isolated resonator approximates an open circuit at the frequency of the signal energy imposed on the RF output port 18 by the drain (D) via the diplexer 22. Furthermore, the separation reactance 3
The capacitive component in 2 provides the necessary low frequency isolation between the IF signal port 20 and the transistor gate (G).
In this way, the isolation reactance 32 allows the LO port 16 to be isolated from the RF port 18 without the use of a balun circuit, thereby effectively implementing the mixer 10 as an integrated circuit. The isolation resonator also prevents the RF and IF signal energies from being coupled to the gate (G) of the FET 12 and affecting its conductance due to the resulting reverse isolation, thus obtaining a preferred third order intercept point. To be able to

FIG. 2 is a schematic diagram of a preferred embodiment of the unbalanced mixer 100 of the present invention. As shown in FIG. 2, the diplexer 22 includes capacitors C4 and C5,
And an inductor L3. Inductor L3 serves to prevent high frequency RF signal energy from coupling from the transistor drain (D) to the IF signal port 20. In the embodiment of FIG. 2, it is clear that the isolation reactance 32 is composed of the inductor L1 in series with the capacitor C3. The inductor L1 is F
In parallel with the intrinsic capacitance C _gd of the ET12,
Form an isolated resonator. The value of L1 is selected so that the isolation resonator is in resonance at the frequency of the RF signal energy coupled from the drain (D) of FET 12 to RF port 18. The capacitor C3 is connected to the IF port 20.
And provides a separation between the relatively low frequency signals appearing at the gate (G) of the FET 12.

It is clear that the series reactance 28 of the gate (G) of the FET 12 is composed of the inductor L2 in series with the capacitor C2. The inductor L2 is F
In series with the intrinsic capacitance C _gs of the ET12,
It directly forms a resonator, which is designed to amplify the LO input signal applied to the LO input port 16. This is the L required to obtain a given level of RF output power when the mixer is configured as a frequency upconverter.
Effectively reduces the magnitude of the O input signal. When the mixer is configured as a frequency downconverter, the series resonator increases efficiency by reducing the LO power level required to obtain the desired IF output power. Since no DC bias current is supplied to transistor 12, the channel of transistor 12 is controlled only by the amplified LO input signal applied to the transistor gate (G). The lack of DC bias is due to transistor 12
Is allowed by the capacitor C2, which serves to self-bias

Capacitor C1 is a DC blocking capacitor and prevents the DC offset at LO input port 16 from reaching the transistor gate (G). In addition, the capacitor C1 is connected to the clamping circuit 30.
To get self-bias.

As stated above, reverse breakdown at the gate of FET 12 is prevented by clamp circuit 30. In the embodiment of FIG. 2, the clamp circuit 30 is
It is composed of a diode-connected FET 104. In operation, the FET 104 looks like a reverse biased diode during the positive half cycle of the LO signal applied to the LO port 16. The magnitude of the negative half cycle of the LO signal is approximately one diode voltage drop (eg 0.7V).
Is exceeded, the diode-connected transistor 104 is forward-biased, and thus the applied L
Clamp the O input signal level. In the illustrated embodiment, the impedance to LO port 16 is approximately 50
It has been found that the matching element 24 must exhibit an inductive reactance in order to achieve Ω. Therefore,
In the embodiment of FIG. 2, the matching element 24 comprises an inductor L4.

FIG. 3 is a circuit diagram of another embodiment of the unbalanced mixer of the present invention. The mixers of FIGS. 2 and 3 are substantially similar, but the clamping circuit in the mixer of FIG. 3 is implemented using a parallel chain of diodes connected in series. In particular, the clamp circuit of FIG. 3 comprises a first set of series-connected diodes D1-D3 and a second set of series-connected diodes D4-D6 connected in parallel thereto. FIG.
Shows a particular embodiment of the mixer of FIG. 3, in which the diodes D1-D6 are implemented with diode-connected field effect transistors T1-T6.

Although the present invention has been described with reference to presently preferred embodiments, it is to be understood that the invention is not limited thereto. Various changes and modifications will be apparent to those skilled in the art in view of the above disclosure. It is therefore intended to cover in the appended claims all changes and modifications that are within the true spirit and scope of this invention.

[Brief description of drawings]

FIG. 1 is a block diagram of a preferred embodiment of the unbalanced mixer of the present invention.

FIG. 2 is a circuit diagram of a preferred embodiment of the unbalanced mixer of the present invention.

FIG. 3 is a circuit diagram of another embodiment of the unbalanced mixer of the present invention.

4 is a diagram showing a particular aspect of the mixer of FIG. 3 in which the diodes that make up the clamp circuit are implemented using diode-connected field effect transistors.

[Explanation of symbols]

 10 Unbalanced Mixer 12 Transistor 16 Local Oscillator (LO) Input Port 18 High Frequency (RF) Signal Port 20 Intermediate Frequency (IF) Signal Port 22 Diplexer 24 Matching Element 28 Series Reactance 30 Clamp Circuit 32 Isolation Reactance

Claims (15)

[Claims] 1. A first transistor having an input port for receiving an input signal, a control terminal connected to the input port, and an output terminal connected to the first signal port, the control terminal and the output terminal. A resonance circuit connected between the input port and the first signal port, the resonance circuit being provided between the input port and the first signal port. 2. Combining signal energy of a first frequency between the output terminal and the first signal port,
The mixer of claim 1, further comprising a diplexer circuit for coupling signal energy at a second frequency between the output terminal and the second signal port. 3. The mixer of claim 1, wherein the resonant circuit comprises an inductive element in parallel with the first intrinsic capacitance of the transistor. 4. The mixer of claim 1, further comprising a series resonant circuit connected to the input terminal, the series resonant circuit including an input inductive element and an input intrinsic capacitance of the first transistor. 5. The mixer of claim 3, further comprising a series resonant circuit connected to the input terminal, the series resonant circuit including an input inductive element and an input intrinsic capacitance of the first transistor. 6. A reverse breakdown prevention circuit connected to the input port of the mixer for preventing the input signal from causing a reverse breakdown at the input terminal of the first transistor. The mixer according to 1. 7. Reverse breakdown protection for preventing the input signal from reverse breakdown at the input terminal of the first transistor connected in parallel at the input port of the mixer to the series resonant circuit. The mixer according to claim 4, further comprising a circuit. 8. A first FE having a gate, a drain and a source, the gate being connected to a first port of the mixer.
A T-transistor, a diplexer circuit interposed between the drain and the second and third ports of the mixer, and a resonant circuit connected between the gate and the drain, the first port of the mixer And a resonance circuit that provides signal separation between the second port and the second port. 9. The diplexer circuit couples signal energy of a first frequency between the drain and the second port, and couples signal energy of a second frequency between the drain and the third port. 9. The mixer of claim 8 including inductive and capacitive circuit elements for 10. The mixer of claim 8, wherein the resonant circuit comprises an inductive element in parallel with the gate / drain capacitance of the FET transistor. 11. The method of claim 8, further comprising a series resonant circuit at the gate of the first FET transistor, the series resonant circuit including an input inductive element and a gate / source capacitance of the first FET transistor. Mixer. 12. The method of claim 10, further comprising a series resonant circuit at the gate of the first FET transistor, the series resonant circuit including an input inductive element and a gate / source capacitance of the first FET transistor. Mixer. 13. Connected to the input port of the mixer,
The input signal sent to the input port is the first FET
9. The mixer of claim 8, further comprising a reverse breakdown prevention circuit for preventing reverse breakdown at the gate of the transistor. 14. A local oscillator (LO) port for receiving a local oscillation signal, a first FET transistor having a gate, a drain and a source, the gate being connected to the LO port, and a high frequency (RF) of the drain and the mixer. ) And an intermediate frequency (IF) port, and a diplexer circuit interposed between the gate and the drain, and a signal separation between the RF port and the LO port of the mixer. An unbalanced FET mixer comprising: 15. The method according to claim 14, further comprising a series resonance circuit connected between the LO port and the gate of the FET transistor, the series resonance circuit resonating at a frequency of the local oscillation signal. Mixer.