JPH09275413A - Inter-network equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inter network equipment which conducts a highly efficient routing in a large scale network by enhancing the utilizing efficiency of a path interconnecting a memory of each processor module of a multi- processor router and each processor module. SOLUTION: In this inter network equipment containing plural networks and adopting a multi-processor structure for communication among networks, a master module 2 having functions of routing protocol processing, routing processing and address solution processing informs dynamically path information to link modules 3, 4 each having a routing processing function. Furthermore, the path information has both sets of network layer address and data link layer address in common and the path information to be noticed as above is only information required for the link module 3 or 4 so as to reduce the memory capacity of the link module and make the retrieval processing of the path information efficient.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internetwork device for connecting networks, and more particularly to a routing system for an internetwork device having a multiprocessor structure.

[0002]

2. Description of the Related Art A conventional routing method is disclosed in Japanese Patent Laid-Open No. 7-1.
As described in JP07111, only the destination network information is included as the route information. In this conventional method, it is necessary to search the destination hardware information after searching the route information that determines the relay destination route, and the search efficiency in the routing process has not been considered.

[0003]

The above-mentioned prior art does not consider the use efficiency of the memory for the route information and the address resolution information and the number of times of reading, and uses the memory more than necessary, and the search processing is There was a problem with duplication.

An object of the present invention is to provide an internetwork apparatus having a master module for executing a routing protocol and one or a plurality of link modules for performing packet relay processing between networks. It is to optimize the memory usage of the link module cache by dynamically notifying the route information of the.

Another object of the present invention is to simplify cache search processing in a link module in an internetwork device having a master module that executes a routing protocol and one or more link modules that perform packet relay processing between networks. Is to turn into.

Another object of the present invention is to provide destination network information and hardware information in an internetwork device having a master module for executing a routing protocol and one or more link modules for performing packet relay processing between networks. By holding the route information in one entry, it is intended to improve the search efficiency in the routing process.

[0007]

In order to achieve the above object, in an internetwork apparatus having a master module that executes a routing protocol and one or more link modules that perform packet relay processing between networks, the master module is Only the required information is dynamically notified to each link module, and each link module side adopts a method of storing both route and address resolution information in a cache manner.
In addition, in order to simplify the processing on the link module side, the master module has comprehensive management of route information and address resolution information, and the link module side executes only route information search processing and packet transmission / reception processing. It was done. Further, on the premise of the multicast function in the inter-module bus (function of transmitting to a plurality of link modules at once), the multicast function is used at the time of notifying the route and address resolution information in order to improve the bus usage efficiency.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of a multiprocessor type internetwork device which is an operating environment of an embodiment of the present invention. The internetwork device (1) has one master module (2) having a routing protocol function for managing route information and address resolution information, a function for relaying packets, and a hardware address resolution function, and a transmission path (28, 29, 30). , 31), and one or a plurality of link modules (3, 4) having a high-speed routing function and a module-to-module bus (5) for connecting the modules. The master module (2) includes a route information database (6) having route information of the network layer, a route information management mechanism (7) having a function of managing the route information database (6), and a network layer address (protocol address). And an address resolution information database (8) having correspondence information of data link layer addresses (hardware addresses), an address resolution management mechanism (9) having a function of managing the address resolution information database (8), and updating of the database. A timer monitoring mechanism (10) having a function of deciding a trigger, a packet processing mechanism (11) addressed to its own station having a function of processing a received packet whose destination address is its own station, and a packet relay having a packet relay function. Mechanism (13) and other link modules via intermodule bus (5) (3,4) between the modules have the function of communicating with the between bus transfer mechanism composed of (13).

The link module (3, 4) includes one or more physical ports (24, 25, 26, 27) and a transmission line (2).
8, 29, 30, 31) and a packet transmission mechanism (20, 21) having a function of transmitting a packet to a transmission line (28,
29, 30, 31) having a packet receiving mechanism (22, 23) having a function of receiving a packet from the module, a function of receiving a packet from the inter-module bus (5) and a function of transmitting a packet to the bus (5). Bus transfer mechanism (14, 1
5), a relay information cache (16, 17) having routing information having both functions of a hardware address and a protocol address, and the cache (16, 1)
It is composed of a cache management mechanism (18, 19) having a registration and retrieval function of 7).

FIG. 2 is a packet format diagram on the transmission line, and FIG. 3 is an inter-module transfer packet format diagram on the inter-module bus (5).
2) is a data link layer header part (33) consisting of a destination hardware address part (36) and a source hardware address part (37) and a destination protocol address part (3)
8) and a source layer protocol address section 39, a network layer header section 34 and a data section 35, and a protocol address section 38, 39.
Is a network section (40) and a station section (41)
Consists of The inter-module transfer packet (42) determines whether the destination port number (44), the cache registration destination port number (45), and the arrival point of the transmission path packet (32) are in the network directly connected to the own router. It is composed of an inter-module transfer packet management header part (43) including a direct connection flag (46) shown and a transmission line packet (32).

FIG. 4 shows the relay information cache (16, 17).
FIG. 4 is a cache entry format diagram of one cache entry (47), which is composed of a destination protocol address (48), a destination port number (49) and a destination hardware address (50), a data link layer address and a network. The relay information cache (16, 17) characterized by having both information of layer address
Is composed of 0 or more cache entries (47).

The operation of each mechanism of the master module (2) and the link module (3, 4) will be described below.

FIG. 5 is a processing flow when the link module (3, 4) receives a packet.
When the transmission line packet (32) is received by the physical port (24, 25, 26, 27) from the physical port (24, 25), it notifies the cache management mechanism (18, 19). The cache management mechanism (18, 19) first searches the relay information cache (16, 17) for a matching entry (47) using the network part (40) of the destination protocol address (38) as a key, and the search fails. In this case, all protocol addresses (38) are used as a key to search again. If the search fails, the bus transfer mechanism (14, 15) transfers the packet to the master module (2). On the other hand, if the search is successful, the destination hardware address of the relay information cache entry (47) read by the search is copied to the destination hardware address part (36) of the packet, and then the relay information cache entry The physical port indicated by the destination port number (49) in (47) is the physical port that received the packet (24, 25, 26, 27)
And check if it exists in the same module as. If it exists in the inspection, the packet transmission mechanism (20, 2,
1) is the source hardware address part (3
7) physical port to send to (24, 25, 26, 27)
Hardware address is copied, transmission processing is executed, and if it is not found in the above inspection, the bus transfer mechanism (1
4, 15) is the link module (3, where the destination port number on the relay information cache entry (47) exists.
High-speed routing is implemented by transferring to 4).

FIG. 6 is a master module relay operation flow performed after a cache search failure in the link modules (3, 4). The inter-module bus transfer mechanism (13) is shown in FIG.
When the packet (42) is received from the inter-module bus (5), the relay mechanism (12) is notified and the mechanism (12) is notified.
Performs a check as to whether the destination protocol address (38) of the transmission path packet (32) included in the packet is addressed to itself. If it is addressed to its own station in the inspection, it notifies the packet processing mechanism (11) addressed to itself, and if it is not addressed to its own station, it notifies the route information management mechanism (7), and the mechanism (7)
Searches the shortest route from the route information database (6) using the network part (40) of the destination protocol address part (38) of the packet as a key. If the route does not exist in the search, the packet is discarded, and if the route exists in the search, the transmission physical port number is set in the destination port number (44) of the inter-module packet management header (43). And the reception physical port number in the cache registration port number (45) of the header (43), and whether the arrival point of the packet exists in the network directly connected to the own internetwork device (1). Write a direct connection flag (46) indicating that, and notify the address resolution management mechanism (9). The mechanism (9) executes address resolution processing, and if this processing is successful, updates the information database (8), then copies to the destination hardware address part (36) of the packet (32) and relays it. Mechanism (1
Notify 2). If the address resolution process fails, the packet is abandoned. The relay mechanism (12) transfers the same packet to the source link module immediately after transferring the packet to the destination link module when the inter-module bus multicast function is not provided. And the receiver link module at the same time, it is possible to improve the usage efficiency of the inter-module bus (5) in the multiprocessor type internetwork device (1) and to move only necessary route information. It becomes possible to register in the link module.

In FIG. 7, the link module (3, 4) is a master module (2) or another link module (3, 4).
4 shows a packet transmission / cache registration processing flow executed when receiving the inter-module transfer packet (42) from 4). When the bus transfer mechanism (14, 15) receives the inter-module transfer packet (42), does the physical port indicated by the registration destination port number (45) of the inter-module transfer packet management header (43) exist in its own link module? Executes cache registration determination processing. If it does not exist, the packet is notified to the packet transmission mechanism (20, 21). If present, cache management mechanism (18, 1,
9) is notified and cache registration processing is executed. When the mechanism (18, 19) refers to the direct connection flag (46) of the inter-module transfer packet management header (43) and the arrival point of the transmission path packet (32) exists in the network directly connected to the own link module. , The entire destination protocol address (38) of the packet is registered in the destination protocol address (48) of the cache entry (47), and the arrival point of the transmission line packet (32) exists in the network directly connected to the own router. If not, the network part (40) of the destination protocol address part (38) of the packet is registered in the destination protocol address (48) of the cache entry (47), and the transmission port number (49) of the cache entry (47) is registered. ) And the destination hardware address (50) of the inter-module transfer packet management header (43) Shinsaki to register the port number (44) and a destination hardware address (36), and notifies the packet transmission mechanism (20, 21). The mechanism (20, 21) executes a packet transmission determination process as to whether the physical port indicated by the transmission destination port number (44) of the inter-module transfer packet management header (43) exists in its own link module. If it exists, the destination port number (4
4) Physical port (24, 25, 26, 27)
If the packet does not exist, the packet is discarded.

FIG. 8 is an operation flow of the master module (2) which gives a cache entry deletion instruction when the route information database (6) of the master module or the address resolution information database (8) changes.
In (a), when the route information database (6) changes, the packet relay mechanism (12) receives a notification from the timer monitoring mechanism (10) or the own-station-destined packet processing mechanism (11) and uses the address information of the network layer as a key. The operation for transmitting the cache entry deletion instruction to all the link modules (3, 4) is shown. (B) shows the packet relay mechanism (12) when the address resolution information database (8) changes and the timer monitoring mechanism (10) or its own station. This is an operation of receiving a notification from the destination packet processing mechanism (11) and transmitting a cache entry deletion instruction using the hardware address information as a key to all link modules (3, 4).

FIG. 9 shows the operation flow when the link module (3, 4) receives the cache entry deletion instruction, and the bus transfer mechanism (14, 15) instructs the cache entry deletion instruction from the master module (2). Received
Notify the cache management mechanism (18, 19). The management mechanism determines whether the key of the instruction is a network layer address or a data link layer address. If the network layer address is a key, the management information is stored in the relay information cache (16, 17) as the key address. A cache entry (4 with the same destination protocol address (48)
7) is searched, and if the hardware address is the key, the cache entry (47) having the same destination hardware address (50) as the key address is searched from the relay information cache (16, 17). If the corresponding entry exists in the relay information cache (16, 17), the entry is deleted, and if there is no corresponding entry, the process is terminated.

[0019]

According to the present invention, since the route information held by each link module in the internetwork apparatus having the multiprocessor structure is only the minimum necessary information for each link module, the memory is used efficiently. It is possible. Further, since the route information held by each link module has both the information of the address of the network layer and the address information of the data link layer, high-speed and highly efficient search processing can be performed. Further, by using the multicast method in the communication between the multiprocessors, the processing of the master module and the load on the interprocessor connection bus can be reduced.

[Brief description of drawings]

FIG. 1 is a structural diagram of an internetwork device having a multiprocessor structure.

FIG. 2 is a packet format flowing on a network transmission path.

FIG. 3 is a packet format flowing on a bus in an internetwork device.

FIG. 4 is a format of a cache entry held by a link module.

FIG. 5 is a packet reception processing flow in the link module.

FIG. 6 is a relay processing flow in the master module.

FIG. 7 is a packet transmission processing flow in the link module.

FIG. 8 is a flowchart of a cache entry deletion instruction transmission processing flow in the master module.

FIG. 9 is a flow chart of a cache entry deletion instruction reception processing flow in the link module.

[Explanation of symbols]

1 ... Internetwork device, 2 ... Master module,
3, 4 ... Link module, 5 ... Inter-module bus, 6
... Route information database, 7 ... Route information management mechanism, 8 ...
Address resolution information database, 9 ... Address resolution information management mechanism, 10 ... Timer monitoring mechanism, 11 ... Self-addressed packet processing mechanism, 12 ... Packet relay mechanism, 13 ... Inter-module bus transfer mechanism, 14, 15 ... Bus transfer mechanism, 16,
17 ... Relay information cache, 18, 19 ... Cache management mechanism, 20, 21 ... Packet transmission mechanism, 22, 23 ...
Packet receiving mechanism, 24-27 ... Physical port, 28-3
1 ... Transmission line.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Andrew Heart 810 Shimoimaizumi, Ebina City, Kanagawa Prefecture, Office Systems Division, Hitachi, Ltd. (72) Masashi Fukuda 810 Shimoimaizumi, Ebina City, Kanagawa Hitachi, Ltd. Office (72) Inventor Hiroyuki Sakoda 1 Horiyamashita, Hadano City, Kanagawa Prefecture Hitachi Computer Engineering Co., Ltd. (72) Inventor, Yasunori Oikawa 6-81, Onoue-cho, Naka-ku, Yokohama, Kanagawa Hitachi Software Engineering Co., Ltd. In the company

Claims (5)

[Claims] 1. An internetwork device for connecting a plurality of networks to each other and relaying packets between the connected networks, wherein one or more internetwork devices for performing a packet relay process between a master module executing a routing protocol and the networks. And a link module of
The master module and the link module are configured by separate processors, the master module and the link module are interconnected via an inter-module bus, and the master module manages route information. Address resolution information management that resolves the destination hardware address of the route information section and the terminal that is the calculation result of the mechanism and the route information, and the relay processing of the communication packet between the address resolution information section that is the resolution result of the destination hardware address and the terminal The inter-module bus transfer mechanism that transfers and receives packets to and from the link module via the inter-module bus and the frame relay mechanism that performs one or more of the link modules. Port and reception process of packet received by the port And a packet transmission mechanism for performing packet transmission processing to the network through the port, a cache unit having a route information unit and an address resolution information unit, and registration of route information and address resolution information in the cache unit, and A cache management mechanism for deleting and a cache search mechanism for performing a destination search process of a received packet by referring to the cache unit and a packet received from a network are transferred to the master module or the other link module via the inter-module bus. When the packet is received from the port connected to the network via the packet receiving mechanism, the cache search mechanism searches the cache unit using the destination network address information of the packet as a key. Then As a result of the search, when the relay destination information and the destination hardware address information are registered in the cache unit, the bus transfer mechanism is used to transfer the packet to the other link module which is the relay destination of the registered packet. The other link module performs transfer, receives the transferred packet via the bus transfer mechanism, and transmits the received packet to the port connected to the network via the packet transmission mechanism. Internetworking equipment. 2. The individual entry information in the cache unit is composed of both relay destination information of the route information unit and destination hardware address information of the address resolution information unit, and the relay destination of the cache unit. The number of pieces of information includes all or part of the relay destination information included in the route information section, and the number of destination hardware address information included in the cache section corresponds to the entire destination hardware address information included in the address resolution information section. Alternatively, the internetwork device according to claim 1, wherein the internetwork device has only a part thereof. 3. The bus transfer mechanism is used if relay destination information or destination hardware address information is not registered in the cache unit when the cache search mechanism searches the cache unit. Then, the master module, which transmits the packet to the master module and receives the transmitted packet via the inter-module bus transfer mechanism, performs the packet reception process in the frame relay mechanism, The routing information management mechanism searches the relay destination information from the unit, and the destination hardware address information is searched from the address resolution information unit using the destination network address information in the packet received by the address resolution information management mechanism as a key. In the frame using the relay destination information and destination hardware address information obtained from the result The mechanism transmits to the link module that is the destination of the packet using the inter-module bus transfer mechanism, and the link module that receives the packet from the master module via the bus transfer mechanism uses the packet transmission mechanism. The internetwork apparatus according to claim 1, wherein packet transmission is performed to the port connected to the network via the network. 4. The master module dynamically gives a registration instruction of relay destination information and destination hardware address information to a transmission source link module of the packet via an inter-module bus transfer mechanism. Claim 3
The internetwork device described. 5. A registration instruction of relay destination information and destination hardware address information for the link module which is a transmission source of the packet by utilizing a bus multicast transfer function of the inter-module bus transfer mechanism,
The internetwork apparatus according to claim 4, wherein packet transmission to the link module, which is the destination of the packet, is performed simultaneously.