JPH09275192A - Semiconductor storage device and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain larger ferroelectric area in a memory cell using two ferroelectric capacitors and two cell transistors, by forming the cell by laminating two ferroelectric capacitors, and using an electrode sandwiched between two ferroelectric substances as a control voltage input line. SOLUTION: In a cell structure, a word line 1 is polysilicon, a lower electrode 2 of a ferroelectric capacitor is lamination structure of Pt/Ti, a ferroelectric substance 3 is PZT, an intermediate electrode 4 is Pt, an upper electrode 5 of ferroelectric substance is Pt, a bit line 6 is Al, a local wiring 7 is Al, an interlayer insulating film 9 is SiO2 , and a bit line 11 is Al. In this constitution, ferroelectric capacitors Cf0 and Cf1 are constituted by using PZT, and laminated. The upper electrode 5 and the lower electrode 2 are connected with a cell transistor Tr0 and a cell transistor Tr1, respectively. The intermediate electrode 4 is used as a plate line. As a result, the areas of Cf0 and Cf1 can be made larger than the conventional case.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to the structure of a semiconductor memory using a ferroelectric capacitor.

[0002]

2. Description of the Related Art A so-called ferroelectric memory in which a semiconductor and a ferroelectric, for example, lead zirconate titanate (Pb (Zr _x Ti _1-x ) O ₃ ; hereinafter, abbreviated as PZT) is combined is used. "1", "0" using remanent polarization of ferroelectrics
Is stored. It is known that this operates as a non-volatile memory because it is retained even when the power is turned off.

As a basic configuration of this ferroelectric memory, FIG. 3 shows an example of a unit cell of the reference (IEEE J
ournal of Solid-State Circuits, vol. 25, No.5, p11
71) shows the circuit configuration.

Referring to FIG. 3, a unit cell is normally composed of two cell transistors T each composed of an n-channel MOSFET.
r0, Tr1 and two ferroelectric capacitors Cf0, Cf1 are combined. This cell includes a ferroelectric capacitor Cf0, a cell transistor Tr0, a bit line BL,
A cell 0 composed of a plate line PL and a word line WL, a ferroelectric capacitor Cf1, a transistor Tr1, a bit line BL 2 ,
It can be considered as a combination of the cell 1 including the plate line PL and the word line WL.

FIG. 4 shows the relationship between the polarization of the ferroelectric capacitors Cf0 and Cf1 used in the cell shown in FIG. 3 and the applied voltage. This is a characteristic known as the hysteresis of a ferroelectric substance. When the applied voltage is swung positively and then dropped to zero, positive remanent polarization remains, and when the applied voltage is swung negative and dropped to zero. Remains a negative remnant polarization. In this cell, the voltage applied to the bit lines BL, BL , the plate line PL, and the word line WL is controlled, Tr0 and Tr1 are turned on and off, and the voltage applied to Cf0 and Cf1 is controlled to control the remanent polarization of each. Alternatively, the reading operation is performed. For example, at the time of writing the signal "1", Cf0 is given a negative remanent polarization, and at the same time, Cf1 is given a positive remanent polarization.

On the contrary, when writing the signal "0", Cf
A positive remanent polarization is given to 0, and a negative remanent polarization is given to Cf1. The level of the voltage appearing on the signal read line, that is, the bit lines BL and BL changes depending on whether the remanent polarization is positive or negative. The voltage is low when the voltage is positive and high when the voltage is negative. Therefore, BL and BL depending on “1” and “0”
The level of the voltage appearing at is changed, and when it is "1", B
L: high, BL : low, and when "0", BL: low,
BL : High. Therefore, "1" and "0" can be discriminated by discriminating whether the potential difference between BL and BL is positive or negative.

Here, in order to determine "1" or "0", to see the potential difference between the bit lines BL and BL , each unit cell has two ferroelectric capacitors and two cell transistors. There is. Set the reference signal level outside the cell,
It may be possible to judge whether the remanent polarization of Cf0 is positive or negative by comparing this with the voltage of BL at the time of reading. In this case, C
Since f1, Tr1, and BL are not necessary, the number of constituent elements of the unit cell is reduced, which is advantageous for increasing the density of the memory.

Further, even if a structure (so-called dummy cell) in which positive and negative remanent polarization is given to the ferroelectric capacitor is installed outside the memory cell in advance and it is used as a reference signal, the unit cell is the same. Can be structured. In this case, the dummy cell can be used once for a plurality of memory cells, which is also advantageous for increasing the density.

However, it is generally known that a phenomenon called fatigue occurs in the ferroelectric capacitor. This is the property that the value of the remanent polarization becomes smaller as the number of cycles for changing the voltage applied to the ferroelectric substance to positive and negative is added. For example, in the case of PZT, it is known that the residual polarization value becomes half or less of the original value after 10 ⁹ cycles. Therefore, in actuality, the potential of BL at the time of reading described above changes as the number of write and read cycles increases, even if the same "1" is set, and it is difficult to set the reference signal level externally. Is.

Further, in the case of the method of installing the dummy cell outside the memory cell, this dummy cell is accessed every time one of the memory cells corresponding to one dummy cell is read. Therefore, the number of times the dummy cell is accessed becomes significantly larger than the number of times the memory cell is accessed, and even if the ferroelectric capacity of the memory cell is not fatigued, the ferroelectric capacity of the dummy cell is fatigued and its use is reduced. I will not do it.

The memory using the unit cell having the structure shown in FIG. 3 does not have these drawbacks because the height of the bit lines BL and BL is determined by looking at the difference. Therefore, since it has a characteristic that the influence of the fatigue of the ferroelectric capacitor is unlikely to occur, it is effective as a stable memory operation.

A structure for realizing the unit cell of the circuit diagram of FIG. 3 is shown in a plan view of FIG. 7A, and a cross-sectional view taken along the line DD 'in FIG. 7B. FIG. 7 is a sectional view in the E ′ direction.
It is shown in (C).

In FIG. 7, 1 is a word line (the gate of a cell transistor is made of polysilicon), 3 is PZT,
5 is a ferroelectric upper electrode (Pt), 6 is a bit line (A)
l), 7 are local wiring (Al), 8 is a silicon n + layer, 9
Is an interlayer film SiO ₂ , 10 is a silicon p-type layer, and 11 is a bit layer.
Wires (Al) and 12 are plate wires or a ferroelectric capacitor lower electrode (Pt / Ti, that is, a laminated structure in which Pt is deposited on Ti).

In this example, the ferroelectric capacitance Cf0,
Cf1 is formed on the same plate line 12, and is connected to the bit line 6 and the bit line 11 via Tr0 and Tr1, respectively. The cell having this structure can be considered as two vertically connected cells each including a ferroelectric capacitor and a cell transistor.

[0015]

Problems of the structure of the conventional cell shown in FIG. 7 will be described below.

It is clear that the larger the remanent polarization value of the ferroelectric capacitor is, the larger the voltage that becomes a signal at the time of signal reading becomes, which is advantageous in device operation. However, the remanent polarization value is the ferroelectric capacitor. Since it is proportional to the area of the device, it is preferable to set this area to be large because the operational margin of the device becomes large.

However, since the conventional cell structure shown in FIG. 7 requires two ferroelectric capacitors,
It is difficult to make this area large. Therefore, the area of the ferroelectric capacitor must be reduced, and it is impossible to obtain a large remanent polarization.

Further, as shown in the examples in FIGS. 5 and 6,
Fatigue becomes a problem because positive and negative pulses are always input to the ferroelectric capacitor for writing and reading.

As a countermeasure against this, if the area of the ferroelectric substance is increased to increase the remanent polarization, the remanent polarization after fatigue can be increased even if the same operation cycle is passed, and therefore, the usable cycle thereof. Will increase. But,
In the conventional cell structure shown in FIG. 7, it is difficult to increase the area of the ferroelectric capacitor, so the above measures cannot be taken.

The present invention has been made in view of the above circumstances, and an object thereof is to obtain a larger ferroelectric area in a memory cell using two ferroelectric capacitors and two cell transistors. It is to provide a cell structure capable of doing so.

[0021]

In order to achieve the above object, the semiconductor memory of the present invention is a semiconductor memory in which a unit memory cell is composed of two ferroelectric capacitors and two transistors. Formed by stacking body volumes,
The electrode sandwiched between the two ferroelectrics is used as a control voltage input line to the cell.

A driving method exactly the same as the conventional one can be applied to the memory having this structure. As the _{ferroelectric, Pb (Zr x Ti 1-} x) O 3, SrBi 2 Ta 2 O 9
Are used.

[0023]

In the present invention, the two ferroelectric capacitors forming the unit cell have a laminated structure, and the intermediate electrode sandwiched between the two is used as a plate line. As a result, the ferroelectric area can be made larger than in the conventional example.

[0024]

Next, embodiments of the present invention will be described with reference to the drawings.

The circuit configuration of the unit cell of the semiconductor nonvolatile memory of the present invention is the same as that of the conventional example shown in FIG. 3, but the structure is different.

1 is a plan view of an embodiment of the present invention, FIG. 2A is a sectional view taken along the line AA 'in FIG. 1, and FIG. 2B is a sectional view taken along the line BB'. A cross-sectional view in the C ′ direction is shown in FIG.
Shown in

In FIGS. 1 and 2, 1 is a word line (cell transistor gate), 2 is a ferroelectric capacitor lower electrode (metal electrode), 3 is a ferroelectric substance, 4 is a plate line or an intermediate electrode (metal electrode). ) 5, ferroelectric upper electrode (metal electrode), 6 bit line (metal electrode), 7 local wiring (metal), 8 silicon n + layer, 9 interlayer insulating film, 10 silicon p-type layer, Reference numeral 11 is a bit line (metal similar to 6).

The embodiment of the present invention is different from the conventional cell structure shown in FIG. 7 in that Cf0 and Cf1 have a laminated structure. In this case, the intermediate electrode of the laminated structure, that is, the intermediate metal electrode between the upper ferroelectric substance and the lower ferroelectric substance is used as the plate line, that is, the electrode line on the side not connected to the cell transistors Cf0 and Cf1. I am using. Therefore, the driving method and the like can be exactly the same as the conventional memory.

[0029]

EXAMPLES Examples of the present invention will be described below in order to explain the above-described embodiments of the present invention in more detail.

In this embodiment, in the cell structure shown in FIGS. 1 and 2, the word line 1 is polysilicon, the ferroelectric capacitor lower electrode 2 is a Pt / Ti laminated structure, and the ferroelectric 3 is PZ.
T, the intermediate electrode 4 is Pt, and the ferroelectric capacitor upper electrode 5 is P
t, the bit line 6 is Al, the local wiring 7 is Al, the interlayer insulating film 9 is SiO ₂ , and the bit line 11 is Al.
Reference numeral 8 is a silicon n + layer, and 10 is a silicon p-type layer.

Therefore, in this configuration, in FIG.
The word line WL is polysilicon, the plate line PL is Pt,
The bit lines BL and BL are made of Al. Also,
In this structure, both the ferroelectric capacitors Cf0 and Cf1 are formed by using PZT, which are laminated, and the upper electrode 5 and the lower electrode 2 of the ferroelectric capacitors Cf0 and Cf1 are respectively stacked.
0, Tr1 and the intermediate electrode is the plate line 4.

As shown in FIGS. 2 (B) and 2 (C),
The connection between the upper electrode 5, the lower electrode 2 and Tr0, Tr1 is
Just as in the example of FIG. 7, the local wiring 7 of Al is used.

In manufacturing the semiconductor memory having this structure, the step of manufacturing the ferroelectric capacitor is important.

Particularly, in order to form the laminated structure, P
As a method for forming ZT, Pt, and Ti, a method capable of forming a high-quality ferroelectric thin film such as a sputtering method or a CVD method is an effective method, and this structure is formed by sequentially forming these materials. it can.

For the processing, a dry etching method capable of performing such fine processing, for example, a method such as reactive ion etching or ion milling using Ar or the like is used.

In this embodiment, PZT is used as the ferroelectric substance and Pt is used as the upper electrode, the lower electrode and the intermediate electrode thereof, but other ferroelectric substances such as SrBi ₂ Ta ₂ O ₉ etc.
Alternatively, other electrodes such as Ru and RuO ₂ can be used, and are used for a combination of a ferroelectric with good ferroelectric characteristics, that is, a readable residual polarization value and upper and lower electrodes. be able to. Further, it is needless to say that other materials generally used for LSI can be used for the bit line, the word line, the local wiring and the like.

The input pulse for writing "1" in this cell is shown in FIG. After this pulse input, finally C
Since a voltage of PL: zero and a voltage of BL: positive are applied to f0, a negative remanent polarization is generated, and a voltage of PL: positive, BL : zero, to Cf1.
On the contrary, positive remanent polarization remains.

On the other hand, in the case of writing "0", it is sufficient to input the bit lines BL and a pulse in which BL is reversed.

Further, FIG. 6 shows another example of the input pulse when "1" is written. In this case, unlike FIG. 5,
The plate line PL is High and L of the pulse input to BL.
The intermediate potential of ow (Vc / 2) is set. Therefore, the pulse is substantially only input to BL. After this pulse is input, PL: Vc / 2, B is finally applied to Cf0.
Since a voltage of L: Vc is applied, the negative remanent polarization is
Voltages of PL: Vc / 2 and BL : zero are applied to Cf1, and conversely positive remanent polarization remains. Also in this case, if the bit lines BL and BL are reversed, "0" is written in the same manner as described above.

In this embodiment, it is clear that the areas of Cf0 and Cf1 can be made larger than those of the conventional example shown in FIG. 7, and in particular, the ratio of the ferroelectric capacitance area to the cell area is made large. be able to. Therefore, it is possible to reduce the loss of the area of the ferroelectric capacitor even when the degree of integration is increased, and it is possible to increase the remanent polarization value.

[0041]

As described above, according to the present invention,
The area of the ferroelectric capacitor can be increased in the memory cell. Therefore, a semiconductor memory can be obtained in which the remanent polarization of the ferroelectric capacitor is large, the device operation margin is large, and fatigue is strong.

[Brief description of drawings]

FIG. 1 is a diagram showing a plan view of an embodiment of a nonvolatile memory of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention shown in FIG.
(A) is a sectional view in the AA 'direction, (B) is a sectional view in the BB' direction, and (C) is a sectional view in the CC 'direction.

FIG. 3 is a circuit diagram of a unit cell of a nonvolatile memory using a ferroelectric substance.

FIG. 4 is a diagram showing a hysteresis characteristic of a ferroelectric substance.

FIG. 5 is a diagram showing an example of an input pulse when writing “1” in a unit cell of a ferroelectric memory.

FIG. 6 is a diagram showing another example of the input pulse when writing “1” in the unit cell of the ferroelectric memory.

FIG. 7A is a plan view of a conventional nonvolatile memory,
(B) is a sectional view in the DD 'direction, and (C) is a sectional view in the EE' direction.

[Explanation of symbols]

1 word line (polysilicon) 2 ferroelectric capacitor lower electrode (Pt / Ti) 3 ferroelectric (PZT) 4 plate line or intermediate electrode (Pt) 5 ferroelectric upper electrode (Pt) 6 bit line (Al) 7 Local Wiring (Al) 8 Silicon n + Layer 9 Interlayer Film (SiO ₂ ) 10 Silicon p-type Layer 11 Bit Line (Al) 12 Plate Line or Ferroelectric Capacitance Lower Electrode (Pt /
Ti)

Claims (5)

[Claims] 1. A unit memory cell has two ferroelectric capacitors and two ferroelectric capacitors.
In a memory cell of a semiconductor memory composed of two transistors, two ferroelectric capacitors are stacked and formed, and an electrode sandwiched between the two ferroelectric capacitors is used as a control voltage input line to the memory cell. A semiconductor memory characterized by being used. 2. A ferroelectric capacitor formed by stacking two ferroelectric capacitors,
In a method of driving a semiconductor memory, wherein an electrode sandwiched between the two ferroelectric capacitors is used as a control voltage input line to a memory cell, a first pulse is input to the control voltage input line, and an upper electrode or A method of operating a semiconductor memory, wherein binary information is written in a memory cell by applying a second pulse to a lower electrode. 3. A memory cell is formed by inputting a pulse to one of an upper electrode and a lower electrode of the control voltage input line and setting the control voltage input line to an intermediate potential between a high potential and a low potential of the pulse. 3. The method of operating a semiconductor memory according to claim 2, wherein binary information is written. 4. The ferroelectric material is Pb (Zr _x Ti _1-x ) O ₃
The semiconductor memory according to claim 1, wherein 5. The semiconductor memory according to claim 1, wherein the ferroelectric substance is SrBi ₂ Ta ₂ O ₉ .