JPH09266196A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the dimensional conversion difference in the patterning by setting the angle between the surface of a material layer to be etched and side wall of a resist mask to a value exceeding the retrogressing angle of a resist mask by etching and less than the deposition angle of a fluorocarbon type polymer on the side wall of the mask. SOLUTION: The angle between the surface of an offset insulation film 5 i.e., a material layer to be etched and inside wall of a resist mask 6 is set to a value exceeding the retrogressing angle of the line width of the mask 6 by etching and less than the deposition angel of a fluorocarbon type polymer on the side wall of the mask 6. This provides a correlation of the angle between the material layer surface and inside wall of the resist mask with the amt. of the side wall deposited polymer and dimensional conversion difference. If the mask 6 is designed for the angle in this range, the dimensional conversion difference can be reduced and stably controlled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having an etching process that requires fine and strict dimensional controllability.

[0002]

2. Description of the Related Art As semiconductor devices such as LSIs have been highly integrated, miniaturization of internal wiring and electrodes has been advanced. The minimum design rule applied to the gate electrodes of MOS transistors is the DRAM (Dynamic Random Accsess).
s Memory) as an example, 0.5μ in 16M DRAM
m, 64M DRAM 0.35μm and next generation 25
It is set to 0.25 μm in 6 MDRAM. In such fine gate electrode etching, a high selection ratio is required as the underlying gate insulating film becomes thinner, and
Strict dimensional control of the pattern width is required. n ⁺ Pol
In the gate electrode processing for etching a refractory metal polycide layer such as y-Si / WSi ₂ using a resist mask, due to the progress of gas chemistry using Cl-based gas or Br-based gas, an extremely thin gate oxidation of about 4 nm is performed. High selectivity to membrane and dimensional conversion difference (ΔCD,
(Pattern shift) to 0.02 μm, that is, the stage where controllability of about 20 nm is obtained has already been reached.

It is considered that as the degree of integration is further increased in the future, a self-aligned contact structure which does not require mask alignment in the processing of contact holes will be adopted.
An example of the manufacturing process of this self-aligned contact structure will be described with reference to FIGS. First, FIG.
As shown in (a), a gate insulating film 2, a polycrystalline silicon film 3, a high resistance metal silicide film 4,
The offset insulating film 5 and the plurality of resist masks 6 are formed adjacent to each other. The space between the plurality of resist masks 6 is a portion where a self-aligned contact facing an impurity diffusion layer (not shown) of the semiconductor substrate 1 is formed in a post process. Next, as shown in FIG. 3B, the offset insulating film 5 is patterned using the resist mask 6 as an etching mask, and the resist mask 6 is removed. This state is shown in FIG. Thereafter, as shown in FIG. 3D, the offset insulating film 5 pattern was used as an etching mask.
The refractory metal silicide film 5 and the polycrystalline silicon film 4 are etched to form a plurality of gate electrodes made of a refractory metal polycide film adjacent to each other.

Next, as shown in FIG. 4E, a sidewall forming film 7 is formed on the entire surface and is anisotropically etched back to form a plurality of gate electrodes as shown in FIG. 4F. The sidewall spacer 7a is left on the side surface. After this
As shown in (g), an interlayer insulating film 8 is formed on the entire surface, and a resist mask 9 for opening a self-aligned contact hole is patterned. Strictness is not required for the alignment during the patterning exposure of the resist mask 9 for opening the self-aligned contact hole. Subsequently, the interlayer insulating film 8 is etched using the resist mask 9 for opening the self-aligned contact hole as an etching mask to open the self-aligned contact hole 10. A state in which the resist mask 9 for opening the self-aligned contact hole is peeled off is shown in FIG. Thereafter, although not shown, a contact plug and an upper layer wiring extending also over the interlayer insulating film 8 are formed in the self-aligned contact hole 10 to complete the self-aligned contact structure.

In this way, the contact surface at the bottom of the self-aligned contact hole 10 has a width and position regulated in a self-aligned manner by the sidewall spacer 7a,
It is also possible to set a minute aperture width equal to or smaller than the resolution limit of lithography. Further, the offset insulating film 5 is necessary to improve the withstand voltage between the gate electrode and the contact plug or the upper wiring, but also plays an important role as an etching mask function when processing the gate electrode.

[0006]

The dimensional conversion difference in the gate electrode processing using the offset insulating film as an etching mask is as follows. Patterning of resist mask 1. Patterning of offset insulating film 3. It appears as the sum of the three factors of gate electrode patterning. Here, the dimensional conversion difference of 1 and 3 is the same factor in the conventional gate electrode processing using the resist mask as an etching mask, but by adding a new factor of 2 to this, the dimensional conversion difference varies. Will be even bigger.

Plasma etching of a silicon oxide-based material layer such as SiO ₂ used for an offset insulating film requires ion incident energy above a certain level in order to break a strong Si—O bond (bonding energy 705 kJ / mol). It On the other hand, in order to obtain an etching selection ratio with respect to the underlying silicon, refractory metal silicide, or the like, plasma etching conditions that generate an excessively fluorocarbon-based polymer are adopted. Therefore, in the processing of a linear pattern such as a gate electrode / wiring, an excessive amount of fluorocarbon-based polymer is deposited on the resist mask or the sidewall of the linear pattern, and the line-shaped pattern is thickened. The pattern size conversion difference may reach a maximum of 0.1 μm. Further, it has been clarified by the inventors that the absolute value and variation of the dimensional conversion difference largely depend on the shape of the resist mask used for processing the offset insulating film.

The problem of the dimensional conversion difference during the etching of the offset insulating film will be described with reference to FIGS. First, as shown in FIG. 5A, a gate insulating film 2, a polycrystalline silicon film 3, a refractory metal silicide film 4, an offset insulating film 5 and a resist mask 6 are sequentially formed on a semiconductor substrate 1 and are etched. Use as a substrate. The angle θ formed between the side wall surface of the resist mask 6 and the surface of the offset insulating film 5 is usually set to 90 °, and only one resist mask 6 is shown in FIG. Next, when the offset insulating film is patterned under a high selective ratio plasma etching condition in which an excessive amount of fluorocarbon-based polymer is generated, the resist mask 6 and the sidewall of the pattern of the offset insulating film 5 being processed are patterned as shown in FIG. 5B. The patterning proceeds while the sidewall deposition polymer 11 is attached to the. Therefore, the bottom width of the completed pattern of the offset insulating film 5 is larger than the width of the resist mask 6. FIG. 5C shows a state where the resist mask 6 and the side wall deposited polymer are peeled off. Then, using the pattern of the offset insulating film 5 as an etching mask, the refractory metal silicide film 4 and the polycrystalline silicon film 3 are etched to complete a gate electrode. As is apparent from this state shown in FIG. 5D, since the shape of the offset insulating film 5 pattern hardly changes during the processing of the gate electrode, the width of the gate electrode is wider than the width of the resist mask 6 and the positive dimension conversion difference. Will occur.

An object of the present invention is to provide a method of manufacturing a highly integrated semiconductor device with high accuracy by reducing a dimensional conversion difference in patterning a material layer to be etched having a fine width such as the above-mentioned offset insulating film. And

[0010]

A method for manufacturing a semiconductor device according to the present invention is proposed to solve the above-mentioned problems, and a resist mask formed on a material layer to be etched is used as an etching mask. In a method for manufacturing a semiconductor device, which has a step of etching the material layer to be etched by an etching gas containing a carbon dioxide gas,
The angle θ formed between the surface of the material layer to be etched and the side wall surface of the resist mask from the inside of the resist mask is
It is characterized in that the line width of the resist mask exceeds the angle of receding by etching, and the angle is less than the angle at which the fluorocarbon-based polymer is deposited on the side wall of the resist mask by the etching.

The material layer to be etched targeted by the present invention can be suitably implemented when it is at least one of SiO ₂ , Si ₃ N ₄ , SiON, SiOF and organic polymers. Further, the function of the material layer to be etched, which is the object of the present invention, can be suitably implemented when it is an offset insulating film formed on the gate electrode.

Next, the operation will be described. In plasma etching using a fluorocarbon-based gas, the amount of fluorocarbon-based polymer adhering to the side walls of the resist mask and the material layer pattern to be etched is the following three types when the shape of the resist mask is constant. It is almost determined by the plasma etching conditions. (1) Incident amount of polymer from plasma due to fluorocarbon-based gas (ratio of carbon to fluorine in plasma, C / F ratio) (2) Probability of polymer adhesion on the surface of the substrate to be etched (substrate temperature to be etched, etc.) (3) Sputtering removal rate of polymer on the surface of the substrate to be etched (incident ion energy) With these plasma etching conditions being kept constant, the shape of the resist mask, that is, the surface of the material to be etched and the inside of the resist mask from the resist As a result of diligent studies, the present inventor has found that there is a certain correlation between the angle θ formed by the side wall surface of the mask and the amount of deposition of the side wall deposited polymer and the dimensional conversion difference ΔCD. It was This relationship is shown in the graph of FIG. In the graph of FIG. 4, the horizontal axis represents the resist mask angle θ, and the vertical axis represents the dimension conversion difference ΔCD.

As is apparent from this graph, when the angle θ is small, that is, the forward-tapered resist mask 6 is formed.
In this case, since the side wall of the resist mask 6 is directly exposed to ion injection, the sputtering removal rate at this portion exceeds the deposition rate of the fluorocarbon polymer determined by (1) to (3), The sidewall deposition polymer 11 does not adhere, but rather the sidewall of the resist mask 6 is sputtered and its width recedes, and as a result, a negative dimension conversion difference occurs in the offset insulating film 5 which is the material layer to be etched. This condition corresponds to the left side of the graph in FIG. 4, that is, the case where the angle θ is the angle a or less. On the other hand, when the angle θ is large, on the contrary, the probability that the side wall of the resist mask 6 is directly exposed to the ion injection is small, and the sputtering removal rate at this portion is determined by (1) to (3). Below the deposition rate of the carbon-based polymer. Therefore, the sidewall deposition polymer 11 adheres to this portion, the line width of the resist mask 6 becomes thick, and as a result, a positive dimensional conversion difference occurs in the offset insulating film 5 which is the material layer to be etched. This condition is shown in Figure 4.
The graph corresponds to the right side of the graph, that is, the case where the angle θ is equal to or larger than the angle indicated by the point b.

In the graph shown in FIG. 4, the line width of the resist mask 6 does not recede between the points a and b, and there is a region in which there is no excessive deposition of the fluorocarbon polymer. . This region has an angle θ of 90 ° or less, that is, a region having a weak forward taper shape. Therefore, if the resist mask 6 is designed to have an angle θ in this region, the dimensional conversion difference ΔCD can be made small and stable. Since the optimum range of the angle θ of the resist mask exists with a width between the points a and b, its control is easy.
The sidewall angle θ of the resist mask is controlled by the exposure amount, PEB
(Post Exposure Bake) conditions or a chemically amplified resist can be used by any method such as the addition amount of the photo acid generator PAG (Photo Acid Generator).

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention will be described below with reference to FIG. The following examples are all examples in which the present invention is applied to processing an offset insulating film on a polycide gate electrode / wiring. It should be noted that the same components as those in FIG. 5 used to explain the conventional example are denoted by the same reference numerals.

Example 1 This example is an example in which an offset insulating film is processed under a high selection ratio condition in which the amount of fluorocarbon polymer is relatively large. As the substrate to be etched, as shown in FIG.
A gate insulating film 2 made of SiO ₂ , a polycrystalline silicon film 3, a refractory metal silicide film 4 made of WSi ₂ , an offset insulating film 5, and a resist mask 6 are sequentially formed on a semiconductor substrate 1 made of silicon or the like. . Of these, the polycrystalline silicon film 3 and the refractory metal silicide film 4
As an example, each of them has a thickness of 100 nm, the offset insulating film 5 has a thickness of 230 nm, and the resist mask 6 is formed by a positive type chemically amplified resist and excimer laser lithography to have a line width of 250 nm and a side wall angle θ = 85 °.

This substrate to be etched is placed on the cathode electrode of a parallel plate type magnetron RIE apparatus, and as an example, the resist mask 6 is formed under the following plasma etching conditions.
The offset insulating film 5 exposed from the above was patterned. C ₄ F ₈ 10 sccm O ₂ 10 sccm Ar 100 sccm Gas pressure 0.5 Pa RF power source power 1000 W (13.56 MHz) Etching substrate temperature 20 ° C. This plasma etching condition has a large C / F ratio in plasma, The line width tends to be thick while the deposition property is relatively large and the selection ratio can be obtained. Therefore, the point a in the graph of FIG.
° and b point are 87 °, and there is a width of 5 ° between them. In this embodiment, by setting the angle θ to 85 °, the fluorocarbon polymer does not adhere to the side surfaces of the resist mask 6 and the pattern of the offset insulating film 5 being patterned, and the resist mask 6 is retracted. Without
Offset conversion film 5 Pattern conversion difference ΔCD +2
It could be suppressed to within 0 nm. The angle θ _O of the side surface of the offset insulating film pattern was 88 °. The substrate to be etched after the patterning of the offset insulating film 5 is completed is shown in FIG.

After that, the resist mask 6 is peeled off and the structure shown in FIG.
The substrate to be etched in the state of (c) is placed on the substrate stage of the substrate bias application type ECR plasma etching apparatus, and the refractory metal polycide film is continuously patterned using the pattern of the offset insulating film 5 as an etching mask. . The etching was performed under the following conditions as an example. Cl ₂ 75 sccm O ₂ 6 sccm Gas pressure 0.4 Pa Microwave power 850 W (2.45 GHz) Substrate bias power Main etching 80 W (13.56 MHz) Over etching 40 W (13.56 MHz) Etched substrate Temperature 20 ° C. In this plasma etching process, since the side surface of the offset insulating film pattern, which is the etching mask, is 88 °,
The polycide gate electrode / wiring did not have a remarkable dimensional conversion difference, and the width of the resist mask 6 was almost the same as the initial width.

The following sidewall spacer forming step,
Since the self-aligned contact opening step, the contact plug forming step and the like are the same as those in the prior art, duplicate description will be omitted. According to this embodiment, even if the high selective ratio etching condition in which the deposition property of the fluorocarbon polymer is strong is adopted,
It is possible to perform fine gate electrode / wiring processing without causing a positive dimensional conversion difference.

Example 2 This example is an example in which the offset insulating film was processed under a high etching rate condition in which the amount of fluorocarbon polymer deposited was relatively small. Since the substrate to be etched shown in FIG. 1A used in this embodiment is substantially the same as that in the first embodiment, duplicate description will be omitted. In this embodiment, the resist mask 6 is formed by a positive chemically amplified resist and excimer laser lithography, and has a line width of 250 nm and a side wall angle θ =.
Formed at 87 °.

This substrate to be etched is placed on the cathode electrode of a parallel plate type magnetron RIE apparatus, and as an example, the resist mask 6 is formed under the following plasma etching conditions.
The offset insulating film 5 exposed from the above was patterned. CHF ₃ 30 sccm Ar 100 sccm Gas pressure 0.5 Pa RF power supply power 1000 W (13.56 MHz) Etching substrate temperature 20 ° C. Under the plasma etching conditions, the C / F ratio in the plasma is small, so that the deposition property is small and etching is performed. While the rate is large, the line width is relatively thin. Therefore, points a and b in the graph of FIG. 4 shift to the large angle side, and point a is 85
The points b and b are around 89 °, and there is a width of 4 ° between them. In this embodiment, by setting the angle θ to 87 °, the resist mask 6 does not recede, and the fluorocarbon polymer does not adhere to the side surfaces of the resist mask 6 and the offset insulating film pattern being patterned. , Dimensional conversion difference ΔCD of 5 patterns of offset insulating film
Was suppressed to the range of 0 to -20 nm. The angle θ _O of the side surface of the offset insulating film pattern was 88 °. The substrate to be etched after the patterning of the offset insulating film 5 is completed is shown in FIG. This plasma etching condition is also an etching condition with a relatively small selection ratio, and it is difficult to obtain a selection ratio with the underlying refractory metal silicide film 4. However, since the refractory metal silicide film 4 is etched in a later step in processing the offset insulating film, the selection ratio is not a particular problem.

After the subsequent step of removing the resist mask 6, the steps up to the step of forming the contact plug are the same as those in the first embodiment, and the duplicated description will be omitted. According to the present embodiment, even if a high etching rate condition in which the deposition property of the fluorocarbon polymer is small is adopted, it is possible to perform fine gate electrode / wiring processing without causing a negative dimension conversion difference. is there.

Although the present invention has been described above with reference to two embodiments, the present invention is not limited to these embodiments.

For example, the material layer to be etched is SiO ₂
However, other material layers such as Si ₃ N ₄ , SiON, SiOF and organic polymers can be used. In particular, since SiOF and organic polymers have a small relative permittivity, they are advantageous in reducing the capacitance between wirings even when they are used as an offset insulating film having a self-align contact structure. As the organic polymer material, organic SOG containing a siloxane bond, polyimide,
There are polyparaxylylene (trade name parylene), polynaphthalene, and polymer materials containing fluorine. The low dielectric constant material layer may be used alone as an offset insulating film.
It may be used by laminating it with an inorganic insulating film such as O ₂ .

C ₄ F ₈ and C as fluorocarbon type gas
Although HF ₃ is exemplified, CF ₄ , C ₂ F ₆ , C ₃ F _6, CH ₂ F ₂ or the like can be used. However, since the C / F ratio in the plasma varies depending on each fluorocarbon-based gas, the points a and b in the graph of FIG. 4 vary. This is also the case when a fluorine chemical species capturing gas such as H ₂ or CO is mixed in the etching gas. Therefore, it is desirable to check the values at points a and b in advance for each etching gas and etching condition. O _{2 in the} etching gas,
The same applies when an additive gas such as N ₂ , Ar or He is mixed.

The present invention can be used not only to reduce the dimensional conversion difference ΔCD in the processing of the offset insulating film, but also to reduce the dimensional conversion difference in the processing of the connection hole using the above-mentioned various material layers to be etched, for example, in the interlayer insulating film. .

[0027]

As is apparent from the above description, according to the present invention, the dimension conversion difference ΔCD of the material layer to be etched can be reduced by the method of controlling the angle θ of the side wall surface of the resist mask. Therefore, it is possible to reliably manufacture a semiconductor device including a plasma etching process that requires precision such as offset insulating film processing.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view explaining an embodiment of the present invention in the order of steps thereof.

FIG. 2 is a graph showing the relationship between the angle θ of the side wall surface of the resist mask and the dimension conversion difference ΔCD.

FIG. 3 is a schematic cross-sectional view illustrating the first half of the manufacturing process of the self-aligned contact in the order of the processes.

FIG. 4 is a schematic cross-sectional view illustrating the second half of the manufacturing process of the self-aligned contact in the order of the processes.

FIG. 5 is a schematic cross-sectional view illustrating problems in processing an offset insulating film in the order of steps thereof.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Gate insulating film, 3 ... Polycrystalline silicon film, 4 ... Refractory metal silicide film, 5 ... Offset insulating film, 6 ... Resist mask, 7 ... Sidewall forming film, 7a ... Sidewall spacer, 8 ... Interlayer insulating film,
9 ... Self-aligned contact opening resist mask,
10 ... Self-aligned contact hole, 11 ... Sidewall deposited polymer

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device, comprising: a step of etching a material layer to be etched with an etching gas containing a fluorocarbon-based gas, using a resist mask formed on the material layer to be etched as an etching mask. The angle θ formed between the material layer surface to be etched and the sidewall surface of the resist mask from the inside of the resist mask is greater than the angle at which the line width of the resist mask recedes due to the etching, A method for manufacturing a semiconductor device, wherein the etching is performed at an angle less than a deposition angle of a fluorocarbon polymer on a sidewall of the resist mask. 2. The material layer to be etched is SiO ₂ , Si
_{2. The} method for manufacturing a semiconductor device according to claim 1, wherein at least one of ₃ N ₄ , SiON, SiOF and an organic polymer is used. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the material layer to be etched is an offset insulating film formed on the gate electrode.