JPH09265396A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the decoder and register of register dependency relation at the time of instruction execution and to accelerate instruction execution time by partially including the dependency relation with instruction in front and at the back of data defined as a processing object in the operand of the instruction at the time of executing the plural instructions. SOLUTION: This data processor is provided with a register file 11 provided with the plural registers to which the executed results of the instructions are written, signal selection circuits 12 and 13, a computing element 14 and a control part 17 provided with an instruction register 15 provided with an additional bit 18 and a decoder 16. By adding the additional bit 18 to the instruction register 15 provided in the control part 17, the decoder/register required before are eliminated from the control part 17. Control signals 101/102 corresponding to the respective operands of the instructions are outputted and selected data are inputted to input A/input B corresponding to the respective operands in the signal selection circuits 12 and 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and more particularly to a data processing device including a microcomputer, a digital signal processor and the like.

[0002]

2. Description of the Related Art FIG. 3 shows an example of the configuration of a conventional data processing apparatus of this type. As shown in FIG. 3, in this conventional example, a plurality of registers (R
0 to R3), a register file 31, signal selection circuits 32 and 33, a calculator 34, and an instruction register 3
5, the control unit 39 including the decoders 36 and 38 and the register 37, and the register file 3
The data output from 1 is the signal selection circuit 32, respectively.
And 33. On the other hand, the arithmetic output data output from the arithmetic unit 34 is input to the register file 31 and the signal selection circuits 32 and 3 described above are input.
3 are also input to the signal selection circuit 32 and are controlled by the control signals 101 and 102 output from the decoder 38 included in the control unit 39, respectively.
And 33, either the output data from the register file 31 or the operation output data of the operator 34 is selected and output, and the input A or the input B corresponding to the 2-input operand of the operator 34 is selected. Entered in.
In this case, in a data processing device such as a microcomputer or a digital signal processor, in executing an instruction, when executing an instruction having a register dependency before and after the instruction, the instruction (1 When the register in the register file 31 in which the execution result of (1) is written is used as the input operand corresponding to the instruction (2) immediately after the instruction, the operation result of the instruction (1) is written. The designated number of the register is temporarily stored in the register 37 in the control unit, and the designated number of the register read from the register 37 is the designated number of the instruction register 35 used in the instruction (2) in the decoder 38. It is compared and collated with. In response to the comparison result of the register designation numbers in the decoder 38, the control signal 101/102 is output from the decoder 38 and is input to the corresponding signal selection circuits 32 and 33, respectively. The control operation relating to such signal selection is a method generally used for high speed processing in a data processing device such as a microcomputer or a digital signal processor.

In the case of the above-mentioned conventional example, although the existence relationship of the registers used in the preceding and following instructions is known in advance, the designated number of the register used immediately before the instruction is temporarily set. A register 37 for temporarily storing the same and a decoder 38 for comparing and collating a designated number of the register with a designated number of a register used in an instruction immediately after that are necessary components. As another conventional example, Japanese Patent Application Laid-Open No. 5-173781 discloses an information processing apparatus having a parallel execution function of a plurality of instructions. In this information processing apparatus of the conventional example, when access to a register overlaps before and after an instruction, a means for executing the instruction at high speed has been proposed. A method is adopted in which the instruction execution speed is increased by decoding the register dependency and temporarily changing the register in response to a register conflict condition. However, in order to change the registers in this way, a complicated decoder is required, and therefore, in reality, it is not possible to obtain a sufficiently high speed processing.

[0004]

In the above-described conventional data processing device, when an instruction having register dependencies before and after execution is executed, the dependency relationships of the registers used in the preceding and following instructions become clear in advance. Nevertheless, in the control unit, a decoder for comparing and collating the register storing the designated number of the register used in the immediately preceding instruction with the designated number and the designated number of the register used in the immediately following instruction. Both are required, and the circuit configuration is enlarged, which is one of the problems in increasing the processing speed.

[0005]

A data processing device according to a first aspect of the present invention comprises a data storage means having a plurality of registers for writing arithmetic processing data executed corresponding to a plurality of instructions,
Arithmetic means having a data input terminal corresponding to each operand of the plurality of instructions, receiving data input corresponding to each of the plurality of instructions to execute arithmetic processing, and output predetermined arithmetic processing data; The data output from the data storage means and the arithmetic processing data output from the arithmetic means are input, these data and arithmetic processing data are selected by a predetermined control signal, and output as input data to the arithmetic means. And a specific function of retaining, as additional information to the operands of the plurality of instructions, specific information indicating a dependency relationship corresponding to instructions before and after the data to be processed in advance, and the additional information. At least, and a data selection control means for generating and outputting the control signal.

In the first invention, the data selection control means decodes an instruction register including bit information defined as the additional information and an instruction output from the instruction register, and outputs the control signal. And a decoder for generating and outputting the signal. The signal selecting means may be composed of a plurality of signal selecting circuits corresponding to the operands of the plurality of instructions, and the signal selecting control means may include: The output control signal may be formed by a plurality of control signals corresponding to the plurality of signal selection circuits.

The data processing apparatus of the second invention corresponds to a first data storage means for storing predetermined data, data output from the first data storage means, and a plurality of instructions. Second data storage means having a plurality of registers for writing arithmetic processing data to be executed, and a data input terminal corresponding to each operand of the plurality of instructions, and a data input corresponding to each of the plurality of instructions are provided. An arithmetic means for receiving and executing arithmetic processing to output predetermined arithmetic processing data, data output from the first and second data storage means, and arithmetic processing data output from the arithmetic means. First signal selecting means for inputting and selecting these data and arithmetic processing data by a predetermined first control signal and outputting as the input data to the arithmetic means; The data output from the second data storage means and the arithmetic processing data output from the arithmetic means are input, and these data and arithmetic processing data are selected by a predetermined second control signal. Second signal selecting means for outputting as input data to the data storing means, and specific information indicating a dependency relationship corresponding to instructions before and after the data to be subjected to arithmetic processing in advance of the plurality of instructions. Data selection control means having a specific function of holding as additional information for the operand and generating and outputting the first and second control signals by referring to the additional information. Is characterized by.

In the second invention, the data selection control means decodes an instruction register including bit information defined as the additional information and an instruction output from the instruction register, and outputs the first register. And a decoder for generating and outputting a second control signal, and the first signal selecting means includes a plurality of signal selecting circuits corresponding to operands of the plurality of instructions. The first control signal configured and output from the data selection control means may be formed by a plurality of control signals corresponding to the plurality of signal selection circuits.

[0009]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the first exemplary embodiment of the present invention.

FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in FIG. 1, in the present embodiment, an instruction including a register file 11 including a plurality of registers in which execution results of instructions are written, signal selection circuits 12 and 13, an arithmetic unit 14, and an additional bit 18. The control unit 17 includes a register 15 and a decoder 16.

In FIG. 1, the operation output of the register file 11 is input to the signal selection circuits 12 and 13, respectively. On the other hand, the operation output output from the operation unit 14 is input to the register file 11 and
The signal is also input to these signal selection circuits 12 and 13, and the decoder 16 included in the control unit 17 respectively.
These signal selection circuits 12 and 13 are controlled by the control signals 101 and 102 output from
Operation output of the register file 11 or operation unit 14
One of the operation outputs of the operation outputs is selected and output, and is input to the input side of the input A or the input B corresponding to the two-input operand of the operation unit 14. In this case, the following four combinations exist in the selection method of the input A or the input B corresponding to the two-input operand in the arithmetic unit 14.

[1] When the operation output of the register file 11 is input to both the input A and the input B.

[2] When the operation output of the operation unit 14 is input to the input A and the operation output of the register file 11 is input to the input B.

[3] When the operation output of the register file 11 is input to the input A and the operation output of the operation unit 14 is input to the input B.

[4] The operation output of the operator 14 is input to both the input A and the input B.

Here, the control signal 10 input from the control section 17 to the signal selection circuits 12 and 13 respectively.
When the logical levels of 1 and 102 are set to the “0” level when the arithmetic output of the register file 11 is selected by these control signals and the “1” level when the arithmetic output of the arithmetic unit 14 is selected, In the case of the above [1], the control signals 101 and 102 output from the control unit 117 and input to the signal selection circuits 12 and 13, respectively, are in a combined state of “0” level. Similarly, in the case of the above [2], the signal selection circuit 1
The control signal 101 input to 2 is a combination state of "1" level, and the control signal 102 input to the signal selection circuit 13 is a combination state of "0" level. In the case of the above [3], the signal selection circuit 12 The control signal 101 input to the signal is in a combination state of “0” level, and the control signal 102 input to the signal selection circuit 13 is in a combination state of “1” level. In the case of the above [4], signal selection is performed. The control signals 101 and 102 input to the circuits 12 and 13 are both in a combination state of "1" level. That is, the signal selection circuit 1
Control signals 101 and 102 input to 2 and 13
By connecting them, the above [1],
The control signals corresponding to the four cases of [2], [3] and [4] are “00”, “01” and “1”, respectively.
It can be expressed as a 2-bit data signal of "0" and "11". Therefore, when assembling or compiling the instruction code, the dependency relationship between the preceding and following instructions is determined in advance, and the above control signal 101/102 is obtained. By providing the 2-bit numerical value to be formed as an additional bit 18 in the operand of the instruction in the instruction register 15, it becomes possible to perform a signal selection control action on the signal selection circuits 12 and 13, and thereby, it is possible to perform the signal selection control operations before and after the conventional example. The register and decoder required for checking the register dependency in the instruction are not required, the configuration of the decoder is simplified as compared with the related art, and the processing speed can be increased.

Next, a second embodiment of the present invention will be described. FIG. 2 is a block diagram showing the configuration of the second embodiment. As shown in FIG. 2, this embodiment is
A plurality of registers (R0-R) in which the execution results of instructions are written
Register file 21 including 3) and signal selection circuit 2
2, 23 and 27, a calculator 24, a memory 28,
An instruction register 25 including an additional bit 30 and a control unit 29 including a decoder 26 are provided. As is clear from comparison with FIG. 1, in the present embodiment, a memory 28 and a signal selection circuit 27 corresponding to the memory 28 are newly added.

In FIG. 2, the data output of the register file 21 is the signal selection circuits 22, 23 and 2 respectively.
7 is input. On the other hand, the arithmetic output data output from the arithmetic unit 24 is input to the register file 21 and at the same time, the signal selection circuits 22, 23 and 2 described above are input.
It is also entered for 7. Further, the data output from the memory 28 is input to the register file 21 and the signal selection circuits 22, 23 and 27 as in the case of the operation output data of the arithmetic unit 24. Further, the control signals 101/102/103 output from the decoder 26 included in the control unit 29 are input to the corresponding signal selection circuits 22, 23 and 27, respectively, and controlled by the control signals 101 and 102, From the signal selection circuits 22 and 23, one of the output data from the register file 11, the operation output data of the arithmetic unit 24 or the data output from the memory 28 is selected, and the two inputs of the arithmetic unit 24 are selected. Is input to the input side of input A or input B corresponding to the operand of
Further, under the control of the control signal 103, the signal selection circuit 27 outputs the output data from the register file 21,
Any one of the operation output data of the calculator 24 and the data output from the memory 28 is selected, input to the memory 28 and stored therein. The control signal 1
01/102/103 is the data output from the instruction register 25 in the control unit 29, which is decoded and generated in the decoder 26 in the same manner as in the first embodiment.

In the present embodiment, when an instruction having a register dependency before and after is executed, there are the following nine methods for selecting the input A or the input B corresponding to the 2-input operand to the arithmetic unit 24. There are combinations of.

[1] The output data of the register file 21 is input to both the input A and the input B.

[2] When the operation output data of the arithmetic unit 24 is input to the input A and the output data of the register file 21 is input to the input B.

[3] When the output data of the register file 21 is input to the input A and the operation output data of the arithmetic unit 24 is input to the input B.

[4] When the operation output data of the operator 24 is input to both the input A and the input B.

[5] The output data of the memory 28 is the input A
And when input is made to both input B.

[6] The output data of the memory 28 is input to the input A, and the output data of the register file 21 is input B.
If entered in.

[7] When the output data of the memory 28 is input to the input A and the operation output data of the arithmetic unit 24 is input to the input B.

[8] When the operation output data of the operation unit 24 is input to the input A and the output data of the memory 28 is input to the input B.

[9] The output data of the register file 21 is input to the input A, and the output data of the memory 28 is input B.
If entered in.

There are the following three combinations for the data input to the memory 28 selected by the signal selection circuit 27.

[10] When the output data of the register file 21 is input.

[11] When the operation output data of the multiplier 24 is input.

[12] When the output data of the memory 28 is input.

Therefore, the signal selection circuits 22, 23 and 2
Control signals 101 and 102 respectively input to
There are a total of 12 combinations in the combinations of and. As the control signal input to each of these signal selection circuits, the control signal corresponding to the selection of the operation output data from the operation unit 24 is "100", and the register file 21
The control signal corresponding to the selection of the output data from
0 "and the control signal corresponding to the selection of the output data from the memory 28 is" 001 ", in the case of the above [1], the control signal 10 for the signal selection circuits 22 and 23 is
Both 1 and 102 may be set to “010”. In the case of the above [2], the control signal 101 to the signal selection circuit 22 is set to “100” and the control signal 102 to the signal selection circuit 23 is set to “010”, In the case of the above [3], the control signal 101 for the signal selection circuit 22 is set to "010",
The control signal 102 for the signal selection circuit 23 is set to "100".
In the case of the above [4], the control signals 101 and 102 for the signal selection circuits 22 and 23 are both set to "1".
00 ", and in the case of the above [5], the signal selection circuit 22
In the case of the above [6], the control signals 101 and 102 for the signals 23 and 23 are both "001", the control signal 101 for the signal selection circuit 22 is "001", and the control signal 102 for the signal selection circuit 23 is "010". age,
In the case of [7] above, the control signal 101 for the signal selection circuit 22 is set to "001", and the control signal 102 for the signal selection circuit 23 is set to "100". In the case of [8] above, the control signal 101 to the signal selection circuit 22 is set. Set the control signal 101 to “10
0 ”, the control signal 102 for the signal selection circuit 23 is set to“ 0 ”.
01 ", and in the case of the above [9], the signal selection circuit 22
Control signal 101 for "010", signal selection circuit 2
The control signal 102 for 3 may be set to “001”.

In the case of the above [10],
The control signal 103 to the selection circuit 27 is "010", the control signal 103 to the selection circuit 27 is "100" in the case of [11], and the control signal 103 to the selection circuit 27 is in the case of [12]. Should be “001”.

Therefore, by providing 9-bit control signal selection bits including the above "100", "010" and "001" as additional bits in the operand of the instruction included in the instruction register 25, the signal selection is performed. Circuit 2
The selection control action on 2, 23 and 27 is carried out smoothly. As a result, as in the case of the above-described first embodiment, the registers and decoders required for checking the register dependency in the preceding and following instructions in the conventional example are unnecessary, and the configuration of the decoder can be compared with the conventional one. Therefore, the processing speed can be increased.

[0036]

As described above, according to the present invention, the dependency relationship between the instruction before and after the data to be processed is
By including it as an additional bit in a part of the operand of the instruction, it becomes possible to eliminate the need for a decoder and a register having a dependency relationship with the registers before and after the execution of the instruction, and the circuit configuration is simplified. With
The instruction execution time can be shortened, and the processing speed can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

11, 21, 31 Register file 12, 13, 22, 23, 27, 32, 33 Signal selection circuit 14, 24, 34 Operation unit 15, 25, 35 Instruction register 16, 26, 36, 38 Decoder 17, 29, 39 Control unit 18, 30 Additional bits 28 Memory 37 Registers 101 to 103 Control signals

Claims (6)

[Claims] 1. A data storage unit having a plurality of registers for writing operation processing data to be executed in response to a plurality of instructions, and a data input terminal corresponding to each operand of the plurality of instructions. Processing unit for receiving data input corresponding to each instruction of (1) and executing arithmetic processing to output predetermined arithmetic processing data, data output from the data storage unit, and arithmetic processing output from the arithmetic unit And a signal selection means for inputting data, selecting these data and arithmetic processing data by a predetermined control signal, and outputting as input data to the arithmetic means, and a command before and after the data to be arithmetic processing target in advance. It has a specific function of holding specific information indicating the corresponding dependency as additional information to the operands of the plurality of instructions,
A data processing device comprising at least data selection control means for generating and outputting the control signal with reference to the additional information. 2. The data selection control means decodes an instruction register including specific bit information defined as the additional information, and an instruction output from the instruction register,
The data processing device according to claim 1, further comprising: a decoder that generates and outputs the control signal. 3. The signal selecting means is composed of a plurality of signal selecting circuits corresponding to the operands of the plurality of instructions, and the control signal output from the data selection controlling means is the plurality of signal selecting circuits. 2. The data processing device according to claim 1, which is formed by a plurality of control signals corresponding to. 4. A plurality of first data storage means for storing predetermined data, data output from the first data storage means, and a plurality of write operation data to be executed corresponding to a plurality of instructions. Second data storage means having a register and a data input terminal corresponding to each operand of the plurality of instructions, receiving data input corresponding to each of the plurality of instructions, executing arithmetic processing, and predetermined The arithmetic processing means for outputting the arithmetic processing data, the data output from the first and second data storage means, and the arithmetic processing data output from the arithmetic means are input, and the data and the arithmetic processing are performed. First signal selecting means for selecting data by a predetermined first control signal and outputting it as input data to the arithmetic means, and output from the first and second data storing means. Data and arithmetic processing data output from the arithmetic means are input, these data and arithmetic processing data are selected by a predetermined second control signal, and output as input data to the first data storage means. And a specific function of holding, as additional information to the operands of the plurality of instructions, specific information indicating the dependency relationship indicating the dependency relationship corresponding to the instruction before and after the data to be processed in advance. And a data selection control means for generating and outputting the first and second control signals with reference to the additional information, and a data processing device comprising at least: 5. The data selection control means decodes an instruction register including specific bit information defined as the additional information, and an instruction output from the instruction register,
The data processing device according to claim 4, further comprising: a decoder that generates and outputs the first and second control signals. 6. The first signal selection means comprises a plurality of signal selection circuits corresponding to the operands of the plurality of instructions, and the first control signal output from the data selection control means comprises: The data processing device according to claim 4, wherein the data processing device is formed by a plurality of control signals corresponding to the plurality of signal selection circuits.