JPH09261509A - Speed modulation circuit - Google Patents

Speed modulation circuit

Info

Publication number
JPH09261509A
JPH09261509A JP7269096A JP7269096A JPH09261509A JP H09261509 A JPH09261509 A JP H09261509A JP 7269096 A JP7269096 A JP 7269096A JP 7269096 A JP7269096 A JP 7269096A JP H09261509 A JPH09261509 A JP H09261509A
Authority
JP
Japan
Prior art keywords
circuit
speed modulation
modulation circuit
input
velocity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7269096A
Other languages
Japanese (ja)
Inventor
Yoshio Kawasaki
善夫 川▲さき▼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7269096A priority Critical patent/JPH09261509A/en
Publication of JPH09261509A publication Critical patent/JPH09261509A/en
Pending legal-status Critical Current

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  • Details Of Television Scanning (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a circuit with which the degradation of picture quality can be prevented by operating a speed modulation circuit corresponding to a noise produced in a TV receiver when an RF input electric field is lowered by providing a video input level detection circuit and a variable amplifier circuit. SOLUTION: When remarkable video amplitude is inputted to a differentiation circuit like a studio program, this amplitude is simultaneously inputted to an input level detection circuit 7 as well. A variable amplifier circuit 3 is controlled corresponding to this input level and operated so as to decrease the amplification gain of the variable amplifier circuit 3 in the case of large input amplitude but operated so as to increase the amplification gain of the variable amplifier circuit 3 in the case of small amplitude. As a result, concerning an image like the studio program, the effect of the speed modulation circuit is lowered but in any other video signal, the effect of the speed modulation circuit is improved and natural picture quality can be provided. When the speed modulation circuit is operated, the noise on the screen is made much more conspicuous. In this case, the operation of the variable amplifier circuit is stopped by operating an RF input detection circuit and the speed modulation circuit is stopped.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明はテレビジョン受像機
の速度変調回路に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speed modulation circuit for a television receiver.

【0002】[0002]

【従来の技術】従来、速度変調回路としては、例えば特
開昭63−164765号公報に記載されたものが知ら
れている。図3に従来のテレビジョン受像機の速度変調
回路を示す。
2. Description of the Related Art Conventionally, as a speed modulation circuit, for example, one described in Japanese Patent Laid-Open No. 63-164765 is known. FIG. 3 shows a speed modulation circuit of a conventional television receiver.

【0003】符号41は映像入力端子、42は微分回
路、43は映像増幅回路、44は出力回路、45は速度
変調コイルで構成されている。
Reference numeral 41 is a video input terminal, 42 is a differentiating circuit, 43 is a video amplifying circuit, 44 is an output circuit, and 45 is a velocity modulation coil.

【0004】[0004]

【発明が解決しようとする課題】上記従来の速度変調回
路においては、入力映像信号の振幅に比例した動作が行
われ、速度変調コイルに電流が流れることになる。した
がって、映像信号の振幅が大の場合その効果が大きく、
映像信号の振幅小の場合効果が少なくなり、映像の輪郭
尖鋭化が入力映像信号の振幅によって変化し、自然な画
質が損なわれることとなる。
In the conventional speed modulation circuit described above, an operation proportional to the amplitude of the input video signal is performed, and a current flows through the speed modulation coil. Therefore, when the amplitude of the video signal is large, its effect is large,
If the amplitude of the video signal is small, the effect becomes small, and the sharpening of the contour of the video changes depending on the amplitude of the input video signal, and the natural image quality is impaired.

【0005】また、RF入力電界が低下すると映像信号
のなかに含まれるノイズ成分が増加し、ノイズ成分によ
って速度変調回路が動作し、画質感が損なわれることと
なる。
Further, when the RF input electric field decreases, the noise component contained in the video signal increases, the speed modulation circuit operates due to the noise component, and the image quality is impaired.

【0006】本発明はRF入力電界が低下したとき、テ
レビジョン受像機内で発生するノイズで速度変調回路が
動作し、画質が劣化するのを防止することを目的とす
る。
It is an object of the present invention to prevent the image quality from deteriorating due to the operation of the speed modulation circuit due to the noise generated in the television receiver when the RF input electric field is lowered.

【0007】[0007]

【課題を解決するための手段】この課題を解決するため
に本発明は、 (1)映像信号入力レベル検出回路、可変増幅回路を備
えた構成 (2)(1)の構成にさらにRF入力電界検出回路を加
えた構成 (3)映像信号のノイズレベルを検出する回路を備えた
構成
In order to solve this problem, the present invention provides (1) a configuration including a video signal input level detection circuit and a variable amplification circuit. (2) An RF input electric field in addition to the configuration of (1). Configuration with addition of detection circuit (3) Configuration with circuit for detecting noise level of video signal

【0008】(4)RF入力電界検出回路と、映像信号
のノイズレベル検出回路信号とを合成した構成。とした
ものである。
(4) A configuration in which the RF input electric field detection circuit and the noise level detection circuit signal of the video signal are combined. It is what it was.

【0009】上記構成により、速度変調回路による不自
然な画質感をなくすることができる。
With the above arrangement, it is possible to eliminate an unnatural image quality feeling due to the speed modulation circuit.

【0010】[0010]

【発明の実施の形態】本発明の請求項1に記載の発明
は、ブラウン管の速度変調コイルに映像信号から合成し
た微分電流を流し、走査速度を変調して映像の輪郭を尖
鋭化する速度変調回路において、速度変調回路の入力さ
れる映像信号レベルを検出し、入力レベルが大きい場合
は速度変調回路の利得を下げ、入力レベルが小さい場合
は速度変調回路の利得をあげる映像入力レベル検出回路
と、可変増幅回路を有した速度変調装置としたもので、
ある一定の電界入力に達したとき速度変調の作動を停止
させ、速度変調回路による不自然な画質感をなくするこ
とができる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is a velocity modulation for causing a differential current synthesized from an image signal to flow in a velocity modulation coil of a cathode ray tube to modulate a scanning velocity to sharpen an outline of an image. And a video input level detection circuit that detects the video signal level input to the speed modulation circuit, lowers the gain of the speed modulation circuit when the input level is high, and increases the gain of the speed modulation circuit when the input level is low. , A speed modulator having a variable amplifier circuit,
When a certain constant electric field input is reached, the speed modulation operation is stopped, and the unnatural image quality of the speed modulation circuit can be eliminated.

【0011】さらに、本発明の請求項2に記載の発明
は、ブラウン管の速度変調コイルに映像信号から合成し
た微分電流を流し、走査速度を変調して映像の輪郭を尖
鋭化する速度変調回路において、RFからの入力電界を検
出する回路を用い、RFからの入力電界がある一定以下
の電界になった場合、速度変調回路を停止させる回路を
有した速度変調回路装置としたもので、ある一定の電界
入力に達したとき速度変調の作動を停止させる。
Further, the invention according to claim 2 of the present invention is a velocity modulation circuit for flowing a differential current synthesized from an image signal to a velocity modulation coil of a cathode ray tube to modulate a scanning velocity to sharpen an outline of an image. , A circuit for detecting an input electric field from RF is used, and when the electric field input from RF becomes a certain electric field or less, a speed modulation circuit device having a circuit for stopping the speed modulation circuit is provided. When the electric field input of is reached, the speed modulation is stopped.

【0012】本発明の請求項3に記載の発明は、ブラウ
ン管の速度変調コイルに映像信号から合成した微分電流
を流し、走査速度を変調して映像の輪郭を尖鋭化する速
度変調回路において、映像信号のノイズ成分を検出し、
ノイズ成分がある一定以上の割合になった場合、速度変
調回路を停止させる回路を有した速度変調装置としたも
ので、一定以上のノイズレベルに達したとき速度変調の
作動を停止させる。
According to a third aspect of the present invention, in a speed modulation circuit for applying a differential current synthesized from a video signal to a speed modulation coil of a cathode ray tube to modulate a scanning speed to sharpen an edge of an image, Detect the noise component of the signal,
When the noise component exceeds a certain ratio, the velocity modulation device has a circuit that stops the velocity modulation circuit. When the noise level reaches a certain level or more, the velocity modulation operation is stopped.

【0013】本発明の請求項4に記載の発明は、ブラウ
ン管の速度変調コイルに映像信号から合成した微分電流
を流し、走査速度を変調して映像の輪郭を尖鋭化する速
度変調回路において、映像信号のノイズ成分を検出し、
ノイズ成分がある一定以上の割合になった場合、及び、
RFからの入力電界がある一定以下の電界になった場
合、各々の検出信号を合成し、速度変調回路を停止させ
る回路を有した速度変調装置としたもので、速度変調の
作動により不自然な画質をなくし、より自然な画質を使
用者に提供するという作用を有する。
According to a fourth aspect of the present invention, in a speed modulation circuit for applying a differential current synthesized from a video signal to a speed modulation coil of a cathode ray tube to modulate a scanning speed to sharpen an outline of a video, Detect the noise component of the signal,
When the noise component exceeds a certain ratio, and
When the electric field input from RF becomes a certain electric field or less, the detection signals are combined and the speed modulation device is provided with a circuit for stopping the speed modulation circuit, which is unnatural due to the operation of the speed modulation. It has the effect of eliminating the image quality and providing a more natural image quality to the user.

【0014】以下、本発明の実施の形態における速度変
調回路について、図面を用いて説明する。
The speed modulation circuit according to the embodiment of the present invention will be described below with reference to the drawings.

【0015】(実施の形態1)図1は本発明の請求項1
における速度変調回路のブロック構成図を示す。図1に
おいて、符号1は映像入力端子、2は微分回路、3は可
変増幅回路、4は増幅回路、5は出力回路、6は速度変
調コイル、7は入力レベル検出回路である。
(Embodiment 1) FIG. 1 shows the first aspect of the present invention.
2 is a block diagram of the speed modulation circuit in FIG. In FIG. 1, reference numeral 1 is a video input terminal, 2 is a differentiation circuit, 3 is a variable amplification circuit, 4 is an amplification circuit, 5 is an output circuit, 6 is a speed modulation coil, and 7 is an input level detection circuit.

【0016】以上のように構成されたテレビジョン受像
機の速度変調回路について、その動作を説明する。
The operation of the speed modulation circuit of the television receiver configured as described above will be described.

【0017】例えば、スタジオ番組のように大きな映像
振幅が微分回路2に入力された場合、入力レベル検出回
路7にも同時に入力される。この入力レベルに応じて可
変増幅回路3を制御し、入力振幅大の場合は可変増幅回
路の増幅利得を下げ、入力振幅小の場合は可変増幅回路
の増幅利得を上げるように作動する。
For example, when a large image amplitude such as a studio program is input to the differentiating circuit 2, it is also input to the input level detecting circuit 7. The variable amplifier circuit 3 is controlled in accordance with this input level, and when the input amplitude is large, the amplification gain of the variable amplifier circuit is reduced, and when the input amplitude is small, the amplification gain of the variable amplifier circuit is increased.

【0018】この結果、スタジオ番組のような映像では
速度変調回路の効果が低下し、そうではない映像信号時
は速度変調回路の効果が増加し、自然な画質を得ること
ができる。
As a result, the effect of the speed modulation circuit is reduced in the case of a video such as a studio program, and the effect of the speed modulation circuit is increased in the case of a video signal which is not so that a natural image quality can be obtained.

【0019】(実施の形態1)次に、本発明のの実施の
形態について、図2を用いて説明する。
(Embodiment 1) Next, an embodiment of the present invention will be described with reference to FIG.

【0020】(実施の形態2)図2は本発明の請求項2
におけるテレビジョン受像機の速度変調回路のブロック
構成図を示す。図2において、符号21は映像入力端
子、22は微分回路、23は可変増幅回路、24は増幅
回路、25は出力回路、26は速度変調コイル、27は
入力レベル検出回路、28はRF入力検出回路、29は
RF入力検出信号端子である。
(Embodiment 2) FIG. 2 shows the second aspect of the present invention.
2 is a block diagram of a speed modulation circuit of the television receiver in FIG. In FIG. 2, reference numeral 21 is a video input terminal, 22 is a differentiation circuit, 23 is a variable amplification circuit, 24 is an amplification circuit, 25 is an output circuit, 26 is a speed modulation coil, 27 is an input level detection circuit, and 28 is an RF input detection. A circuit, 29 is an RF input detection signal terminal.

【0021】以上のように構成されたテレビジョン受像
機の速度変調回路について図2を用いてその動作を説明
する。
The operation of the speed modulation circuit of the television receiver configured as described above will be described with reference to FIG.

【0022】RF入力電界が55dB程度まで低下する
と、映像信号の中にノイズ成分が混入しテレビジョンの
画面上にもノイズが目立ってくる。
When the RF input electric field is lowered to about 55 dB, noise components are mixed in the video signal, and noise is noticeable on the screen of the television.

【0023】速度変調回路が作動すると、より一層、画
面上のノイズが目立つ。このような場合、RF入力検出
信号端子29に入力された信号(例えば、AGC 電圧
等)で、RF入力検出回路28が作動し、可変増幅回路
23の動作を止め、速度変調回路が停止する。
When the speed modulation circuit operates, noise on the screen becomes more noticeable. In such a case, the signal input to the RF input detection signal terminal 29 (eg, AGC voltage or the like) activates the RF input detection circuit 28, stops the operation of the variable amplification circuit 23, and stops the speed modulation circuit.

【0024】以上により、RF入力電界が低下したと
き、速度変調回路を停止させ、画面上に発生するノイズ
を軽減し、自然な画質を提供することができる。
As described above, when the RF input electric field is lowered, the speed modulation circuit is stopped, noise generated on the screen is reduced, and a natural image quality can be provided.

【0025】(実施の形態3)図3は本発明の請求項3
におけるテレビジョン受像機の速度変調回路のブロック
構成図を示す。図3において、31は映像入力端子、3
2は微分回路、33は可変増幅回路、34は増幅回路、
35は出力回路、36は速度変調コイル、37は入力レ
ベル検出回路、38は映像信号ノイズレベル検出回路で
ある。
(Embodiment 3) FIG. 3 shows a third embodiment of the present invention.
2 is a block diagram of a speed modulation circuit of the television receiver in FIG. In FIG. 3, 31 is a video input terminal and 3
2 is a differentiation circuit, 33 is a variable amplification circuit, 34 is an amplification circuit,
Reference numeral 35 is an output circuit, 36 is a velocity modulation coil, 37 is an input level detection circuit, and 38 is a video signal noise level detection circuit.

【0026】RF入力電界が55dB程度まで低下する
と、映像信号の中にノイズ成分が混入しテビジョンの画
面上にもノイズが目立ってくる。速度変調回路が作動す
ると、より一層、画面上のノイズが目立つ。このような
場合、映像信号ノイズレベル検出回路38が作動し、速
度変調回路を停止させ、画面上に発生するノイズを軽減
し、自然然な画質を提供することができる。
When the RF input electric field is lowered to about 55 dB, noise components are mixed in the image signal, and noise is conspicuous on the screen of the television. When the speed modulation circuit operates, noise on the screen becomes more noticeable. In such a case, the video signal noise level detection circuit 38 operates, the speed modulation circuit is stopped, noise generated on the screen is reduced, and a natural image quality can be provided.

【0027】(実施の形態4)この場合は、実施の形態
2と、実施の形態3で説明をしたRF入力検出回路と、
映像信号ノイズレベル検出回路とを合成し作動させるも
のである。
(Fourth Embodiment) In this case, the second embodiment and the RF input detection circuit described in the third embodiment,
The image signal noise level detection circuit is combined and operated.

【0028】RF入力検出回路と、映像信号ノイズレベ
ル検出回路とを合成することにより、誤動作の無い安定
した画質を提供することができる。
By combining the RF input detection circuit and the video signal noise level detection circuit, stable image quality without malfunction can be provided.

【0029】[0029]

【発明の効果】以上のように本発明によれば、映像入力
の振幅レベルによって速度変調の効果を変化させ、より
自然な画質を提供し、更に、RF入力が低下し、ノイズ
が目立つ状況に於いては速度変調動作を停止させ、画面
上に発生するノイズを軽減し、自然な画質を再現し、使
用者に満足な映像を提供するものである。
As described above, according to the present invention, the effect of speed modulation is changed according to the amplitude level of the video input to provide a more natural image quality, and further, the RF input is lowered and the noise is conspicuous. In that case, the speed modulation operation is stopped, noise generated on the screen is reduced, natural image quality is reproduced, and a satisfactory image is provided to the user.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の請求項1の一実施の形態によるテレビ
ジョン受像機の速度変調回路のブロック構成図
FIG. 1 is a block configuration diagram of a speed modulation circuit of a television receiver according to an embodiment of claim 1 of the present invention.

【図2】本発明の請求項2の一実施の形態によるテレビ
ジョン受像機の速度変調回路のブロック構成図
FIG. 2 is a block configuration diagram of a speed modulation circuit of a television receiver according to an embodiment of claim 2 of the present invention.

【図3】本発明の請求項3の一実施の形態によるテレビ
ジョン受像機の速度変調回路のブロック構成図
FIG. 3 is a block configuration diagram of a speed modulation circuit of a television receiver according to an embodiment of claim 3 of the present invention.

【図4】従来のテレビジョン受像機の速度変調回路のブ
ロック構成図
FIG. 4 is a block configuration diagram of a speed modulation circuit of a conventional television receiver.

【符号の説明】[Explanation of symbols]

1,21,31 映像入力端子 2,22,32 微分回路 3,23,33 可変増幅回路 4,24,34 増幅回路 5,25,35 出力回路 6,26,36 速度変調コイル 7,27,37 入力レベル検出回路 28 RF入力電界検出回路 29 RF入力検出信号端子 38 映像信号ノイズレベル検出回路 1, 21, 31 Video input terminal 2, 22, 32 Differentiation circuit 3, 23, 33 Variable amplification circuit 4, 24, 34 Amplification circuit 5, 25, 35 Output circuit 6, 26, 36 Speed modulation coil 7, 27, 37 Input level detection circuit 28 RF input electric field detection circuit 29 RF input detection signal terminal 38 Video signal noise level detection circuit

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 ブラウン管の速度変調コイルに映像信号
から合成した微分電流を流し、走査速度を変調して映像
の輪郭を尖鋭化する速度変調回路において、速度変調回
路の入力される映像信号レベルを検出し、入力レベルが
大きい場合は速度変調回路の利得を下げ、入力レベルが
小さい場合は速度変調回路の利得をあげる映像入力レベ
ル検出回路と、可変増幅回路を有した速度変調回路。
1. A speed modulation circuit for causing a differential current synthesized from a video signal to flow in a speed modulation coil of a cathode ray tube to modulate a scanning speed to sharpen an outline of a video, and a video signal level input to the speed modulation circuit is changed. A speed modulation circuit that has a variable amplification circuit and a video input level detection circuit that detects and reduces the gain of the speed modulation circuit when the input level is high, and increases the gain of the speed modulation circuit when the input level is low.
【請求項2】 ブラウン管の速度変調コイルに映像信号
から合成した微分電流を流し、走査速度を変調して映像
の輪郭を尖鋭化する速度変調回路において、RFからの
入力電界を検出する回路を用い、RFからの入力電界が
ある一定以下の電界になった場合、速度変調回路を停止
させる回路を有した速度変調回路。
2. A circuit for detecting an input electric field from RF is used in a velocity modulation circuit for flowing a differential current synthesized from an image signal to a velocity modulation coil of a cathode ray tube to modulate a scanning velocity to sharpen an outline of an image. , A velocity modulation circuit having a circuit for stopping the velocity modulation circuit when the electric field input from RF becomes a certain electric field or less.
【請求項3】 ブラウン管の速度変調コイルに映像信号
から合成した微分電流を流し、走査速度を変調して映像
の輪郭を尖鋭化する速度変調回路において、映像信号の
ノイズ成分を検出し、ノイズ成分がある一定以上の割合
になった場合、速度変調回路を停止させる回路を有した
速度変調回路。
3. A noise component of a video signal is detected and detected in a velocity modulation circuit for flowing a differential current synthesized from a video signal to a velocity modulation coil of a cathode ray tube to modulate the scanning velocity to sharpen the contour of the image. A speed modulation circuit having a circuit for stopping the speed modulation circuit when the ratio exceeds a certain level.
【請求項4】 ブラウン管の速度変調コイルに映像信号
から合成した微分電流を流し、走査速度を変調して映像
の輪郭を尖鋭化する速度変調回路において、映像信号の
ノイズ成分を検出し、ノイズ成分がある一定以上の割合
になった場合、またはRFからの入力電界がある一定以
下の電界になった場合のいずれか一方において、各々の
検出信号を合成し、速度変調回路を停止させる回路を有
した速度変調回路。
4. A noise component of a video signal is detected and detected in a velocity modulation circuit for flowing a differential current synthesized from a video signal to a velocity modulation coil of a cathode ray tube to modulate the scanning velocity to sharpen the contour of the image. There is a circuit for synthesizing each detection signal and stopping the speed modulation circuit when either the ratio exceeds a certain ratio or the electric field input from RF falls below a certain value. Speed modulation circuit.
JP7269096A 1996-03-27 1996-03-27 Speed modulation circuit Pending JPH09261509A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7269096A JPH09261509A (en) 1996-03-27 1996-03-27 Speed modulation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7269096A JPH09261509A (en) 1996-03-27 1996-03-27 Speed modulation circuit

Publications (1)

Publication Number Publication Date
JPH09261509A true JPH09261509A (en) 1997-10-03

Family

ID=13496625

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7269096A Pending JPH09261509A (en) 1996-03-27 1996-03-27 Speed modulation circuit

Country Status (1)

Country Link
JP (1) JPH09261509A (en)

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