JPH09261221A - Device for analyzing communication line data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To collect data in an actual line by recognizing the remote side frame signal of a large attenuation level by a remote side receiving circuit and a frame synchronizing circuit and amplifying it to the prescribed level thereby demodulating it. SOLUTION: When data of the communication line of a time dividing direction control system in TTC standard JT-961 is collected and analized, a loss level detecting part 205a detects a loss level being the decay quantity of an AMI signal and a remote and frame binarizing part 205b amplifies it, converts it into positive/negative binary value data AMI2P and AMI2N and outputs it in the receiving circuit 205 of the remote end side receiving circuit. The frame synchronizing circuit 206 supplies a near end side synchronizing signal, etc., to the receiving circuit 205 and outputs a demodulation frame data string after receiving positive/ negative binary value stream data AMI1P and AMI1N from the near end side receiving circuit and positive/negative binary value stream data AMI2P and AMI2N from the remoteend frame binarizing part 205b so as to execute a synchronizing processing.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to the TTC standard JT-G96.
1 Connect to a communication line (JT-G961 line) that uses the TCM (time division direction control) system (commonly called "ping-pong transmission system") of "ISDN basic access metallic subscriber line transmission system", collect line data, The present invention relates to a communication analysis device for performing analysis.

[0002]

2. Description of the Related Art The contents of the TTC standard JT-G961 are two-way transmission means on a two-line metallic subscriber transmission line, and include LT (Line Termination) and DSU or NT1.
It is a communication standard for a U-point subscriber line between (Network Termination), and it is described in JT-G961 of the TTC standard user / network interface document. Among these, the dynamic range of the received signal level is 0 dB to 37
It is a communication standard that can support a wide range of loss levels of dB or more. FIG. 6 shows the data sequence structure of the burst frame of this standard. The data sequence consists of LT or N from the beginning.
Frame word (FW) for synchronization with the transmission direction of T1
And CL channel, which is various communication status data,
It consists of a 2B + D channel data string of slots and a parity bit.

In recent years, digital communication networks have been developed along with the progress of the advanced information society, and in particular, Internet connection using ISDN line, PHS public network connection, etc. have been rapidly established.

In the ISDN line as described above, in the past, a terminal was mostly connected via a DSU to a subscriber line from a switching center of a telecommunication line facility operator, but recently, In order to reduce the price of terminals and PHS base stations, the number of cases in which a DSU is incorporated is increasing.

Up to now, when there is a transmission failure in the subscriber line,
A communication line data analysis device (common name: protocol, etc.) for collecting and analyzing data at the demarcation point between the telecommunication line equipment (switching station or subscriber line) and the terminal equipment (wiring equipment, DSU or terminal). There is no analyzer etc., so the basic interface or primary group interface used in the switching center, DSU or terminal, RS232C
In general-purpose serial interfaces such as, the verification was performed based on the indirect data collected by the communication line data analysis device.

However, when the telecommunication line facility operator such as the subscriber line is different from the terminal facility operator, it is necessary to isolate the fault at the demarcation point of responsibility. It keeps the state of connecting the call, such as a momentary disconnection of the subscriber line (a state where the line is not momentarily connected or the power is not provided), but causes an error in which the transmission data has an error, Since it may not be possible to verify with indirect data, a communication line data analysis device that enables data collection on the JT-G961 line has been earnestly desired.

Further, in a terminal or PHS base station with a built-in DSU, a connection circuit for connecting an existing communication line data analysis device and performing fault verification tends to be deleted for cost reduction. In development or maintenance,
There was a long-felt need for a communication line data analysis device that enables JT-G961 line data collection.

[0008]

However, when the above-mentioned JT-G961 line data is collected, there are the following problems.

NT1 (DSU or PHS base station) and L
In the start or stop procedure with T (Exchange), NT1
Since the state transition is performed by the change of the input impedance of the communication line data analysis device, it is necessary to increase the input impedance of the connection part of the communication line data analysis device so as not to adversely affect the transmission of the line when the communication line data analysis device is connected. There is.

The transmission system between NT1 and LT is the TCM system, and N is based on the reception timing of the transmission frame of LT.
Since T1 sends the frame, the LT frame and NT1
Frames alternate. The communication line data analysis device needs frame synchronization processing for both the LT frame and the NT1 frame in order to consider the frame delay due to the subscriber line or the like.

Further, since there is a subscriber line loss (loss of a signal transmitted through the subscriber line), the amplitude value of the frame signal received on the LT side or the NT1 side depends on the length of the subscriber line, etc. As shown in FIG. 5, both frame signal levels between LT and NT1 have a large difference depending on the connection point and the transmission line length. The communication line data analysis device must receive and process both frame signals of LT and NT1 having a large level difference alternately transmitted as shown in FIG.

An object of the present invention is to solve the above-mentioned problems and to provide a communication line data analysis device which enables data collection on the JT-G961 line.

[0013]

[Means for Solving the Problems] First, in order to solve the above problems, in the configuration of the present invention, the layer 1 frame processing is performed by receiving the AMI signal including the power supply voltage signal from the JT-G961 line. , CH data of layer 2 and later, and layer 1
In response to the signals from the JT-G961 line signal processing circuit 200 and the JT-G961 line signal processing circuit 200 which supply the state transition data to the HDLC monitor processing circuit 300 and the layer 1 state data to the data analysis device main body 400. , Process the input layer 1 status data, and add HD after layer 2
An HDLC monitor processing circuit 300 that performs LC frame processing and supplies monitor data to the data analysis apparatus main body, and JT
-Controls the G961 line signal processing circuit 200 and the HDLC monitor processing circuit 300, receives the layer 1 state data from the JT-G961 line signal processing circuit 200, displays the layer 1 state, and outputs from the HDLC monitor processing circuit 300. Upon receiving the monitor data, the HDLC frame data and the layer 1 state transition data are translated and displayed, and the data analysis apparatus main body 400 is configured to record the data on the recording medium (HDD or the like). This allows TTC standard JT-G961 "ISD
N basic access metallic subscriber line transmission system "TCM
In the communication line data analysis device 100 which is connected to the communication line of the time division direction control system and collects and analyzes this line data, the TTC capable of coping with the difference between both frame signal levels at the connection point on the LT side or the NT1 side. Realizes a communication line data analysis device of the standard JT-G961 standard.

The JT-G961 line signal processing circuit 200 receives the line signals L1 and L2 with a high input impedance, outputs an AMI signal that passes a predetermined band component, and supplies normal power, reverse power, or no power. Input stage 20 for outputting power supply state detection signals PSNOM, PSRVS of
1, a reception unit 1202 circuit, and a power feeding detection circuit 203
And receiving the AMI signal after filtering into a predetermined band component from the receiving unit 1202 circuit and converting it from the first frame on the near end side having a high signal level into binary value stream data AMI1P, AMI1N of positive / negative NRZ. The near-end side receiving circuit that outputs the signal is amplified by the receiving circuit 2204 and the positive / negative of the far-end side first frame after amplification corresponding to the loss level of the far-end side second frame with large subscriber line loss. Far-end side reception circuit for converting and outputting NRZ binary value stream data AMI1P, AMI1N: reception circuit 3205, and positive / negative NRZ binary value stream data AMI1P from the AMI signal of the near-end side first frame, Upon receiving AMI1N, 2 of positive / negative NRZ from the far-end frame 2 evolution unit 205b is received.
A frame synchronization circuit 206 that receives the binary stream data AMI2P 1 and AMI2N 2 and, after synchronizing each of them, outputs demodulated demodulated frame data strings NT1data and LTdata, and the demodulated frame data string NT1data,
Receiving LTdata, power supply state detection signals PSNOM, PSR
In response to VS, the layer 1 state transition detection circuit 207 for outputting the layer 1 state data for HDLC monitoring and the layer 1 state transition data and the demodulated frame data sequence NT1data, LTdata are received in accordance with the JT-G961 line standard. Upon receiving the power supply state detection signals PSNOM and PSRVS, JT-G96
Data channels B1ch, B2ch, and Dch of layer 2 or later that are descrambled based on the one-line standard
Is a monitor channel selection circuit 208 for extracting and outputting the data of the data channel corresponding to the output selection condition.

The input stage, the receiving section 1 circuit, and the power supply detecting circuit receive the line signals L1 and L2 and divide the voltage with a high resistance resistor divider (attenuator) so as not to affect the load on the connection line. , An input stage 20 having a HPF for cutting DC components and cutting low frequency components such as power supply hum
1 and a receiver 120 that receives a differential signal divided by the input stage 201 and filtered by the HPF by a differential amplifier, and outputs an AMI signal in which a predetermined band component is passed by the BPF.
The differential amplifier receives the differential signal divided by the two circuits and the input stage 201 by a differential amplifier, outputs a power supply voltage that is a direct current component, and uses a positive / negative comparator from this voltage signal to perform normal power supply, reverse power supply, or no power supply. A power supply detection circuit 20 that detects whether power is supplied and outputs power supply state detection signals PSNOM and PSRVS
There is a configuration means for setting 3.

Near-end side receiving circuit: The receiving circuit 2 204 receives an AMI signal after filtering into a predetermined band component from the receiving unit 1 202 circuit, and outputs a positive / positive signal from the near-end side first frame having a high signal level. There is a configuration means that is a comparator that outputs binary value stream data AMI1P 1 and AMI1N 2 of negative NRZ.

Far-end side receiving circuit: The receiving circuit 3 205 receives the AMI signal after filtering into a predetermined band component from the receiving unit 1 202 circuit, and outputs the second end-side second frame having a low signal level. The signal is converted into an absolute value signal by an absolute value amplifier, the absolute value signal is received, and the position of the far end side second frame signal is specified from the near end side first frame synchronization information obtained by the frame synchronization circuit 206, The far end side second
Hold the level of the frame signal with the peak hold circuit,
A loss level detection circuit that outputs loss level data obtained by digitally converting the held analog level signal, and a receiver 1
AM after filtering to a predetermined band component from the 202 circuit
Upon receiving the I signal, the far-end side signal amplifier amplifies it to a predetermined amplitude with a gain amplification factor corresponding to the loss level data, receives the amplified AMI signal, and outputs the positive / negative from the far-end side second frame. NRZ binary stream data AMI2P
, AMI2N output far-end frame 2 evolution unit 205
There is a configuration means designated as b.

As the far-end frame 2 evolution section 205b,
The far-end side signal amplifier receives the AMI signal obtained by amplifying the far-end side frame signal to a predetermined amplitude and converts it to an absolute value signal. A predetermined threshold value is generated from the holding peak hold circuit and the holding amplitude level, the AMI signal from the far end side signal amplifier is received at this threshold value, and binary value stream data AMI2P of positive / negative NRZ is received. , AMI2
There is a constituent means which is a comparator for converting to N and outputting.

The frame synchronization circuit 206 receives binary value stream data AMI1P and AMI1N of positive / negative NRZ from the AMI signal of the first frame of the near end side, and receives the positive / negative of the far end frame binary evolution section 205b. NRZ 2
Receiving the binary stream data AMI2P, AMI2N, the synchronized near-end first frame outputs the synchronized near-end sync signal, and the alternate near-end side first frame and the far-end side second frame are alternately output. The near-end / far-end frame switching circuit, the near-end synchronization signal, and the far-end receiving circuit: the far-end loss level data from the receiving circuit 3 205 is received to control the gain of the far-end signal amplifier. Then, based on the JT-G961 line standard, a binary frame stream data AMI1P, AMI1N or AMI2P of positive / negative NRZ on the near end side / far end side, which is a burst frame,
In response to the AMI2N, a line clock and line data are generated, the line clock is synchronized with the frame word FW for synchronization, LT or NT1 is specified from the bit information of this frame word, and the corresponding LT frame synchronization circuit / NT1 frame synchronization circuit is specified. Demodulated frame data sequence NT1dat demodulated from
There is a configuration means for outputting a and LTdata respectively.

In addition to the JT-G961 line signal processing circuit 200, the data channels B1ch and B2c from the monitor channel selection circuit 208 of the JT-G961 line signal processing circuit 200.
There is a configuration means for providing an audio monitor circuit 209 which receives h data, demodulates to PCM64K and outputs an audio signal.

Secondly, in order to solve the above problems, in the configuration of the present invention, the burst frame from two points from the connection line is the near-end first frame and the far-end second frame signal, the AMI differential signal L1. L2 and the power supply voltage are received by a high impedance circuit, one of the near-end side first frame signals having a high signal level is received, and one of the synchronization frame words FW of the JT-G961 standard corresponding to the communication standard is received. Outputting the first stream data in synchronization with the first frame,
Upon receiving the one first frame synchronization signal, the position of the other far end side second frame signal having a low signal level is specified,
The signal level is amplified to a predetermined level, and in response to this, the second stream data is output in synchronization with the other second frame in accordance with the communication standard, and the synchronized first frame and first frame are output. Receiving both stream data, it specifies the LT side or the NT1 side from the information data of the CL channel, outputs the layer 1 data, receives the layer 1 data, and performs data processing and translation processing of each layer. The data processing / translation unit outputs the data to the recording medium display unit.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to examples.

[0023]

1 is a block diagram showing an embodiment of a communication line data analyzing apparatus of the present invention. In the configuration example of the communication line data analysis device 100 of the present invention, a JT-G961 line signal processing circuit 200 and an HDLC monitor processing circuit 300 are provided.
And a data analysis device main body 400.

The JT-G961 line signal processing circuit 200 is a JT-G9
The signal of 61 lines is input, and the HDLC monitor processing circuit 300
, The CH data of layer 2 or higher and the layer 1 state transition data are output. In addition, the data analysis device main body 400
, The layer 1 status data is output. This JT-G96
An example of the internal configuration of the one-line signal processing circuit 200 includes an input stage 201, a receiving unit 1202 circuit, a power supply detecting circuit 203 as shown in FIG. 2, and a near-end side receiving circuit as shown in FIG.
Reception circuit 2 204, far-end side reception circuit: reception circuit 3 20
5, a frame synchronization circuit 206, and a layer 1 state transition detection circuit 207, a monitor channel selection circuit 208, and a voice monitor circuit 209 as shown in FIG.

The HDLC monitor processing circuit 300 outputs monitor data to the data analysis apparatus main body. The communication analysis device main body 400 is the JT-G961 line signal processing circuit 2
00 and the HDLC monitor processing circuit 300 are controlled.

The operation of the JT-G961 line signal processing circuit 200 in the communication line data analysis apparatus having the above configuration example will be described below.

Referring to FIG. This is JT-G961
It is an input part of the line signals L1 and L2 from the line, receives with a high impedance so as not to affect the line, outputs an AMI signal that passes a predetermined band component, and supplies normal power, reverse power, or no power. Power supply state detection signal PSN
Output OM and PSRVS.

Therefore, the input stage 201 is connected to the line signal L1,
L2 Each resistor divider and each H.
It is composed of PF and is divided by a high resistance resistor divider (attenuator) with a high input impedance so as not to affect the line, cuts DC components with HPF, cuts low frequency components such as power supply hum, and receives 1202, and a signal obtained by dividing the line signals L1 and L2 is supplied to the power supply detection circuit 2
03. The receiving unit 1202 receives the signal from the HPF by a differential amplifier, and further outputs an AMI signal in which a predetermined band component is passed by the BPF. The power feeding detection circuit 203 receives a signal from the resistance divider by a differential amplifier and compares the level of the power feeding voltage, which is a DC component, with a comparator of a positive / negative comparator to detect whether the power feeding is normal feeding or reverse feeding. Power supply state detection signal PSNO
Outputs M and PSRVS.

Next, FIG. 3 will be described. here,
Upon receiving the AMI signal from the input section, the near-end side first frame having a high signal level and the far-end side second frame having a large subscriber line loss are synchronized, and then both stream data are demodulated and output.

Therefore, near-end side receiving circuit: receiving circuit 22
In 04, receiving the analog AMI signal after filtering to the predetermined band component from the receiving unit 1202 circuit, the binary value stream data AMI1P, AMI1N of the positive / negative NRZ from the first frame at the near end side having a high signal level. Converted to and output.

Far-end side receiving circuit: In the receiving circuit 3 205, it is necessary to amplify the greatly attenuated AMI signal and then convert it into digital data. Therefore, the loss level detection unit 205a detects the loss level that is the attenuation amount, and the far-end frame binary evolution unit 205b amplifies the loss level to obtain positive / negative N.
RZ binary value data AMI2P, AMI2N are converted and output.

That is, the loss level detecting section 205a is composed of an absolute value amplifier, a peak hold circuit, and a loss level detecting circuit, and receives the filtered analog AMI signal into a predetermined band component from the receiving section 1202 circuit. Then, the absolute value amplifier converts the negative side of the AMI signal to positive. In response to this, the peak hold circuit causes the frame synchronization circuit 20 to
Based on the near-end side synchronization signal obtained in step 6, the signal level of the far-end side frame is held, and the level value of the subscriber line loss level data AD-converted by the loss level detection circuit is gain controlled by the frame synchronization circuit 206. Supply to.

The far-end frame binarization unit 205b comprises a far-end side signal amplifier, an absolute value amplifier, a peak hold circuit, a storage circuit, a comparison value generation circuit, and a comparator.
Receiving section 120 Receives the analog AMI signal from the circuit, receives the gain signal obtained by converting the loss level data obtained above by gain control, and amplifies the far end side frame signal to a predetermined level by the far end side signal amplifier. To do. Thereafter, the near-end side receiving circuit: the binary value data AMI2P, AMI of the positive / negative NRZ is similar to the operation of the receiving circuit 2 204.
Convert to 2N and output. A specific example of this portion will be described in detail below. The far-end side signal amplifier receives the signal obtained by amplifying the far-end side frame signal to a predetermined level, the negative value of the AMI signal is converted to positive by the absolute value amplifier, and the near-end side synchronizing signal is converted by the peak hold circuit. The position of the far-end side frame is known from, and the positive / negative signal level of the far-end side frame is held at this timing. Each of the capacitors in the storage circuit is charged and maintained so that the held value can be held even when there is no frame on the far end side. This stored signal is divided by the comparison value generation circuit to obtain a positive / negative comparison value threshold value for AMI. Upon receiving this threshold value and the analog AMI signal from the far-end side signal amplifier, the comparator outputs binary value data AMI2P 1 and AMI2N 2 of positive / negative NRZ.

The frame synchronizing circuit 206 includes a near-end / far-end side frame switching circuit, a bit synchronizing circuit, a frame word detecting circuit, an NT1 frame synchronizing circuit, and an LT.
The frame synchronization circuit and the gain control are provided, and receive the positive / negative NRZ binary value stream data AMI1P 1 and AMI1N 2 from the AMI signal of the first frame on the near end side. Negative NR
Z binary value stream data AMI2P, AMI2N
After receiving the respective synchronization processing, the near-end side synchronization signal and the gain signal are supplied to the far-end side receiving circuit: receiving circuit 3 205, and demodulated frame data sequence NT1data, LTda is demodulated.
Output ta respectively.

That is, the near-end side / far-end side frame switching circuit is configured such that, at the beginning of synchronization, the near-end side receiving circuit: the receiving circuit 2
The positive / negative NRZ binary stream data AMI2P, AMI2N on the 204 side is supplied to the bit synchronization circuit, and the frame synchronization detection signal from the NT1 frame synchronization circuit or the LT frame synchronization circuit in the subsequent stage is received, whichever comes first. A determination process is performed in which the frame synchronized with is regarded as the near-end side frame and the other as the far-end side frame. After the near-end side frame is determined, the near-end side frame and the far-end side frame are alternately switched based on the synchronization signal and supplied to the bit synchronization circuit. Further, the far-end side reception circuit 205 is supplied with a peak hold control signal to the peak hold circuit and a charge timing control signal to the storage circuit to control the gain control. The bit synchronization circuit is either the near end side initially or the near end side /
Upon receiving the AMIP / N signal of the far-end side frame, a line clock (320 KHz) is generated from this pulse train data, and a line data train demodulated by this clock is generated and output. The frame word detection circuit receives the line clock and line data generated by the bit synchronization circuit,
The NT1 frame word detection signal or the LT frame word detection signal is specified and output by comparing with the bit pattern of the frame word (FW) unique to T1 or LT.
The NT1 frame synchronizing circuit and the LT frame synchronizing circuit receive the NT1 / LT frame word detection signal and the line data string from the bit synchronizing circuit, and individually receive the JT-G961.
The frame synchronization state / out of frame synchronization processing is performed according to the frame synchronization procedure, and the NT1 demodulated frame data string N
It outputs T1data, LT demodulated frame data string LTdata, and respective clock signals.

Next, the layer 1 state transition detection circuit 207 shown in FIG. 4 receives the demodulated frame data sequences NT1data and LTdata from the frame synchronization circuit 206, and receives the power supply detection circuit 2
In response to the power supply state detection signals PSNOM and PSRVS from 03, processing is performed based on the JT-G961 line standard, and HDL
The layer 1 state data for C monitor and the layer 1 state transition data indicating the state transition of the layer 1 are output.

The monitor channel selection circuit 208 receives the demodulated frame data sequence NT1da from the frame synchronization circuit 206.
Upon receiving ta and LTdata, descrambling processing is performed on Dch, B1ch, and B2ch of the data channel based on the received ta and LTdata, and Dch, B1ch, and B2c are set according to the monitor channel selection setting conditions from the data analysis apparatus main body 400.
Any channel of h is extracted, and C of Layer 2 or higher is extracted.
Output as H data.

The audio monitor circuit 209 is the B1 channel descrambled by the monitor channel selection circuit 208.
Alternatively, the B2ch data is received, and based on this, a designated channel of the B1ch or the B2ch is extracted according to the audio monitor channel selection setting condition from the data analysis device main body 400, and data buffering at 8 KHz is performed, and PCM64K After demodulation, the analog audio signal is output to the external headphones. The voice monitor circuit 209 may be removed from the device configuration if desired.

[0039]

According to the present invention, the following effects can be obtained from the contents described above. Far-end side receiving circuit: The receiving circuit 3 205 and the frame synchronizing circuit 206 recognize the far-end side frame signal having a large attenuation level, amplify it to a predetermined level and realize demodulation, so TTC standard JT-G96.
It has become possible to realize a communication line data analysis device for a single standard real line.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a communication line data analysis device of the present invention.

FIG. 2 is a circuit diagram of an input unit showing an example of a JT-G961 line signal processing circuit of the present invention.

FIG. 3 is a circuit diagram of two frame stream reproduction units showing an example of a JT-G961 line signal processing circuit of the present invention.

FIG. 4 is a block diagram of a layer state detection and monitor processing unit showing an example of a JT-G961 line signal processing circuit according to the present invention.

FIG. 5 shows an example of an amplitude difference between both frame signal levels between LT and NT1 at a certain connection point.

FIG. 6 is a configuration diagram of a data string of a burst frame that is a JT-G961 line standard.

[Explanation of symbols]

L1, L2 line signal NT1data demodulated frame data string AMI1P, AMI2P, AMI2N, AMI1N Positive / negative NRZ binary value stream data 100 Communication line data analysis device 200 JT-G961 Line signal processing circuit 201 Input stage 202 Reception unit 1 203 Feeding detection circuit 204 Near-end receiving circuit: receiving circuit 2 205 Far-end receiving circuit: receiving circuit 3 205b Far-end frame 2 evolution section 205a Loss level detection section 206 Frame synchronization circuit 207 Layer 1 state transition detection circuit 208 Monitor channel selection Circuit 209 Audio monitor circuit 300 HDLC monitor processing circuit 400 Data analysis device main body

Claims (9)

[Claims] 1. A communication line data analysis for collecting and analyzing this line data by connecting to a TCM (time division direction control) communication line of TTC standard JT-G961 "ISDN basic access metallic subscriber line transmission system" In the device (100), the AMI signal including the power supply voltage signal from the JT-G961 line is received, the layer 1 frame processing is performed, and the layer 2 and subsequent Cs are processed.
A JT-G961 line signal processing circuit (200) for supplying H data and layer 1 state transition data to the HDLC monitor processing circuit (300) and for supplying layer 1 state data to the data analysis device body (400); An HDLC monitor process that receives a signal from the G961 line signal processing circuit (200), processes the input layer 1 state data, performs an HDLC frame process of layer 2 and subsequent layers, and supplies monitor data to the data analyzer main body. The circuit (300), the JT-G961 line signal processing circuit (200) and the HDLC monitor processing circuit (300) are controlled to receive the layer 1 state data from the JT-G961 line signal processing circuit (200), and to receive the layer 1 The status is displayed and the HDLC monitor processing circuit (30
A communication line data analysis device, comprising: a data analysis device body (400) that receives monitor data from 0) and translates and displays HDLC frame data and layer 1 state transition data. 2. The JT-G961 line signal processing circuit (200) according to claim 1, receives the line signals (L1, L2) with a high input impedance, and outputs an AMI signal that passes a predetermined band component. , A normal power supply, a reverse power supply, or a non-power supply state detection signal (PSNOM, PSRVS) output stage (201), a receiving unit 1 (202) circuit, a power supply detection circuit (203), Positive / negative NR from high near-end side first frame
Z binary value stream data (AMI1P, AMI1
Near-end side receiving circuit for converting and outputting to N: receiving circuit 2
(204), and after amplification corresponding to the loss level of the far-end side second frame having a large subscriber line loss, the positive / negative NRZ binary value stream data (AMI1P, A of the far-end side first frame).
Far-end side receiving circuit for converting and outputting to MI1N: receiving circuit 3 (205), and binary value stream data (AMI1P, AMI1N) of positive / negative NRZ from the AMI signal of the near-end side first frame
Received from the far-end frame 2 evolution unit (205b)
Negative NRZ binary stream data (AMI2P,
AMI2N), and after performing respective synchronization processing, a frame synchronization circuit (206) that outputs demodulated demodulated frame data sequences (NT1data, LTdata), respectively, and receives the demodulated frame data sequence (NT1data, LTdata) and supplies power. A layer 1 state transition detection circuit (207) which receives the state detection signals (PSNOM, PSRVS) and outputs layer 1 state data and layer 1 state transition data for HDLC monitoring based on the JT-G961 line standard; A frame data string (NT1data, LTdata) is received, a power supply state detection signal (PSNOM, PSRVS) is received, and a descrambling-processed data channel of layer 2 or later (B1ch, based on the JT-G961 line standard).
B2ch, Dch), and a monitor channel selection circuit (208) for extracting and outputting data of a data channel corresponding to the output selection condition, and a communication line data analysis device. 3. The input stage according to claim 2, the receiving unit 1 circuit, and the power feeding detection circuit receive the line signals (L1, L2) and divide the voltage with a high resistance resistor divider to cut a DC component. Then, the differential amplifier receives an input stage (201) having an HPF that cuts low-frequency components and a differential signal divided by the input stage (201) and filtered by the HPF, and the BPF outputs a predetermined signal. Receiver 1 (2 that outputs an AMI signal that has passed the band component)
02) circuit and the differential signal divided by the input stage (201) is received by a differential amplifier, and a power supply voltage that is a DC component is output. From this voltage signal, normal power supply is performed by a positive / negative comparator. A power supply status detection signal (P
Power supply detection circuit (20) that outputs SNOM, PSRVS)
3), and a communication line data analysis device comprising: 4. The near-end side receiving circuit according to claim 2, wherein the receiving circuit 2 (204) receives the AMI signal after filtering into a predetermined band component from the receiving unit 1 (202) circuit, and outputs the signal level. A communication line data analysis apparatus, characterized in that a comparator for outputting binary stream data (AMI1P, AMI1N) of positive / negative NRZ from the first frame on the near end side having a high frequency is provided. 5. The far-end receiving circuit according to claim 2, wherein the receiving circuit 3 (205) receives the AMI signal after filtering into a predetermined band component from the receiving unit 1 (202) circuit, The far-end side second frame signal having a low signal level is converted into an absolute-value signal by the absolute-value amplifier, the absolute-value signal is received, and the near-end-side first frame synchronization information obtained by the frame synchronization circuit (206) A loss level detection circuit that specifies the position of the far-end side second frame signal, holds the level of the far-end side second frame signal by the peak hold circuit, and outputs loss level data obtained by digitally converting the held analog level signal. And receiving the AMI signal after filtering into a predetermined band component from the receiving unit 1 (202) circuit, and increasing the amplitude to a predetermined amplitude with a gain amplification factor corresponding to the loss level data in the far end side signal amplifier. And a far-end frame 2 evolution unit (205b) that receives the amplified AMI signal and outputs binary stream data (AMI2P, AMI2N) of positive / negative NRZ from the far-end side second frame, A communication line data analysis device comprising: 6. The far-end frame binarization unit (205b) according to claim 5, receives the AMI signal obtained by amplifying the far-end frame signal to a predetermined amplitude by the far-end signal amplifier, and converts it into an absolute value signal. An absolute value amplifier, a peak hold circuit that receives the absolute value signal and holds the amplitude level at the far end side frame position, and a predetermined threshold value is generated from the held amplitude level. Receiving the AMI signal from the side signal amplifier,
Positive / negative NRZ binary stream data (AMI2
P, AMI2N) and a comparator for outputting the converted data, and a communication line data analysis device. 7. The frame synchronization circuit (2) according to claim 2.
06) is binary stream data (AMI1P, AMI1N) of positive / negative NRZ from the AMI signal of the first frame on the near end side.
Received from the far-end frame 2 evolution unit (205b)
Negative NRZ binary stream data (AMI2P,
AMI2N) to output a near-end synchronization signal synchronized in the synchronized first frame at the near-end side, and alternately switch between the first frame at the near-end side and the second frame at the far-end side for output. The frame switching circuit on the far end side, the near end synchronization signal, and the far end side receiving circuit: the receiving circuit 3 (2
The far end side loss level data from 05) is received, the gain control of the far end side signal amplifier is performed, and it is a burst frame based on the JT-G961 line standard.
Near-end / far-end side positive / negative NRZ binary value stream data (AMI1P, AMI1N or AMI2P, A
MI2N) to generate a line clock and line data, which are then synchronized by a synchronization frame word (FW), and LT or NT1 is determined from the bit information of this frame word.
Which is specified and demodulated from the corresponding LT frame synchronization circuit / NT1 frame synchronization circuit (N
T1data, LTdata) are each output, The communication line data analysis device characterized by the above-mentioned. 8. The JT-G961 line signal processing circuit (200) according to claim 2, further comprising a data channel (B1ch, from a monitor channel selection circuit (208) of the JT-G961 line signal processing circuit (200).
B2ch) A communication line data analysis device comprising a voice monitor circuit (209) for receiving data and demodulating PCM64K to output a voice signal. 9. Communication line data for connecting to a TCM (Time Division Direction Control) line of TTC standard JT-G961 "ISDN Basic Access Metallic Subscriber Line Transmission System", collecting line data, and performing analysis In the analyzer, a high impedance circuit receives AMI differential signals (L1, L2), which are burst frame signals (near end first frame, far end second frame) signals from two points from a connection line, and a power supply voltage. The near-end side first frame signal having a high signal level is received, and one of the first frames is synchronized from the JT-G961 standard synchronization frame word (FW) according to the communication standard. Outputting data, receiving the one first frame synchronization signal, and specifying the position of the far end side second frame signal of the other low signal level,
This signal level is amplified to a predetermined level, and in response to this, the second stream data is output in synchronization with the other second frame according to the communication standard, and the synchronized first frame and first frame are output. When both stream data are received, the LT data is output from the CL channel information data.
Side or NT1 side to output the layer 1 data, receive the layer 1 data, and process the data of each layer,
A communication line data analysis device comprising: a data processing translation unit that performs translation processing and outputs the data to a recording medium display means; and the above.