JPH09261212A - Clock extracting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To adequately execute the re-timing processing of input data by judging the phase of an input signanl based on a specified secondary clock and adjusting a phase based on the third clock selected from the second clock. SOLUTION: A multi-phase clock generating circuit 20 generates plural clocks CLK1-CLK8 based on a frequency dividing clock CLK 1 from a PLL circuit 10 and a data edge detecting circuit 30 detects the rising/falling timing edges of input data so as to generate a pulse (e) at every timing cycle. An optimum phase judging circuit 40 counts the number of reference clocks betwewen the pulses (e) and outputs setting informamtion of a required position in input data and an optimum phase selecting circuit 50 selects an optimum phase clock from the clocks CLK1-CLK8 based on the information. A data re-timing circuit 70 adjusts the phase of delay data outputted from a timing adjusting circuit 60 based on the optimum phase clock and outputs an extraction clock CLK9 and extraction data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock extraction circuit, and more particularly to a clock extraction circuit that optimizes the phases of input data and a clock and suppresses a timing shift when retiming input data with the extracted clock. Regarding the circuit.

[0002]

2. Description of the Related Art An example of a clock extraction circuit that uses a phase locked loop (PLL circuit) that extracts a clock from input data and generates a clock having a frequency and a phase that match the input data is disclosed in, for example, Japanese Patent Laid-Open No. Hei 2 -1
No. 23566 or Japanese Patent Laid-Open No. 7-46231.

FIG. 11 shows the configuration of a clock extraction circuit generally used conventionally. As shown in the figure, the input data D _in is commonly input to the PLL circuit 10 and the data retiming circuit 70. The input data D _in input to the PLL circuit 10 is compared in phase with the reference clock CLKV _in the phase comparator 11, and voltages f _up and f _down proportional to the phase error are output. The output of the charge pump 12 is controlled. The error voltage output from the charge pump 12 is the low-pass filter 1
After the frequency band is limited by 3, the voltage is input to the control terminal of the voltage controlled oscillator (VCO) 14. VCO14
Is based on the control input, input data D _in and VCO 14
The reference clock CLKV is controlled so as to reduce the difference in the transmission frequency and the difference in the phase. In this way, the reference clock CLKV is generated from the digital signal (input data D _in ) input to the PLL circuit 10.

On the other hand, the input data D _in input to the data retiming circuit 70 is subjected to phase adjustment based on the reference clock CLKV generated by the PLL circuit 10, and the extracted data D _out and the extracted clock CLK9.
Is output. Here, the configuration of the phase comparison circuit 11 of the PLL circuit 10 will be described. The input data D _in has a constant delay time deray by the delay circuit (delay gate) 11a.
1 is added and input to the exclusive NOR circuit (EXNOR) 11b together with the original input data D _in . EXN
The output a of the OR 11b is input to the NOR circuit (NOR) 11c together with the reference clock CLKV, while NOT
The reference clock CLKV inverted by the circuit (inverter) 11e is also input to the NOR 11d. These NORs 11c and 11d output voltages f _up and f _down proportional to the phase error between the input data D _in and the reference clock CLKV.

Next, the structure of the data retiming circuit 70 will be described. The reference clock CLKV generated by the PLL circuit 10 is added with a constant delay time delay4 by the delay gate 70b, and the flip-flop is used as the retiming clock b. It is input to the C terminal of the (FF) 70a. The input data D _in is input to the D terminal of the FF 70a. Therefore, from the output Q of the FF 70a,
The input data D _in whose phase is adjusted based on the retiming clock b is output as the extracted data D _out . The retiming clock b obtained by adding the delay time delay4 to the reference clock CLKV is inverted by the inverter 80 and output as the extraction clock CLK9.

FIG. 12 shows a timing chart in such a clock extraction circuit 1. The EXNOR 11b, which receives the input data D _in having one cycle of the time T, detects the rising / falling data edge of the input data D _in , and the delay time delay1 is reflected in the output a by the delay gate 11a. It That is, the reference clock CLKV generated by the PLL circuit 10 inevitably has a delay time due to various delay elements such as a logic circuit. Therefore, _in the data retiming circuit 70 that adjusts the phase of the input data D _{in with} the retiming clock (inverted signal of the extracted clock) b, the input data D _in rises at the center (1 / 2T) of the data, for example. A delay gate 70b is provided so as to operate and a delay time delay is applied to the reference clock CLKV.
4 is added, the input data D _in and a predetermined timing are set, and the phase-adjusted extracted data D _out is obtained.

[0007] That is, in the conventional clock extraction circuit, upon the phase adjustment of the input data D _in accordance with data retiming circuit 70, in order to match the input data D _in the retiming clock b of the phase, the input data D _in
Providing a delay gate on the path or clock path,
The adjustment is made so that the rising timing of the retiming clock b is set in the center of the input data.

[0008]

In the PLL circuit 10 of the clock extraction circuit 1 described above, the phase comparator 11 detects the rising / falling edge of the input data D _in or the data retiming circuit. The delay gate 11 is added to add a delay time to the reference clock CLKV.
Although the delay gates a and 70b are provided, in general, the delay gate is easily affected by fluctuations in the ambient temperature, the power supply voltage, and the like, and the delay gate 70b having a delay capability equivalent to that of the PLL circuit 10 is provided in the data retiming circuit 70. Since it is installed, an equivalent error is generated with respect to the above-mentioned fluctuation factors, and the fluctuation range of the timing of the reference clock CLKV is expanded, and there is a problem that the phase adjustment of the input data cannot be performed at the desired timing position. It was In particular, when the input data has a lot of jitter, the above-mentioned timing shift causes an error, and there is a problem that the malfunction of the device using the clock extraction circuit becomes serious.

An object of the present invention is to suppress the timing fluctuation of the extracted clock due to the fluctuation of the operating temperature, the power supply voltage, etc. in the clock extraction circuit using the delay gate, and thereby accurately perform the retiming process of the input data. It is to provide a clock extraction circuit capable of performing. Especially,
An object of the present invention is to suppress the occurrence of an error by surely setting the rising timing of the extraction clock at a desired position of the input data, for example, the center (1 / 2T), and performing the optimum retiming processing of the input data. .

[0010]

In order to achieve the above object, the invention according to claim 1 compares the phase with an input signal, and based on an error voltage proportional to the error of the phase, the input signal is Phase synchronization means for generating a reference clock having a frequency synchronized with the reference clock, an extraction clock having a predetermined delay from the reference clock, and a retiming signal in which the timing of the input signal is adjusted and controlled based on the reference clock. A clock extraction circuit comprising retiming adjusting means, wherein the retiming adjusting means generates a plurality of secondary clocks having a predetermined phase based on the reference clock;
Data edge detecting means for detecting rising and falling edges of the input signal based on a next clock, and a phase of the input signal based on edges of the input signal detected by the reference clock and the data edge detecting means And a phase selection unit that selects a clock used for phase adjustment of the input signal from the plurality of secondary clocks based on the determination result from the phase determination unit and outputs the selected clock as a tertiary clock. A timing adjusting means for reflecting a delay time when the third-order clock is generated from the reference clock in the input signal, and the input signal added with a predetermined delay time by the timing adjusting means, the third-order clock And a retiming means for adjusting the phase on the basis of.

With such a configuration, the clock extraction circuit of the present invention uses the phase synchronization means to input the input signal (input data).
On the basis of the reference clock generated from, the multi-phase clock generation means generates a plurality of secondary clocks of different phases, and the data edge detection means detects the edge of the input signal and generates a pulse for each timing cycle. Then, the number of reference clocks for each cycle of the input data is counted by the phase determination means, and half of the count value,
That is, the center position of the input data is set, and the phase selecting means selects the secondary clock (optimal phase clock) of the phase corresponding to the center position of the data. The timing adjusting means adds the delay time equivalent to the optimum phase clock setting processing to the input data, and the data retiming means performs the phase adjusting processing of the input data based on the optimum phase clock.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A clock extraction circuit according to claim 1 of the present invention will be described in detail below with reference to the drawings.
FIG. 1 shows the basic configuration of the clock extraction circuit of the present invention. In FIG. 1, input data D _in input to a PLL circuit (phase synchronizing means) 10 includes a phase comparator 11, a charge pump 12, a low pass filter 13 and a voltage controlled oscillator (VC).
O) 14 generates the reference clock CLKV which is the source oscillation. The reference clock CLKV is subjected to predetermined frequency division processing via the frequency divider 15, and the phase comparator is supplied with the clock CL.
Supplied as K1. Here, the frequency divider 15 frequency-divides the reference clock CLKV by 1 / n, and in the present embodiment, frequency-dividing by 1/8.

A data retiming adjusting circuit (retiming adjusting means) 100 generates a plurality of (eight) clocks CLK1 to CLK8 having a desired phase based on the divided clock CLK1 generated by the PLL circuit 10. A multi-phase clock generation circuit (multi-phase clock generation means) 20 and a data edge detection circuit (data edge) that detects a rising / falling timing edge of the input data D _in and generates a pulse e at each timing cycle. and detecting means) 30, a data edge detection pulse counts reference clocks CLKV number between e, desired position, for example, central (setting information for setting the 1/2) of the count value g ₁ to g of the input data D _{in The} optimum phase determination circuit (phase determination means) 40 that outputs ₃ and the desired position of the input data D _in based on the setting information g _{1 to} g _3. The optimum phase clock (retiming clock) h corresponding to
Optimal phase selection circuit (phase selection means) 50 to be selected from
And a timing adjusting circuit (timing adjusting means) 60 for adding a delay corresponding to the delay time generated in the process of setting the optimum phase clock h to the input data D _in and outputting the delay data i, and the optimum phase clock h The data retiming circuit (retiming means) 70 for adjusting the phase of the delay data i by outputting the extracted clock CLK9 and the extracted data D _in synchronized with the extracted clock CLK9.
It is composed of

Next, regarding each configuration of the clock extraction circuit of this embodiment, a concrete circuit configuration example will be shown, and the operation will be described with reference to a timing chart. [1] PLL Circuit The PLL circuit 10 shown in the present embodiment is equivalent to the configuration shown in FIG. 11, and the input data D _in
Reference clock CLKV (source oscillation) synchronized with VCO1
It is output from 4. In the present invention, the reference clock C
The frequency-divided clock CLK1 obtained by frequency-dividing LKV by 1/8 by the frequency divider 15 is input to the phase comparator 11 as a comparison clock, and the phase comparison with the input data D _in is performed.

Therefore, as shown in the timing chart of FIG. 2, the voltage corresponding to the phase error output from the phase comparator 11 is adjusted by adjusting (arrow) the rising timing of the divided clock CLK1 by the frequency divider 15. Since the area ratio of f _up and f _down can be changed, the output of the charge pump 12 can be appropriately controlled. Here, as a premise of the clock extraction processing, it is necessary to input a repeating pattern of "1" and "0" which is switched at a cycle T to the input data D _in . [2] Multi-Phase Clock Generation Circuit As shown in FIG.
The divided clock CLK1 generated by the LL circuit 10 is input, a predetermined delay is added by seven stages of delay gates 20a to 20f, and a plurality of clocks CL having different phases are added.
Outputs K2 to CLK8.

As shown in the timing chart of FIG.
Delay time delay included in the delay gates 20a to 20f
3, the clocks CLK2 to CLK8 extracted from the output of each delay gate are generated with a phase difference of delay3. The smaller the setting of the delay time delay3 added by the delay gates 20a to 20f, and the larger the number of multi-phase clocks generated, the later-described data.
During the retiming process, the clock rising timing can be set more accurately _in the center of the input data D _in . [3] Data Edge Detection Circuit As shown in FIG. 4, the data edge detection circuit 30 adds the delay time delay2 to the input data D _in and outputs the delay gate 30a for outputting the delay data D and the delay data D. A flip-flop (FF) 30b having a D terminal input and a divided clock CLK1 having a C terminal input, delay data D having a D terminal input, and a clock CLK2 output from the multi-phase clock generation circuit 20 having a C terminal input. F
An EX that receives the F30c and the Q outputs D1 and D2 of the FFs 30b and 30c as inputs and outputs the exclusive NOR logic e
It is composed of NOR 30d. Here, the delay time delay2 added by the delay gate 30a is set to be larger than the delay given by the PLL circuit 10 described above.

With such a configuration, as shown in the timing chart of FIG. 5, delay 2 is applied to the input data D _in .
The delay data to which the delay time is added is held at the timing of the clock CLK1 in the FF 30b and the Q output D
1 is obtained, and the clock CLK2 is obtained in the FF 30c.
The Q output D2 is obtained by being held at the timing of. The exclusive NOR logic of these outputs D1 and D2 then outputs a pulse output e indicating a data edge. [4] Optimum Phase Judgment Circuit The optimum phase judgment circuit 40, as shown in FIG.
The pulse output e output from the edge detection circuit 30 is commonly input to the S terminal, the reference clock CLKV is input to the C terminal, and the inverted signal f _{0 of the} Q ^* output (Q ^* : inverted output of Q) is output. FF40b~ but the Q output of the FF of FF40a and preceding stage is input to the D terminal is input to the C terminal, and the Q ^* output inverted signals f ₁ ~f ₃ of is inputted to each of the D terminal
A first flip-flop group consisting 40d, pulse output e is input in common to the C terminal, and each D terminal receives the inverted signal f ₁ ~f ₃ of Q ^* output of FF40b～40d, also Q ^* output composed of the second flip-flop group consisting FF40e~40g for outputting an inverted signal g ₁ to g ₃ as the determination information of the optimum phase.

With such a configuration, as shown in the timing chart of FIG. 7, a period between the first pulse output e ₁ and the second pulse output e ₂ output from the data edge detection circuit 30 is set as a count period. Reference clock CLKV
The number of clocks is measured by the first flip-flop group. The count values f _{1 to} f ₃ are multiplied by ½ by the second flip-flop group, that is, the phase determination information g ₁ = "which corresponds to the central position (1 / 2T) of the input data D _{in.
0 ", g 2 =" 0} ", g 3 =" output as 1 ". [5] optimum phase selecting circuit optimum phase selection circuit 50, as shown in FIG. 8, is outputted from the optimum phase determining circuit 40 A MUX logic circuit (MU) in which the phase determination information g ₁ is a common S terminal input and the clocks CLK1 and CLK2 are D1 and D2 terminal inputs, respectively.
X) 50a, as well as clocks CLK3 and CLK4
MUX50b, which is respectively the D1 and D2 terminal inputs,
Clocks CLK5 and CLK6 to D1 and D2 respectively
MUX 50c for terminal input and MUX for clocks CLK7 and CLK8 as D1 and D2 terminal inputs, respectively
50d and the first MUX group, and the phase determination information g ₂
As a common S terminal input, and MUX50a and MUX5
MU which inputs Q output of 0b to D1 and D2 terminal respectively
A second MUX group consisting of X50e and MUX50f whose Q outputs of MUX50c and MUX50d are input to D1 and D2 terminals respectively, and phase determination information g ₃ is an S terminal input, and Q outputs of MUX50e and MUX50f are respectively D1 and The MUX 50g (third MUX) that receives the D2 terminal input and outputs the Q output as the optimum phase clock h
(Group)). Here, in the MUX logic, when the S terminal input is "0", the D1 terminal input is reflected in the Q output,
When the S terminal input is "1", the D2 terminal input is reflected in the Q output.

With such a configuration, FIG. 7 and FIG.
As shown in the timing chart of 1., during the count period set by the pulse output e indicating the data edge of the input data D _in , the phase determination information output from the optimum phase determination circuit 40 is g ₁ = “1”. ", G ₂ =" 1 ", g ₃
= "1", and MUX 50a-g are all connected to S terminal
1 "is input. Therefore, the output clock h
, The clock CLK8 is selected as indicated by the dotted line in FIG. Next, after the end of the counting period, the phase determination information output from the optimum phase determination circuit 40 is g ₁ = “0”, g ₂
= “0”, g ₃ = “1”, and S of MUX 50a-f
"0" is input to the terminal. Therefore, as the output clock h, the clock CLK5 is selected as shown by the dotted line in FIG. Here, in selecting the optimum phase clock h, as shown in FIG. 10, the first, second and third MUs are selected.
Due to the X group, the clocks CLK5 and CLK8 have M
A delay of three stages of UX is added. [6] Timing Adjustment Circuit As shown in FIG. 9, the timing adjustment circuit 60 uses the delay data D output from the data edge detection circuit 30 as the D1 terminal input, and the S terminal grounded.
And the MUX 60b with the Q output of the MUX 60a as the D1 terminal input and the S terminal grounded, and the MUX 60c with the Q output of the MUX 60b as the D1 terminal input, the S terminal grounded, and the Q output as the retiming data i. Composed of.

With such a configuration, as shown in the timing chart of FIG. 10, the delay data D has the same delay (three MUX stages) as the delay added to the optimum phase clock h in the optimum phase selection circuit 50 described above. ) Is added to cancel each other's delay. [7] Data Retiming Circuit The data retiming circuit 70, as shown in FIG.
The optimum phase clock h output from the optimum phase selection circuit 50 is used as the C terminal input, the retiming data i output from the timing adjustment circuit 60 is used as the D terminal input, and the Q output is output as the extracted data D _out. Composed. The optimum phase clock h is
It is inverted by 0 and output as the extracted clock CLK9.

With such a configuration, as shown in the timing chart of FIG. 10, the phase of the retiming data i is adjusted by the optimum phase clock h (CLK5) having the rising timing at the center (1 / 2T) of the data. , And is output as extracted data D _out . After that, the extracted data D _out that matches the phase of the extracted clock CLK9 (the inverted signal of the optimum phase clock) is obtained.

As described above, the reference clock CLKV and the divided clock CLK1 generated by the PLL circuit 10.
On the basis of the above, the multi-phase clock generation circuit 20, the data edge detection circuit 30, the optimum phase determination circuit 40, and the optimum phase selection circuit 50 extract the clock having the optimum phase for the retiming processing of the input data D _in , Then, based on the optimum phase clock, the timing adjustment circuit 60 and the data retiming circuit 70 can perform retiming processing of the input data D _in . Here, since the multi-phase clock to be selected is generated using the delay gate that is smaller than the delay of the PLL circuit 10 when generating the optimum phase clock, it is possible to prevent fluctuation factors such as the ambient temperature and the power supply voltage. Thus, the fluctuation amount of the extracted clock can be suppressed to a small level and the rising timing can be set at a predetermined position of the input data D _in , so that the phase of the data can be adjusted well.

[0023] Data retiming adjustment control in the embodiment described above, in the practice of the extraction process of the series of clock retiming processing of input data D _in, "1" to the input data D _in, the "0" Although the method of inputting a repetitive pattern has been shown, by inputting such a repetitive pattern at a predetermined cycle or by configuring the repetitive pattern to be automatically executed, the optimum phase The clock is selected with high accuracy, and the error suppression effect can be improved.

The number of stages of delay gates for generating a multi-phase clock and the reference clock CLK in the present embodiment.
The number of FF stages for counting the number of V clocks and setting a predetermined position of data, and the number of MUX stages for selecting the clock of the optimum phase are determined by the frequency divider (1 / n) 15 for dividing the reference clock. It is appropriately determined according to the setting.

[0025]

As described above, according to the clock extraction circuit of the present invention, the rising timing of the clock signal can be accurately set at the center of the timing of the input data without being affected by the fluctuation of the ambient temperature and the power supply voltage. Since it can be set, it is possible to suppress the occurrence of an error at the retiming even if the data with a lot of jitter is input.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of a clock extraction circuit according to the present invention.

FIG. 2 is a diagram showing a timing chart in the phase locked loop circuit applied to the present invention.

FIG. 3 is a diagram showing an example of a data edge detection circuit and a multi-phase clock generation circuit applied to the present invention.

FIG. 4 is a diagram showing a timing chart in the multi-phase clock generation circuit applied to the present invention.

FIG. 5 is a diagram showing a timing chart in the data edge detection circuit applied to the present invention.

FIG. 6 is a diagram showing an example of an optimum phase determination circuit applied to the present invention.

FIG. 7 is a diagram showing a timing chart in the optimum phase determination circuit applied to the present invention.

FIG. 8 is a diagram showing an example of an optimum phase selection circuit applied to the present invention.

FIG. 9 is a diagram showing an example of a timing adjustment circuit and a data retiming circuit applied to the present invention.

FIG. 10 is a diagram showing a timing chart in the optimum phase selection circuit, timing adjustment circuit, and data retiming circuit applied to the present invention.

FIG. 11 is a diagram showing a configuration of a conventional clock extraction circuit.

FIG. 12 is a diagram showing a timing chart in a conventional clock extraction circuit.

[Explanation of symbols]

1 Clock Extraction Circuit 10 Phase Synchronous Circuit (PLL Circuit: Phase Synchronous Means) 11 Phase Comparator 11a Delay Gate 11b Exclusive NOR Circuit (EXNOR) 11c, 11d NOR Circuit 11e NOT Circuit (Inverter) 12 Charge Pump 13 Low-pass Filter 14 Voltage controlled oscillator (VGO) 15 Frequency divider 20 Multi-phase clock generation circuit (multi-phase clock generation means) 30 Data edge detection circuit (data edge detection means) 40 Optimal phase determination circuit (phase determination means) 50 Optimal phase selection Circuit (phase selection means) 60 Timing adjustment circuit (timing adjustment means) 70 Data retiming circuit (data retiming means) 80 NOT circuit (inverter) 100 Data retiming adjustment circuit

Claims (1)

[Claims] 1. A phase synchronizing means for comparing a phase with an input signal and generating a reference clock having a frequency synchronized with the input signal based on an error voltage proportional to an error of the phase, and a predetermined clock from the reference clock. A clock extraction circuit comprising: an extracted clock having a delay; and a retiming adjusting unit that outputs a retiming signal that adjusts and controls the timing of the input signal based on the reference clock, wherein the retiming adjusting unit comprises: Multi-phase clock generation means for generating a plurality of secondary clocks having a predetermined phase based on a reference clock; and data edge detection means for detecting rising and falling edges of the input signal based on the secondary clocks. , Based on the edges of the input signal detected by the reference clock and the data edge detection means Phase determining means for determining the phase of the input signal, based on the determination result from the phase determining means,
A phase selection unit that selects a clock used for phase adjustment of the input signal from the plurality of secondary clocks and outputs the selected clock as a tertiary clock, and a delay time when the tertiary clock is generated from the reference clock, the input signal And a retiming means for adjusting the phase of the input signal to which a predetermined delay time has been added by the timing adjusting means based on the third-order clock. circuit.