JPH09261192A - Multiplexer and compression coder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease number of data lines, to facilitate multiplex processing, to improve the utilizing efficiency of packets and to enhance a degree of freedom of muultiplex scheduling in the case of supplying digital data by plural channels to the multiplexer. SOLUTION: Coders 51(1)-51(4) apply compression coding to audio data of channels CH(1)-CH(4) in compliance with the MPEG compression coding rules. FIFO circuits 52(1)-52(4) store tentatively the audio data of the channels CH(1)-CH(4) compression-coded by the coders 51(1)-51(4). A selector 53 is used to multiplex the audio data read from the FIFO circuits 52(1)-52(4). The audio data stored in the FIFO circuits 52(1)-52(4) are read by a read function in the inside of the FIFO circuits 52(1)-52(4) based on read request signals RR(1)-RR(4) denoting a channel from which the data are to be read and an amount of data to be read.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexer for multiplexing digital data of a plurality of channels and outputting the multiplexed data. The present invention also relates to a compression encoding device that compresses and encodes digital data of a plurality of channels, and then multiplexes and outputs it.

[0002]

2. Description of the Related Art In recent years, interest in multimedia systems has increased. Here, the multimedia system is, for example, a system in which various kinds of information such as audio information, video information, character information, etc. are collected into one recording medium and recorded on one recording medium or transmitted via one transmission medium. Say.

In order to realize this multimedia system, information compression technology and multiplexing technology are required. MPEG (Moving Picture Experts Group: International standard for media-integrated video compression) is a standardized version of this information compression technology and multiplexing technology.

The multimedia system constructed according to the MPEG has a compression encoding device, a transmission medium (recording medium, transmission medium), and a decoding device. here,
The compression encoding device is configured to compress and encode a plurality of pieces of information included in one program and then multiplex the information.

FIG. 12 shows an example of this compression coding apparatus. The illustrated compression encoding device is an audio encoder 10.
, Video encoder 20, and private encoder 30
And a multiplexer 40 for individually digitizing audio data, video data, and private data, and then multiplexing them.

Further, this compression encoding device can handle not only information for one channel but also information for a plurality of channels as information. In FIG.
1 shows a configuration of an audio encoder 10 that can handle information for multiple channels. In the figure, for example, four encoders 11 (1), 11 (2), 11 (3), 11 (4)
With 4 channels CH (1), CH (2), CH
An audio encoder capable of handling audio data of (3) and CH (4) is shown.

Here, the audio data of the channel CH (1) is, for example, Japanese right channel data, and the audio data of the channel CH (2) is, for example, Japanese left channel data. Channel CH
The audio data of (3) is, for example, English right channel data, and the audio data of the channel CH (4) is, for example, English left channel data.

[0008]

When a plurality of channels of audio data are treated as audio data, the audio data of each channel are equivalent to each other and also to other digital data (video data etc.). . Therefore, when supplying audio data for a plurality of channels to the multiplexer 40, it is conceivable to supply audio data for a plurality of channels in parallel with each other and in parallel with other digital data.

That is, in the example of FIG. 13, the audio data of the four channels CH (1) to CH (4) are converted into the audio data of FIG.
As shown in FIG. 4, it is possible to supply the multiplexer 40 in parallel with each other and with the digital video data and the digital private data in parallel.

However, in such a configuration, the number of data lines between the audio encoding unit 10 and the multiplexer 40 increases, which may cause a problem that wiring between them becomes difficult. To be Particularly, in the case of an MPEG compression encoding device, this problem is considered to be great because a large-scale circuit must be incorporated in a limited space.

The present invention has been made in view of the above problems, and its object is to reduce the number of data lines when supplying digital data for a plurality of channels to a multiplexer. An apparatus and a compression encoding apparatus are provided.

[0012]

A multiplexer and a compression encoder according to the present invention are provided with a data holding means for temporarily holding digital data of a plurality of channels for each channel, and hold the data in the data holding means. The digital data for a plurality of channels are read and multiplexed according to a read request indicating a channel to be read and an amount to be read.

In the multiplexing device and compression encoding device of the present invention, digital data for a plurality of channels is temporarily held in the data holding means for each channel. The digital data of a plurality of channels held in the data holding means is read according to the read request. As a result, the digital data of the channel designated by the read request is read by the amount designated by the read request. This read data is multiplexed and put into one data string.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

[First Embodiment] First, a first embodiment of the present invention will be described.
An embodiment will be described. In the following description, the present invention will be described as an audio encoder 10 shown in FIG.
A case where the present invention is applied to an apparatus that compresses and encodes audio data of four channels CH (1) to CH (4) will be described as a representative.

[Outline of First Embodiment] First, an outline of the present embodiment will be described. The present embodiment has a data holding means for temporarily holding the audio data of the four channels CH (1) to CH (4) for each channel CH (n) (n = 1, 2, 3, 4). The audio data held in the data holding means is read and multiplexed in accordance with a read request indicating a channel to be read and an amount to be read.

That is, in order to reduce the number of data lines between the audio encoder 10 and the multiplexer 40 shown in FIG. 14, four channels CH (1) to CH shown in FIG. 13 are used.
The audio data of (4) may be multiplexed.

In order to realize this multiplexing, one buffer is provided as a transmission buffer of the audio encoder 10, and four channels CH (1) are provided in this transmission buffer.
-CH (4) audio data may be written in a time division manner.

That is, in the MPEG compression encoding apparatus, the timing at which the audio encoder 10 outputs the audio data is usually different from the timing at which the MPEG multiplexer 40 takes in the audio data. For this reason, this compression coding apparatus requires a transmission buffer for absorbing the difference between the above two timings.

In such a configuration, as shown in FIG. 15, one buffer 12 is provided as a transmission buffer, and four channels CH (1) are provided in this transmission buffer 12.
If CH (4) audio data is written in a time division manner, these can be multiplexed. As a result, the number of data lines between the audio encoder 10 and the multiplexer 40 can be reduced from four to one.

However, such a configuration has the following two problems.

(1) First Problem The first problem is that the multiplexing process of the multiplexer 40 becomes complicated and the packet use efficiency decreases.

That is, the MPEG2 is provided with a multi-program function for multiplexing a plurality of programs into a single program. In this multi-program function, digital data of each program is multiplexed by using a relatively short packet called a transport packet, so that a plurality of programs can be integrated into one.

Therefore, the multiplexer 40 divides the input data by the data length of the payload of the transport packet to generate a plurality of segments S, and adds header information or the like to each segment S to add the transport information. It is designed to generate port packets.

However, when the coded output of each encoder 11 (n) is written in the transmission buffer 12 in a time division manner, each coded output is sequentially written in one coding unit as shown in FIG. Be done. The number N of bytes in one coding unit is generally not an integral multiple of the number M of bytes in the payload of the transport packet. Therefore, when one coding unit is divided by the number of bytes M of the payload of the transport packet, the number of bytes of the last segment S becomes smaller than the number M of bytes of the payload.

On the other hand, the generation of the transport packet is
It must be done for each channel. That is, when a transport packet is generated, it is necessary to prevent data of different channels from being mixed in one packet. Therefore, in a configuration in which the number of bytes of the last segment S is smaller than the number of bytes M of the payload of the transport packet, meaningless data (hereinafter referred to as "dummy data") is added to the last segment S, and this segment S is added. It is necessary to match the data length of the above with the number of bytes M of the payload of the transport packet.

However, in such a configuration, since the process for inserting the dummy data DD is required in the multiplexing process, there is a problem that the multiplexing process becomes complicated. Further, since dummy data is inserted into some transport packets, there arises a problem that packet usage efficiency is reduced.

(2) Second Problem The second problem is that the degree of freedom in multiplexing scheduling is reduced when audio data is multiplexed with video data or the like. Here, the multiplexing scheduling refers to a scheduling indicating how much audio data of which channel is multiplexed with video data and the like.

That is, when the audio data of each channel CH (n) is written in the transmission buffer 12, these are written in a predetermined order as described above. Therefore, even when the multiplexer 40 multiplexes the audio data of each channel CH (n) with the video data or the like, they must be multiplexed in this order.

When the audio data of each channel CH (n) is written in the transmission buffer, these are multiplexed in one coding unit as described above. Therefore,
Even when the multiplexer 40 multiplexes the audio data of each channel CH (n) into digital data, it must be multiplexed in this unit.

From the above, with the above-mentioned configuration, the degree of freedom of multiplexing scheduling when audio data is multiplexed with video data or the like is reduced.

Therefore, in the present embodiment, when the audio data of the four channels CH (1) to CH (4) are supplied to the multiplexer 40, the number of data lines can be reduced, of course. It is an object of the present invention to provide a multiplexing device and a compression encoding device which can prevent the complication of the encoding process and the reduction of packet use efficiency and can increase the degree of freedom of the multiplexing scheduling.

In order to achieve the above object, the present embodiment has four channels CH (1) to CH (CH) as described above.
(4) Data holding means for temporarily holding the audio data for each channel CH (n) is provided, and the audio data held in the data holding means is read out to indicate the channel to be read and the amount to be read. The data is read out and multiplexed according to a request.

According to the above configuration, four channels CH
Since the audio data of (1) to CH (4) are multiplexed, the number of data lines for transmitting the audio data from the audio encoder 10 to the multiplexer 40 is reduced to 1/4. Can be reduced.

Further, four channels CH (1) to CH
A data holding means for temporarily holding the audio data of (4) is provided for each channel CH (n), and a read request indicating a channel from which the audio data held in the data holding means should be read and an amount to be read. Since the data is read in accordance with the above, it is possible to prevent the multiplexing process from becoming complicated and the packet usage efficiency from decreasing, and it is possible to increase the degree of freedom in multiplexing scheduling.

[Structure of First Embodiment] FIG.
3 is a block diagram showing the configuration of the embodiment of FIG. In the figure, reference numeral 50 denotes an audio encoder that compresses and encodes audio data of four channels CH (1) to CH (4). The audio encoder 50 corresponds to the compression encoding device of the present invention. 60 is an audio encoder 5
It is a multiplexer for multiplexing audio data output from 0, video data output from a video encoder (not shown), and the like.

The audio encoder 50 has an encoder 51.
(1), 51 (2), 51 (3), 51 (4) and first-in first-out memory circuit (hereinafter referred to as "FIFO circuit") 52 (1), 52 (2), 52 (3), 52.
(4) and the selector 53.

Here, each encoder 51 (n) has a function of compressing and coding the audio data of the corresponding channel CH (n) according to the compression coding standard of MPEG.
Each FIFO circuit 52 (n) has a corresponding encoder 51.
It has a function of temporarily holding the audio data of the channel CH (n) compressed and encoded by (n). The selector 53 has a function of multiplexing the audio data read from the FIFO circuits 52 (1) to 52 (4).

The encoders 51 (1) to 51 (4) correspond to the compression encoding means of the compression encoding device of the present invention. The selector 53 corresponds to the data selecting means of the compression encoding device and the multiplexing device of the present invention. Furthermore, FIFO
The circuits 52 (1) to 52 (4) correspond to the data holding means and the data reading means of the compression encoding device and the multiplexing device of the present invention.

That is, each FIFO circuit 52 (n) is
Functionally, as shown in FIG. 2, the data storage unit 521
(N), a data writing unit 522 (n), and a data reading unit 523 (n). These are usually 1
It is integrated into one chip.

Here, the data storage unit 521 (n) has a function of storing the audio data output from the corresponding encoder 51 (n). Data writing unit 522
(N) is based on the write request signal WR (n) output from the corresponding encoder 51 (n).
(N) has a function of writing the audio data output from the data storage unit 521 (n).

The data reading unit 523 (n) outputs the audio data stored in the data storage unit 521 (n) according to the read request signal RR (n) of the channel CH (n) output from the multiplexer 60. It has a reading function. This reading is performed according to the first-in first-out method in which the written data is read in order.

In such a configuration, the data storage unit 521 (n) and the data writing unit 522 (2) correspond to the data holding means of the present invention. In addition, the data reading unit 5
23 (n) corresponds to the data reading means of the present invention.

The read request signal RR (n) is
It is output for each channel CH (n). Further, the read request signal RR (n) corresponds to the corresponding channel CH.
Designate the data read amount of (n). This designation is made, for example, by controlling the length of the active level period of the read request signal RR (n).

Each data read section 523 (n) reads audio data from the data storage section 521 (n) when the corresponding read request signal RR (n) is set to the active state. This read is performed by the read request signal RR.
The level of (n) is continued during the active level.
Further, the selector 53 keeps the corresponding FI during the period when each read request signal RR (n) is set to the active state.
The read output of the FO circuit 52 (n) is selected.

[Operation of First Embodiment] The operation of the above configuration will be described. First, each FIFO circuit 52
The operation of writing audio data in the (n) data storage unit 521 (n) will be described.

The input data of each channel CH (n) is supplied to the corresponding encoder 51 (n). Encoder 51
The audio data supplied to (n) is compression-encoded at a predetermined encoding cycle. As a result, audio data having a compressed data amount can be obtained.

The encoder 51 (n) writes the write request signal WR when the compression encoding processing for one encoding unit is completed.
Set (n) to the active state. As a result, the audio data obtained by the compression encoding process for one encoding unit is processed by the data writing unit 522 (n) of FIG.
It is written in the data storage unit 521 (n) of FIG.

Thereafter, similarly, the above-described operation is repeated in a predetermined coding cycle. As a result, each FIFO circuit 5
As shown in FIG. 3, only the audio data of the channel CH (n) is written in the 2 (n) data storage unit 521 (n).

The above is the operation of writing the audio data into the data storage section 521 (n) of each FIFO circuit 52 (n). Next, an operation of reading audio data from the data storage unit 521 (n) and multiplexing the audio data will be described.

The multiplexer 60 sets the read request signal RR (n) to the active state in accordance with the predetermined multiplexing scheduling. When the read request signal RR (n) is set to the active state, the FIFO circuit 52 (n)
Audio data of the channel CH (n) stored in the data storage unit 521 (n) of the data reading unit 523.
It is read by (n). This reading is continued while the read request signal RR (n) is at the active level.

When the read request signal RR (n) is set to the active state, the selector 53 causes the FIFO.
The output of circuit 52 (n) is selected. This selection is continued while the read request signal RR (n) is at the active level. As a result, the audio data read from the data storage unit 521 (n) by the data reading unit 523 (n) is supplied to the multiplexer 60 via the selector 53.

According to the above configuration, by setting the number of read bytes of the audio data to an integral multiple of the number of bytes M of the payload of the transport packet, it is possible to eliminate the process of adding the dummy data DD. As a result, the multiplexing process can be simplified and the packet usage efficiency can be improved.

FIG. 4 is a timing chart showing an example of the operation when audio data is read from the data storage unit 521 (n) and multiplexed. In the figure,
(A)-(d) are read request signals RR (1)-
Indicates RR (4). These are signals that make a low level an active level and a high level an inactive level. Further, (e) shows the selection output (multiple output) of the selector 53.

FIG. 4 shows read request signals RR (1) to R.
The case where R (4) is sequentially set to the active state is shown. Further, a case is shown in which the read request signals RR (1) to RR (4) have the same active level period.

In this case, first, the read request signal RR (1) of the channel CH (1) is set to the active state. As a result, the audio data is read from the data storage unit 521 (1) of the FIFO circuit 52 (1) by the data reading unit 523 (1). This data is
It is selected by the selector 53.

Similarly, channels CH (2) to CH
The read request signals RR (2) to RR (4) of (4) are sequentially set to the active state. As a result, the audio data of these channels CH (2) to CH (4) sequentially appear at the output terminal of the selector 53. As a result, as shown in FIG. 4 (e), channels CH (1) to CH
A data string in which the audio data of (4) is sequentially multiplexed is obtained.

[Specific Example of Selector 53] Here, an example of a specific configuration of the selector 53 will be described. FIG. 5 is a block diagram showing an example of a specific configuration of the selector 53. The illustrated selector 53 includes four gate circuits 531 (1), 531 (2), provided for each channel CH (n).
531 (3) and 531 (4).

Here, the gate circuits 531 (1) to 531
The input terminals of (4) correspond to the corresponding FIFO circuits 5
It is connected to the output terminals of 2 (1) to 52 (4). The output terminals of the gate circuits 531 (1) to 531 (4) are commonly connected. The common connection point is the multiplexer 6
Connected to 0. Gate circuits 531 (1) -531
The corresponding read request signals RR (1) to RR (4) are supplied to the on / off control terminals of (4).

In the above configuration, the read request signal RR
When (n) is set to the active state, the gate circuit 5
31 (n) is set to the ON state. As a result, the corresponding data storage unit 521 (n) of the FIFO circuit 52 (n).
The audio data read from the gate circuit 531
It is supplied to the output terminal of the selector 53 via (n).
As a result, at the output terminal of the selector 53, the four channels CH (1) to C are multiplexed according to the multiplexing scheduling.
Audio data for H (4) is obtained.

[Effects of First Embodiment] According to the present embodiment described in detail above, the following effects can be obtained.

(1) First, according to the present embodiment, 4
Since the audio data of the one channel CH (1) to CH (4) is multiplexed, the number of data lines for transmitting the audio data to the multiplexer 60 can be reduced to 1/4.

(2) According to the present embodiment, 4
FI for temporarily holding audio data of one channel CH (1) to CH (4) for each channel CH (n)
The FO circuits 52 (1) to 52 (4) are provided, and the FIFO
Since the audio data held in the circuits 52 (1) to 52 (4) are read according to the read request signals RR (1) to RR (4) indicating the channel to read and the amount to read, the multiplexing processing is performed. It is possible to prevent complication of packet and decrease of packet usage efficiency, and increase the degree of freedom of multiplexing scheduling.

[Second Embodiment] Next, the second embodiment of the present invention will be described.
An embodiment will be described. In the above embodiment, the case where the read request signal is output from the multiplexer 40, the case where the dedicated read request signal RR (n) is output for each channel CH (n) has been described. On the other hand, in the present embodiment,
From the multiplexer 40, four channels CH (1) to CH
The read request signal RR shared in (4) is output, and the read request signal RR is converted into read request signals RR (1) to RR (4) dedicated to the channel by using a decoder.

FIG. 6 is a block diagram showing the structure of the main part of this embodiment. Note that, in FIG. 6, parts that perform substantially the same functions as in FIG. 5 described above are given the same reference numerals, and detailed description thereof will be omitted.

In FIG. 6, the read request signal RR output from the multiplexer 40 includes a channel designation signal RRa and a read amount designation signal RRb. Here, the channel designation signal RRa is a signal that designates the read channel CH (n) to be read. The channel designation signal RRa is represented by, for example, a 2-bit digital signal. This is because the number of designated channels is four. The read amount designation signal RRb is a signal that designates the amount of data to be read. The read amount designating signal RRb is represented by a binary digital signal like the read request signal RR (n) dedicated to the channel.

The read channel designating signal RRa and the read amount designating signal RRb are supplied to the decoder 54. The decoder 54, based on the read channel designation signal RRa,
The channel CH (n) to be read is determined, and the read amount designation signal RRb is output as the read request signal RR (n) of this channel CH (n). Thereby, the FIF of the channel CH (n) designated by the channel designation signal RRa
From the data storage unit 521 (n) of the O circuit 52 (n), the data reading unit 523 (3) reads the read amount designation signal CHb.
The amount of audio data specified by is read.

The read channel designating signal RRa is further supplied to the selector 55. The selector 55 determines the channel CH (n) to be read based on the channel designation signal RRa, and the F of this channel CH (n) is determined.
The read output of the IFO memory 52 (n) is selected. As a result, the audio data of the channels CH (1) to CH (4) are multiplexed according to the multiplexing scheduling.

Note that in such a configuration, the decoder 54 and the data reading section 523 of the FIFO circuit 52.
(N) corresponds to the data reading means of the present invention. Further, the selector 55 corresponds to the data selecting means of the present invention.

FIG. 7 is a timing chart showing an example of the operation when the audio data is read from the data storage unit 521 (n) and multiplexed. In the figure,
(A) shows the read channel designation signal RRa. In the figure, the channel CH (1) is designated by "00" and "01"
Indicates the channel CH (2), and "10" indicates the channel CH
The case where (3) is designated and the channel CH (4) is designated by "11" is shown.

(B) shows the read amount designation signal RRb. The figure shows the case where the low level is the active level and the high level is the inactive level.
(C) shows the selection output (multiple output) of the selector 55.

As shown in FIG. 7A, the value of the read channel designating signal RRa is sequentially switched according to the multiplexing scheduling. In the figure, "00", "0"
As a representative, the case of switching in the order of 1 ”,“ 10 ”, and“ 11 ”is shown. Therefore, in this case, the channels are CH (1), CH (2), CH (3), CH (4).
Are specified in this order.

Accordingly, the level of the read amount designating signal RRb is also sequentially switched as shown in FIG. 7 (b). As a result, although not shown in the figure, channel CH (1)
~ CH (4) read request signals RR (1) to RR (4)
Are sequentially set to the active level. As a result, the multiple output as shown in FIG. 7C is obtained from the selector 55.

In this embodiment described in detail above, the same effect as in the previous embodiment can be obtained, and further, the read request signal RR is transmitted from the multiplexer 60 to the compression encoder 50. It is possible to obtain the effect that the number of control lines for controlling the number can be reduced by one as compared with the previous embodiment.

[Third Embodiment] Next, a third embodiment of the present invention will be described.
An embodiment will be described. In the second embodiment,
The case where the read channel designation signal RRa is supplied from the multiplexer 60 to the audio encoding unit 50 has been described. On the other hand, in the present embodiment, this is supplied from a circuit other than the multiplexer 60.

FIG. 8 is a block diagram showing the configuration of the present embodiment. In FIG. 8, the same parts as those in FIG. 6 are designated by the same reference numerals and detailed description thereof will be omitted.

In the illustrated apparatus, for example, a read channel is designated by a control unit 71 which manages multiplexing scheduling and the like. That is, the control unit 71 outputs the read channel specifying command Ca that specifies the read channel. The read channel designation command Ca is supplied to the decoder 73 via the command bus 72.

The decoder 73 decodes the read channel designating command Ca and outputs the read channel designating signal RRa. The read channel designation signal RRa is supplied to the decoder 54 and the selector 55. As a result, audio data is read from the FIFO circuit 52 (n) of the channel CH (n) designated by the read channel designation signal RRa. This audio data is supplied to the multiplexer 60 via the selector 55.

According to this embodiment described in detail above, the multiplexer 60 and the compression encoder 5 are different from those of the second embodiment.
The number of control lines between 0 and 2 can be reduced by two.

[Fourth Embodiment] Next, a fourth embodiment of the present invention will be described.
An embodiment will be described. In the above-described first to third embodiments, a FIFO circuit is provided for each channel to hold digital data of four channels CH (1) -CH (4) for each channel CH (n). Explained the case.

On the other hand, according to the present embodiment, the storage area of the random access memory (hereinafter referred to as “RAM”) is divided into a plurality of areas, and each divided area is assigned to each channel CH (n). Channels CH (1) -CH
The digital data of (4) is held for each channel CH (n).

FIG. 9 is a block diagram showing the configuration of the present embodiment. In FIG. 9, the same parts as those in FIG. 1 described above are designated by the same reference numerals, and detailed description thereof will be omitted.

The difference between FIG. 9 and FIG. 1 is that the FIF
RAM 56 instead of O circuits 52 (1) to 52 (4)
And a memory control circuit 57 is provided. Here, the RAM 56 has a function of temporarily holding the audio data output from the encoders 51 (1) to 51 (4). The memory control circuit 57 has a function of controlling writing and reading of the RAM 56. That is, RAM5
6 corresponds to the data storage means of the present invention, and the memory control circuit 57 also corresponds to the data writing means and the data reading means.

FIG. 10 shows a storage area of the RAM 56.
As shown, the storage area R of the RAM 56 is divided into four areas R (1), R (2), R (3) and R (4). Each divided region R (n) is assigned to the channel CH (n).

The operation of the above configuration will be described. First, the audio data of each channel CH (n) is stored in RAM
The operation when writing to 56 will be described.

The encoders 51 (1) to 51 (4) output write request signals WR (1) to WR (4) when the compression encoding processing for one encoding unit is completed. The write request signals WR (1) to WR (4) are sent to the memory control circuit 57.
Is supplied to.

Upon receiving the write request signals WR (1) to WR (4), the memory control circuit 57 receives the coder 51.
The processing results for one coding unit supplied from (1) to 51 (4) are divided into regions R (1) to R (R) of the RAM 56, respectively.
Write in (4). As a result, the audio data of the four channels CH (1) to CH (4) obtained by compression encoding are held in the RAM 56 for each channel CH (n).

FIG. 11 shows the memory control circuit 57 in this case.
6 is a flowchart showing the processing of FIG. The illustrated process is repeated in the encoding cycle. In this process, the memory control circuit 57 first determines whether or not the write request signal WR (n) is generated (step S101).

When it occurs, the output of the encoder 51 (n) corresponding to the generated write request signal WR (n) is changed to RA.
Writing to the divided area R (n) of M57 (step S10)
1 to S105). For example, when the write request signal WR (1) is generated, the output of the encoder 51 (1) corresponding to the write request signal WR (1) is written in the divided area R (1) of the RAM 57 (step S102). .

When this process ends, the memory control circuit 5
7 returns to step S101, and then the write request signal W
It also waits for R (n) to occur. After repeating the above processing for the number of channels 4, the memory control circuit 57 ends the processing (step S106). After this, the above-mentioned processing is repeated again in the next encoding cycle.

The memory control circuit 57 does not receive a write request signal of another channel when writing data of a certain channel. This is because when writing data to the RAM 56, only one channel can be written at a time. It should be noted that such competition occurs because the processing time of the compression encoding process for one encoding unit changes from moment to moment depending on the content of data to be processed.

The above is the operation when the audio data of each channel CH (n) is written in the RAM 56. Next, the audio data of each channel CH (n) is stored in the RAM.
The operation of reading from 56 will be described.

This operation is performed based on the read request signal RR. In FIG. 9, the read channel designation signal RRa and the read amount designation signal RRb supplied from the multiplexer 60.
A case where the reading is controlled based on and is shown. In this case, the memory control circuit 57 causes the read channel designation signal R
The read channel CH (n) is determined according to Ra, and the audio data is read from the divided area R (n) of the RAM 56 corresponding to this channel CH (n). This reading is performed by the amount designated by the reading amount designation signal RRb.

The audio data read from the RAM 56 is supplied to the multiplexer 60. In this case, the audio data will not be selected by a selector or the like. This is because audio data of all channels CH (1) to CH (4) is stored in one RAM 56 in the present embodiment. That is,
According to such a configuration, all channels CH (1)
This is because the audio data of CH (4) is output from one terminal and is multiplexed at the time of being read.

Also in the present embodiment described in detail above, the same effect as that of the first embodiment can be obtained, and one RAM 56 is used for all the channels C.
Since the audio data of H (1) to CH (4) is held, the selector can be omitted. Thereby, the configuration of the audio encoder 50 can be simplified.

[Other Embodiments] Although the four embodiments of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments.

For example, in the above embodiment, the present invention is
The case where it is applied to the multiplexing of a plurality of audio data has been described. However, the present invention can also be applied to multiplexing digital data (private data, etc.) other than audio data. Further, the present invention can be applied not only to the multiplexing of the same kind of digital data but also to the multiplexing of different kinds of digital data (audio data, video data, etc.). Furthermore, the present invention can be applied not only to multiplexing within one program but also to multiplexing between programs. In addition to this, it goes without saying that the present invention can be variously modified without departing from the scope of the invention.

[0098]

As described in detail above, according to the multiplexer and the compression encoder of the present invention, the digital data of a plurality of channels are multiplexed, so that the data for transmitting the digital data is transmitted. The number of lines can be reduced.

Further, a data holding means for temporarily holding digital data of a plurality of channels is provided for each channel, and the reading showing the channel and the amount to be read out of the digital data held in the data holding means. Since the reading is performed according to the request signal, it is possible to prevent the complexity of the multiplexing process and the decrease in the packet usage efficiency, and it is possible to increase the degree of freedom of the multiplexing scheduling.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing the basic configuration of the FIFO circuit according to the first embodiment.

FIG. 3 is a diagram showing a data storage state according to the first embodiment.

FIG. 4 is a timing chart for explaining the operation of the first embodiment.

FIG. 5 is a block diagram showing an example of a specific configuration of a selector according to the first embodiment.

FIG. 6 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 7 is a timing chart for explaining the operation of the second embodiment.

FIG. 8 is a block diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a fourth exemplary embodiment of the present invention.

FIG. 10 is a diagram showing a configuration of a RAM according to a fourth embodiment.

FIG. 11 is a flowchart for explaining the operation of the fourth embodiment.

FIG. 12 is a block diagram showing the configuration of an MPEG compression encoding device.

FIG. 13 is a block diagram showing the structure of a multi-channel MPEG audio encoder.

[Fig. 14] Fig. 14 is a block diagram illustrating an example of a configuration of a multi-channel MPEG compression encoding device.

FIG. 15 is a block diagram showing another example of the configuration of a multi-channel MPEG compression encoding device.

16 is a diagram for explaining a problem of the compression encoding device shown in FIG.

[Explanation of symbols]

50 ... Audio encoder, 60 ... Multiplexer, 51 (1)
-51 (4) ... Encoder, 52 (1) -52 (4) ... F
IFO circuit, 53 ... Selector, 521 (n) ... Data storage section, 522 (n) ... Data writing section, 523 (n) ...
Data read unit, 531 (1) to 531 (n) ... Gate circuit, 54 ... Decoder, 55 ... Selector, 56 ... RA
M, 57 ... Memory control circuit, 71 ... Control unit, 72 ... Command bus, 73 ... Decoder.

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[Procedure amendment]

[Submission date] June 5, 1996

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] Fig. 8

[Correction method] Change

[Correction contents]

[Figure 8]

Claims (8)

[Claims] 1. A data holding means for temporarily holding digital data of a plurality of channels for each channel, and a read request indicating a channel to be read and an amount to be read, from the data holding means for the plurality of channels. And a multiplexing unit for reading and multiplexing digital data. 2. The data holding means is provided for each channel and stores a plurality of data storage means for storing digital data of the corresponding channel, and a write request for digital data of the corresponding channel provided for each channel. And a plurality of data writing means for writing the digital data in the corresponding data storage means according to the above, the multiplexing means is provided for each channel, and in accordance with a digital data read request of the corresponding channel, A plurality of data reading means for reading the digital data from the corresponding data storage means in the order of writing, and a data selecting means for selectively selecting the digital data read by the plurality of data reading means in accordance with the read request. Characterized in that it is configured to be equipped with Motomeko 1 multiplexer according. 3. The data holding means stores the digital data of the plurality of channels for each channel using a plurality of divided areas obtained by dividing the storage area, and When a digital data write request is generated, the digital data write means writes the digital data in a corresponding divided area of the data storage means, and the multiplexing means is configured to send a digital data read request of each channel. 2. The multiplexing apparatus according to claim 1, wherein when the digital data is generated, the digital data is read out from the corresponding divided area of the data storage means. 4. The multiplexer according to claim 1, wherein the read request is output for each channel and indicates the read amount of digital data of the corresponding channel. 5. The multiplexing device according to claim 1, wherein the read request is shared by the plurality of channels and indicates a channel to be read and a data amount to be read. 6. The multiplexing apparatus according to claim 1, wherein the digital data is compression-encoded based on the MPEG compression-encoding standard. 7. A plurality of compression coding means for compressing and coding digital data of a plurality of channels for each channel, and digital data compressed and coded by the plurality of compression coding means for each channel temporarily. And a multiplexing unit for reading and multiplexing the digital data of the plurality of channels from the data holding unit according to a read request indicating a channel to be read and an amount to be read. And a compression encoding device. 8. The compression coding apparatus according to claim 7, wherein said compression coding means is configured to compression code the digital data based on a compression coding standard of MPEG. .