JPH09260509A - Dual gate and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a gate where voltage does not fluctuate by heat treatment. SOLUTION: A p-type conductive layer 15p and an n-type conductive layer 15n connected to the layer are provided. First metal silicide layers 16 (16a) are formed on the p-type conductive layer 15p and second metal silicide layer 16 (16b) are formed on the n-type conductive layer 15n. A groove 17 is formed in the metal silicide layers 16 on the boundary of the p-type conductive layer 15p and the n-type conductive layer 15n. A buried conductive layer 20 constituted of the conductive metal material that separates at least the first and second metal silicide layers 16a and 16b and inhibits the mutual diffusion of impurities, which occurs between the first and second metal silicide layers 16a and 16b, is formed in the groove 17.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a dual gate and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a gate electrode of a MOS transistor, mainly for the purpose of reducing the wiring resistance of the gate electrode,
Conventionally, a so-called polycide structure in which a tungsten silicide (WSi ₂ ) layer is laminated on a polycrystalline silicon layer has been used. On the other hand, due to the miniaturization of the transistor size (mainly the gate length), the short channel effect of the transistor (threshold voltage Vth variation due to the variation of the gate length) becomes larger and larger. Especially p-channel MI
The S (MIS is an abbreviation for Metal Insulator semiconductor) transistor has a buried channel in the n ⁺ -type polycrystalline silicon gate currently used, so that the short channel effect is larger than that of the n-channel MIS transistor. That is a major obstacle to further miniaturization in the future. Therefore, phosphorus (P) or arsenic (As) is used for the gate electrode of the n-channel MIS transistor.
With n ⁺ -type polycrystalline silicon doped with, for p-channel MIS transistor using the p ⁺ -type polycrystalline silicon doped with an boron (B), so-called dual gate structure has been proposed.

[0003]

However, when the polycide structure is used for the dual gate structure, phosphorus (P) or arsenic (As) in the n ⁺ -type polycrystalline silicon, and p Boron (B) in the ⁺ type polycrystalline silicon diffuses through a tungsten silicide (WSi ₂ ) layer having a large diffusion coefficient, which causes a phenomenon called mutual diffusion. When this interdiffusion occurs, the work function of the polycrystalline silicon that constitutes the gate changes, which in turn changes the threshold voltage Vth. This interdiffusion is due to the transistor manufacturing process.
As long as heat treatment is performed, there is no way to prevent it, and it will become a major issue in the practical application of the dual gate structure in the future. Therefore, a structure for separating tungsten silicide (WSi ₂ ) and polycide has also been proposed. However, if isolation is performed when patterning the gate, for example, the area of the isolation portion becomes large, which hinders the miniaturization of the device.

[0004]

SUMMARY OF THE INVENTION The present invention is a dual gate and a method of manufacturing the same for achieving the above object.

The dual gate has the following structure. That is, the first conductive type conductive layer is formed on one of the conductive layers, and the first conductive type conductive layer is formed on the other side of the first conductive type conductive layer.
A conductive layer of a second conductivity type, which is a conductivity type opposite to the conductivity type, is formed. A metal silicide layer is formed on the conductive layer of the first conductivity type and the conductive layer of the second conductivity type, and the metal silicide layer on the boundary between the conductive layer of the first conductivity type and the conductive layer of the second conductivity type. A groove is formed in the. Then, at least the first metal silicide layer and the second metal silicide layer are separated by the buried conductive layer made of a conductive metal-based material that blocks the interdiffusion that occurs between the first metal silicide layer and the second metal silicide layer. Thus, it is formed inside the groove.

In the above dual gate, a groove for separating the first metal silicide layer on the first conductive type conductive layer and the second metal silicide layer on the second conductive type conductive layer is provided with a groove for separating the first conductive type conductive layer. Formed on the boundary between the first metal silicide layer and the second conductive type conductive layer, and in the groove thereof, at least the first metal silicide layer and the second metal silicide layer are separated, and the first metal silicide layer and the second metal are formed. Since the buried conductive layer made of a conductive metal-based material that prevents mutual diffusion that occurs between the first metal silicide layer and the second silicide layer is formed.
Interdiffusion of impurities that occurs with the metal silicide layer is prevented, and potential transfer is not hindered by the diode formed between the first conductive type conductive layer and the second conductive type conductive layer. , The potential transfer between the conductive layer of the first conductivity type and the conductive layer of the second conductivity type is performed by connecting the first metal silicide layer, the buried conductive layer, and the second conductivity type of the conductive layer of the first conductivity type. And a second metal silicide layer connected to the conductive layer.

The dual gate manufacturing method has the following steps. That is, after forming a conductive layer film on a substrate, one of the conductive layer films is doped with a first conductive type impurity to form a first conductive type conductive layer, and then a first conductive type film is formed. A first metal silicide layer is formed on the conductive layer. Then, the other of the conductive layers is doped with an impurity of the second conductive type opposite to the first conductive type to form a conductive layer of the second conductive type. Then, a first metal silicide layer is formed on the conductive layer of the second conductivity type. Then, a sidewall insulating film is formed on the side wall of the first metal silicide layer on the side of the conductive layer of the second conductivity type. Then, after forming the second metal silicide layer on the second conductive type conductive layer, the sidewall insulating film is exposed, and the first metal silicide layer and the second conductive type conductive layer on the first conductive type conductive layer are exposed. The upper second metal silicide layer is separated. Then, the sidewall insulating film is removed to form a groove between the first metal silicide layer and the second metal silicide layer. Subsequently, at least the first metal silicide layer and the second metal silicide layer are separated from each other by a conductive metal-based material that prevents interdiffusion between the first metal silicide and the second metal silicide in the groove. A dual gate is formed by forming a buried conductive layer.

In the above dual gate manufacturing method,
A first metal silicide layer and a second metal silicide layer connected to a conductive type conductive layer;
Since the trench for separating the second metal silicide layer connected to the conductive type conductive layer is formed by self-aligning the sidewall insulating film and then removing the sidewall insulating film, the first metal silicide is formed. The separation width between the layer and the second metal silicide layer is reduced.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION An example of an embodiment of a dual gate of the present invention will be described with reference to the schematic configuration diagram of FIG.

An element isolation film 12 is formed on the semiconductor substrate 11, and a gate insulating film 14 is formed on the semiconductor substrate 11 in the element formation regions 13 (13a, 13b) separated by the element isolation film 12. There is. The semiconductor substrate 11 is formed of, for example, a silicon substrate, and the element isolation film 12 is formed by, for example, a local oxidation method [eg, LOCOS (Local Oxidation of Si).
licon) method]. The gate insulating film 14 is made of, for example, a silicon oxide film. A conductive layer is formed on such a substrate 10, and one of the conductive layers is formed as a conductive layer 15p of the first conductivity type (hereinafter referred to as p type) with the element isolation film 12 as a boundary. The other of the conductive layers is formed as a second conductive type (hereinafter referred to as n type) conductive layer 15n that is joined to the p type conductive layer 15p.
For example, the conductive layer is made of non-doped polysilicon, the p-type conductive layer 15p is made of p ⁺ -type polysilicon, and the n-type conductive layer 15n is made of n ⁺ -type polysilicon.

Further, a metal silicide layer 16 is formed on the p-type conductive layer 15p and the n-type conductive layer 15n. A groove 17 is formed in the metal silicide layer 16 on the boundary between the p-type conductive layer 15p and the n-type conductive layer 15n. Due to the groove 17, the metal silicide layer 16 is connected to the first metal silicide layer 16a connected to the p-type conductive layer 15p and the n-type conductive layer 15n.
It is separated from the second metal silicide layer 16b connected thereabove.

An interlayer insulating film 18 is formed on the metal silicide layer 16, and a contact hole 19 is formed on the groove 17. This interlayer insulating film 18 is
Like a normal interlayer insulating film, it is made of, for example, a silicon oxide-based insulating film.

The contact hole 18 and the groove 1
Reference numeral 7 is made of a conductive metal-based material that prevents mutual diffusion of impurities that occur between the first metal silicide layer 16a and the second metal silicide layer 16b, and is composed of at least the first metal silicide layer 16a and the second metal. A buried conductive layer 20 that separates the silicide layer 16b is formed. The buried conductive layer 20 is composed of a so-called barrier metal layer formed on the inner walls of the contact hole 19 and the groove 17, and a metal layer material or doped polysilicon that fills the contact hole 19 and the groove 17. The barrier metal layer includes, for example, titanium nitride (TiN) and titanium oxynitride (T
It is possible to use a metal compound such as iON) or doped polysilicon. Further, as the metal-based material, it is possible to use a metal or a metal compound made of, for example, tungsten, aluminum (Al), copper (Cu), or the like. The barrier metal layer is necessary only when high-temperature heat treatment (for example, heat treatment at a temperature of 700 ° C. or higher) is applied after the buried conductive layer 20 is formed. Therefore, it is not necessary to form the barrier metal layer when high temperature heat treatment is not applied.

A wiring 21 connected to the buried conductive layer 20 is formed on the interlayer insulating film 18. The wiring 21 is made of a wiring material such as an aluminum-based metal or a copper-based metal.

As described above, the p-type conductive layer 15p, the n-type conductive layer 15n, the metal silicide layer 16 and the buried conductive layer 20 constitute the dual gate 1.

In the dual gate 1, the groove 17 for separating the first metal silicide layer 16a and the second metal silicide layer 16b is provided with the p-type conductive layer 15p and the n-type conductive layer 15n.
The first metal silicide layer 1 is formed substantially on the boundary between the first metal silicide layer 1 and the groove 17 so that at least the first metal silicide layer 16a and the second metal silicide layer 16b are separated from each other.
6a and the second metal silicide layer 16b, the buried conductive layer 20 made of a conductive metallization material that prevents mutual diffusion of impurities that occurs between the first metal silicide layer 16a and the second metal silicide layer 16a is formed. Interdiffusion of impurities that occurs with 16b is prevented. Along with that, p
The potential transfer between the p-type conductive layer 15p and the n-type conductive layer 15n is prevented by the diode formed between the p-type conductive layer 15p and the n-type conductive layer 15n. , The first metal silicide layer 16a connected to the p-type conductive layer 15p, the buried conductive layer 20, and the second metal silicide layer 16b connected to the n-type conductive layer 15n.

Next, an example of an embodiment relating to a method of manufacturing a dual gate will be described with reference to the manufacturing process diagrams of FIGS. 2 and 3, the same components as those in FIG. 1 are designated by the same reference numerals.

As shown in FIG. 2A, an element isolation film 12 is formed on a semiconductor substrate (for example, a silicon substrate) 11 by a normal element isolation region forming method to form an element formation region 13 (13a, 13b). ) Is separated. As a method of forming the element isolation film 12, for example, a local oxidation method (for example, LO
COS method) was used. Next, the gate insulating film 14 is formed on the surface of the semiconductor substrate 11 to have a thickness of 7 nm, for example. As a method for forming the gate insulating film 14, for example, a thermal oxidation method is used to form the gate insulating film 1 made of a silicon oxide film.
4 was formed. Further, a film to be a conductive layer is formed on the semiconductor substrate 11. The conductive layer film is formed of, for example, a non-doped polysilicon film having a thickness of 100 nm, and a method of forming the film is, for example, chemical vapor deposition (hereinafter, referred to as CVD, CVD is Chemical. Vap
The abbreviation for our Deposition) method was used.

Thereafter, the entire surface of the non-doped polysilicon film is doped with, for example, boron ions (B ⁺ ) as an impurity of the first conductivity type (p type) to make the non-doped polysilicon film p-type, and the p-type conductive layer 15p is formed. Form. For the doping, for example, an ion implantation method is used. Here, as an example of the ion implantation conditions, the acceleration energy is set to 5 keV and the dose amount is set to 3.0 × 10 ¹⁵ pieces / cm ² . As a result, a p-type conductive layer 15p made of p ⁺ -type polysilicon was formed.

Then, as shown in (2) of FIG.
Of the first metal silicide layer 16 on the entire surface of the conductive layer 15p of
a is formed to have a thickness of 150 nm, for example. The first metal silicide layer 16b is made of, for example, a tungsten silicide (WSi ₂ ) film, and as a method for forming the film, for example, the CVD method was used.

Subsequently, as shown in FIG. 2C, an etching mask 41 is formed by a coating technique and a lithographic technique to cover a region where a p-type gate electrode is to be formed. Then, the first metal silicide layer 16a is patterned by etching using the etching mask 41. As the etching, for example, reactive ion etching was used.

Then, the p-type conductive layer 15p exposed by the etching is formed into an n-type film by an ion implantation method.
For example, phosphorus ions (P ⁺ ) are doped as an impurity of the second conductivity type (n type) with a dose amount to be typed to form the n type conductive layer 15n in the region where the ion implantation is performed.
In the above-mentioned ion implantation, as an example, the acceleration energy is set to 10 keV and the dose amount is set to 6.0 × 10 ¹⁵ pieces / cm ² . As a result, an n-type conductive layer 15n made of n ⁺ -type polysilicon was formed.

After that, the etching mask 41 is removed. This removal is performed by, for example, ashing and cleaning treatment.

Next, as shown in FIG. 2D, a silicon oxide film, for example, having a thickness of 150 nm is formed as an insulating film on the entire surface of the semiconductor substrate 11 on the side where the first metal silicide layer 16a is formed. To do. Then, by etching back the silicon oxide film, a sidewall insulating film 31 made of the oxide silicide film is formed on the sidewall of the first metal silicide layer 16a to have a width of 100 nm, for example.

Then, as shown in FIG. 3 (5), for example, tungsten silicide (WS) is formed as the second metal silicide layer 16b on the entire surface on the n-type conductive layer 15n side.
The i ₂ ) layer is formed to a thickness of 150 nm. The CVD method, for example, was used for this film forming method.

Further, as shown in (6) of FIG. 3, chemical mechanical polishing (hereinafter referred to as CMP, CMP stands for Chemical Mec
hanical Polising) method, the second metal silicide layer 16b is polished to form the sidewall insulating film 3
1 is exposed. In this polishing, the upper layer of the first metal silicide layer 16a may also be polished. By performing the polishing as described above, the surfaces of the first metal silicide layer 16a and the second metal silicide layer 16b are planarized.

Then, the sidewall insulating film 31 [shown in (4)] is removed by etching to form a groove 17 between the first metal silicide layer 16a and the second metal silicide layer 16b.

Then, by the usual lithographic technique and etching, the first and second silicide layers 16 are formed.
a, 16b and p-type conductive layer 15p and n-type conductive layer 1
5n was patterned to form a p-type gate electrode 22p and an n-type gate electrode 22n. As such, source / drain regions (not shown) are formed in the semiconductor substrate 11 on both sides of the p-type and n-type gate electrodes 22p and 22n by an ion implantation method or the like to form a transistor.

Thereafter, as shown in (7) of FIG. 3, an interlayer insulating film 18 is further formed by the CVD method. Next, a contact hole 19 communicating with the groove 17 is formed in the interlayer insulating film 18 by lithographic technique and etching. At this time, the interlayer insulating film 18 embedded in the groove 17 is also removed.

Then, the contact hole 19 and the groove 1
A buried conductive layer 20 is formed in 7. The buried conductive layer 20 is formed of at least the first metal silicide layer 16a and the second metal silicide layer 16a by a conductive metal-based material that prevents mutual diffusion of impurities that occur between the first metal silicide layer 16a and the second metal silicide layer 16b. A barrier metal layer formed in a state of separating from the metal silicide layer 16b, for example, a barrier metal layer formed on the inner wall of the contact hole 19 and the groove 17 and a conductive material layer formed so as to fill the contact hole 19 and the groove 17. Consists of. For the barrier metal layer, a metal compound such as titanium nitride (TiN) or titanium oxynitride (TiON), or doped polysilicon can be used. Further, as the metal-based material, it is possible to use a metal or a metal compound made of, for example, tungsten, aluminum (Al), copper (Cu), or the like.
The barrier metal layer is necessary only when high-temperature heat treatment (for example, heat treatment at a temperature of 700 ° C. or higher) is applied after the buried conductive layer 20 is formed. Therefore, it is not necessary to form the barrier metal layer when high temperature heat treatment is not applied.

Next, a wiring 21 connected to the buried conductive layer 20 is formed on the interlayer insulating film 18 by a normal wiring forming technique. The wiring 21 is formed of a wiring material such as an aluminum-based metal or a copper-based metal.

As described above, the p-type conductive layer 15p,
The dual gate 1 is formed by the n-type conductive layer 15n, the metal silicide layer 16 and the buried conductive layer 20.

In the method of manufacturing the dual gate 1 described above, p
First metal silicide layer 16 connected to the conductive layer 15p of
After forming the sidewall insulating film 21 in a self-aligned manner in a groove separating the a and the second metal silicide layer 16b connected to the n-type conductive layer 15n, the sidewall insulating film 2 is formed.
Since it is formed by removing 1, the width of the groove 17 for preventing mutual diffusion between the first metal silicide layer 16a and the second metal silicide layer 16b is reduced. Moreover, the formation of the groove is simplified as compared with the case of forming the groove by the lithographic technique and the etching.

Further, in the above-mentioned manufacturing method, the groove 17 for separating the first metal silicide layer 16a and the second metal silicide layer 16b is formed, so that the first metal silicide layer 16a and the second metal are formed inside the groove 17. Silicide layer 16
The buried conductive layer 20 made of a conductive metallization material that prevents mutual diffusion of impurities between the first metal silicide layer 16a and the second metal silicide layer 1 is formed.
6b can be formed in a separated state.

Further, after the first metal silicide layer 16a is formed, the n-type conductive layer 15n is formed by the ion implantation method. At this time, therefore, the first metal silicide layer 16 is formed.
a serves as a mask, and the junction between the p-type conductive layer 15p and the n-type conductive layer 15n is located below the side surface of the first metal silicide layer 16a. Therefore, the sidewall insulating film 21 formed on the side surface of the first metal silicide layer 16a includes the p-type conductive layer 15p and the n-type conductive layer 15n.
It will be formed almost on the boundary with. Therefore, by removing the sidewall insulating film, the groove 17 is formed on the boundary between the p-type conductive layer 15p and the n-type conductive layer 15n. Therefore, the embedded conductive layer 20 is also formed on the boundary.

[0036]

As described above, according to the dual gate of the present invention, the groove for separating the first and second metal silicide layers is formed substantially on the boundary between the conductive layers of the first and second conductivity types. , A buried conductive layer made of a conductive metal-based material that prevents interdiffusion of impurities occurring between the first and second metal silicide layers in a state where at least the first and second metal silicide layers are separated inside the groove. Since this is formed, it is possible to prevent mutual diffusion of impurities that occur between the first and second metal silicide layers. Therefore, variation in the threshold voltage Vth of the transistor can be suppressed. Further, since the buried conductive layer is formed between the first metal silicide layer connected to the first conductive type conductive layer and the second metal silicide layer connected to the first conductive type conductive layer, The potential transfer between the first and second conductive type conductive layers can be performed by the first and second metal silicide layers and the buried conductive layer. Therefore, the potential transfer is not hindered by the diode formed between the first and second conductive type conductive layers.

According to the method of manufacturing the dual gate,
Since the trench for separating the first metal silicide layer and the second metal silicide layer is formed by forming the sidewall insulating film in a self-aligning manner and removing the sidewall insulating film, the process can be simplified. In addition, the separation width between the first metal silicide layer and the second metal silicide layer can be reduced.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a dual gate according to the present invention.

FIG. 2 is a manufacturing process diagram of a dual gate according to the present invention.

FIG. 3 is a manufacturing process diagram (continuation) of a dual gate.

[Explanation of symbols]

1 Dual Gate 15n n-type Conductive Layer 15
pp type conductive layer 16 metal silicide layer 16a first metal silicide layer 16b second metal silicide layer 17 groove 20
Embedded conductive layer

Claims (2)

[Claims] 1. A conductive layer of a first conductive type formed on one of the conductive layers, and a first conductive type which is joined to the conductive layer of the first conductive type and is formed on the other side of the conductive layer is opposite. Conductive type second
A conductive type conductive layer, a metal silicide layer formed on the first conductive type conductive layer and on the second conductive type conductive layer, the first conductive type conductive layer and the second conductive type conductive layer A groove formed in the metal silicide layer on a boundary with a layer, and formed inside the groove so as to separate at least the first metal silicide layer and the second metal silicide layer, A dual gate, comprising: a first metal silicide layer and a buried conductive layer made of a conductive metal-based material that prevents mutual diffusion of impurities that occur between the first metal silicide layer and the second metal silicide layer. 2. A film to be a conductive layer is formed on a substrate, one of the films to be a conductive layer is doped with an impurity of the first conductivity type to form a conductive layer of the first conductivity type, Forming a first metal silicide layer on the conductive layer of the first conductive type, and doping the other film of the conductive layer with an impurity of the second conductive type having a conductivity type opposite to the first conductive type. Forming a second conductive type conductive layer, forming a sidewall insulating film on the side wall of the first metal silicide layer on the second conductive type conductive layer side, and the second conductive type conductive layer. After forming a second metal silicide layer on the layer, the sidewall insulating film is exposed to expose the first metal silicide layer on the conductive layer of the first conductivity type and the second metal silicide layer.
Separating the second metal silicide layer on the conductive type conductive layer, and removing the sidewall insulating film to form a groove between the first metal silicide layer and the second metal silicide layer. And a step of forming the first metal silicide layer and the second metal layer inside the groove.
Forming a buried conductive layer in a state where at least the first metal silicide layer and the second metal silicide layer are separated by a conductive metal-based material that prevents mutual diffusion of impurities that occur between the metal silicide layer and the metal silicide layer. A method of manufacturing a dual gate, comprising: