JPH09259154A - Method and device for designing logic, and production of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the period for designing a semiconductor integrated circuit. SOLUTION: The area of elements at the gate level corresponding to the technology of a semiconductor integrated circuit to be produced is previously registered in a library 13, a specification 10 of the semiconductor integrated circuit described in a hardware description language, a simplified element form and the characteristics of a clock to be applied to the semiconductor integrated circuit are inputted to a computer and while using the elements registered in the library 13, the computer generates the net list of circuit at the gate level based on the specification. Based on the element form and the element area registered in the library 13, an element size is decided and based on the net list and the element size, the automatic arrangement of elements and automatic wiring between the elements are roughly performed rather than the stage of layout design on a floor 20 corresponding to a chip. Then, based on the results of automatic arrangement and automatic wiring, signal delay time is found and based on the signal delay time and the characteristics of the clock, the timing analysis of signal at a flip-flop inside the semiconductor integrated circuit is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic design method and device, and a semiconductor integrated circuit manufacturing method.

[0002]

2. Description of the Related Art In automatic design of a semiconductor integrated circuit, a gate-level circuit is generated by inputting the function and structure specifications of the semiconductor integrated circuit described in HDL (Hardware Description Language) to a logic synthesis tool. To be done. The generated circuit is layout-designed using an automatic placement and routing tool.

In order to reduce the timing error after layout design, after logic synthesis and before layout design,
From the graph of the relationship between the size of the functional block and the average virtual wiring capacitance of the inter-element wiring in the functional block, find the virtual wiring capacitance between the elements without laying it out, and perform a logic simulation to determine the timing error. It detected and adjusted the timing.

[0004]

However, due to the miniaturization of circuit elements, (inter-cell wiring capacitance) / (cell input capacitance) becomes large, and this ratio becomes almost 1 in an LSI having a wiring width of 0.5 μm. . The larger this ratio, the (virtual wiring capacity)-
The (real wiring capacity) becomes large, the virtual wiring capacity becomes inaccurate, and the timing error after layout design increases. This increase becomes significant due to the large scale of the circuit and the high speed operation. Partially modifying the circuit to eliminate timing errors in one part affects the timing in another part. Therefore, it is necessary to repeatedly perform the circuit structure modification, logic synthesis, and layout design described in HDL, which causes a problem that the design period becomes long.

Further, in the logic simulation, the operation of a certain part is complicatedly related to the entire circuit, so that a huge amount of time is required for this detection, and the above problem is further exacerbated. In particular, when the semiconductor integrated circuit operates at a plurality of clock frequencies, it is not easy to detect the timing error, and the above problem becomes more serious. In view of such problems, it is an object of the present invention to provide a logic design method and device and a semiconductor integrated circuit manufacturing method capable of shortening the design period of the semiconductor integrated circuit.

[0006]

In the logic design method according to the first aspect of the present invention, the name of the gate level element and the area of the element according to the technology of the semiconductor integrated circuit to be manufactured are registered in the library in advance. The specifications of the semiconductor integrated circuit described in the hardware description language, the simplified element shape, and the characteristics of the clock given to the semiconductor integrated circuit are input to a data processing device, for example, a computer, and , A netlist of gate-level circuits is generated based on the specifications using the elements registered in the library, and the element size is determined based on the area of the elements and the element shape registered in the library. On the floor corresponding to the chip of the semiconductor integrated circuit, based on the logic synthesis process to be determined, the netlist and the element size, Automatic layout and automatic wiring between elements are performed more roughly than the layout design stage, a signal delay time is obtained based on the result of the automatic layout and automatic wiring, and the characteristics of the signal delay time and the clock A timing analysis step of performing timing analysis of a signal in a flip-flop in the semiconductor integrated circuit based on
Execute

According to the first aspect of the present invention, in the logic design stage, rough floor planning is performed, and timing analysis is performed based on the result to detect timing errors. (1) Timing adjustment is more accurate and the number of iterations between logic design and layout design is reduced compared to the conventional method in which a timing error is detected by performing a logic simulation considering the signal delay according to As a result, the design period of the semiconductor integrated circuit is shortened, and (2) the timing error can be detected in a much shorter time than the conventional logical simulation in which the entire circuit is intricately entangled. This has the effect of reducing the design period of the integrated circuit.

Further, since the element shape in the floor planning is simplified, it is possible to prevent the floor planning processing time from being lengthened. Furthermore, since the element size is determined by the combination of the area and shape of the element, the amount of information to be registered in the library can be reduced. In a first aspect of the first aspect of the invention, a timing adjusting step of correcting a timing error by correcting the circuit on the floor based on the result of the timing analysis, and a semiconductor integrated circuit on which the timing is adjusted And a netlist extraction step of extracting a netlist from.

According to the first aspect, since the timing error is eliminated based on the result of the timing analysis, there is an effect that the timing adjustment is automatically performed. In a second aspect of the first invention, the output of the first flip-flop is supplied to the second flip-flop on the floor, and
The first clock from the point and the second clock from the second point are respectively supplied to the clock input terminals of the first flip-flop and the second flip-flop, and the timing analysis step is substantially the second point. The first time difference T11 which is the time difference between the trigger edge of the second clock and the trigger edge of the first clock at the first point, and the maximum of the period of the first clock and the period of the second clock. Common divisor GDC
And the trigger edge time difference T11 (GDC-T1
1) The second step of obtaining the second time difference T12, the signal delay time between the first point and the data input terminal of the second flip-flop, and the second point and the second flip-flop. The second step of obtaining the delay time difference α, which is the difference from the signal delay time with the clock input terminal, and the third time (T11−
α) and the third step of obtaining the fourth time (T12 + α),
The third time and the fourth time are respectively the setup time ST and the hold time H of the second flip-flop.
And a fourth step of comparing with T to determine whether a timing error occurs.

According to the second aspect, there is an effect that the timing analysis can be easily performed even when the semiconductor integrated circuit operates at a plurality of clock frequencies. In a third aspect of the first invention, in the second step,
The clock delay time is multiplied by the first coefficient λ, the data delay time is multiplied by the second coefficient μ, and it is assumed that the set (λ, μ) changes in accordance with the change of the physical condition. Of the delay time difference α, and in the third step, corresponding to each of the plurality of values of the delay time difference α, the third time (T11−α) and the fourth time (T12 + α).
Ask for.

In the third aspect, the timing is assumed assuming that the first coefficient of the clock delay and the second coefficient of the data delay are different due to changes in physical conditions such as voltage changes, temperature changes, and semiconductor manufacturing process condition changes. Since the analysis is performed, the timing error under the bad condition is detected, the timing error detection omission is reduced, and the reliability of the semiconductor integrated circuit is improved. Since this process itself is simple, it hardly affects the logic design time.

In a fourth aspect of the first invention, a layout design is performed based on the logic design result obtained by executing any one of the above logic design methods, and a mask is manufactured based on the result of the layout design. A semiconductor integrated circuit is manufactured using the mask. According to the fourth aspect, it is possible to shorten the delivery time of the semiconductor integrated circuit.

A logic design apparatus according to a second aspect of the present invention is an apparatus for implementing the method of the first aspect of the present invention, in which the names and areas of gate-level elements corresponding to the technology of the semiconductor integrated circuit to be manufactured are registered. And a data processing device for inputting the specifications of the semiconductor integrated circuit described in the hardware description language, the simplified element shape, and the characteristics of the clock given to the semiconductor integrated circuit, and performing logic design based on the input And the data processing device uses the elements registered in the library to generate a netlist of gate-level circuits based on the specifications, and the area of the elements registered in the library. And an element size based on the element shape, and based on the netlist and the element size, the element size is determined on the floor corresponding to the chip of the semiconductor integrated circuit. Dynamic placement and automatic wiring between elements are performed more roughly than in the layout design stage, a signal delay time is obtained based on the result of the automatic placement and automatic wiring, and the signal delay time is calculated based on the characteristic of the signal delay time and the clock. Timing analysis of signals in flip-flops in a semiconductor integrated circuit is performed.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of a logic design device. This design is applied to a master slice type gate array, sea of gate, etc., and a standard cell type.

The design specification 10 relates to the function and structure of a semiconductor integrated circuit described in a hardware description language (HDL). The design specification 10 includes information on the shape of elements arranged in the following floor planning, for example, a square or a rectangle whose sides in one direction have a fixed length. The logic synthesis unit 11 and the floor planning unit 12 correspond to different programs installed in the same computer.

The library 13 is stored in the storage device. In the library 13, elements and their areas according to the technology of the semiconductor integrated circuit to be manufactured are registered. This area is, for example, based on the grid area used in layout design as a unit, and 100 flip-flops (FF) and 1 inverter (INV).
6. The number of NAND gates (NAND) is 25.

The logic synthesis unit 11 uses the elements registered in the library 13 to generate a gate level circuit based on the design specification 10 and supplies the netlist to the floor planning unit 12. The netlist has a hierarchical structure and is composed of a netlist in each functional block and a netlist between the functional blocks. The logic synthesis unit 11
The element size is obtained from the element shape included in the design specification 10 and the element area stored in the library 13, and the element size is supplied to the floor planning unit 12. For example, in the sea of gate or standard cell method, the element shape is a square, and patterns 31 to 33 shown in FIG.
The element size is determined as follows. Further, in the gate array, since the wiring region is between the basic cell columns,
As in the patterns 41 to 43 shown in (B), the length of the side in the width direction of the basic cell row determines the element size fixed to the width of the row. The reason for determining the element size in this way is to simplify the element shape and prevent the floor planning processing time from becoming long. The terminals of the device are on the sides.

By determining the element size based on the combination of the area and shape of the element, the amount of information to be registered in the library 13 can be reduced. The floor planning unit 12 roughly performs automatic placement and routing design on the floor 20 corresponding to the chip surface of the semiconductor integrated circuit based on the netlist and the element size. In order to reduce the calculation time, for example, each functional block is assumed to be a square, and its size is obtained by multiplying the total area of the elements in the functional block by a constant. First, the functional blocks are automatically arranged on the floor 20, and global wiring is performed between the functional blocks.
Next, for each functional block, automatic placement of the elements of the above size and automatic wiring between the elements are performed. In the general automatic placement and routing design, the rule of the automatic placement and routing in the layout design is weakened in order to reduce the calculation time. For example, the rule is weakened by ignoring the partial overlap between elements, and instead, the grid spacing is made larger than in the case of actual arrangement (arrangement in layout design).

FIG. 1 shows the result of a part of floor planning within one functional block. D flip-flop 2
1, the buffer gate 22, the D flip-flops 23 and 24 are cascaded in this order. The clocks CK1 and CK2 input to the external terminals are supplied to the clock input terminals of the D flip-flops 21 and 23 via the wirings L1 and L2, respectively. Wirings between the D flip-flop 21 and the buffer gate 22 and between the buffer gate 22 and the D flip-flop 23 are L3 and L4, respectively.
And The signals at the data input terminal, the data output terminal and the clock input terminal of the D flip-flop 21 are D1 and
D2 and CK1 '. Also, the D flip-flop 2
The signals at the data input terminal, the data output terminal, and the clock input terminal of No. 3 are D2 ′, D3, and CK2 ′, respectively. These signals are shown in FIG.

For simplification of explanation, the clock CK
Although 1 and CK2 are input to the external terminal, the clock CK2 may be the clock CK1 divided in the semiconductor integrated circuit. The trigger edge of the clock for the flip-flop is the rising edge, and the periods of the clocks CK1 and CK2 are TP1 and T, respectively.
P2, the trigger edge of clock CK2 and clock C
The time difference between the trigger edges of K1 is T11. Period TP
1, TP2 and the trigger edge time difference T11 are included in the design specification 10 as the characteristics of the clocks CK1 and CK2 input to the external terminals.

The wiring length is determined by floor planning,
The wiring capacitance is obtained by multiplying the wiring length by the wiring capacitance per unit length. For example, the time difference (delay time) Δt11 between the clock CK1 ′ and the clock CK1 is obtained based on the sum of the wiring capacitance of the wiring L1 and the input capacitance of the clock input terminal of the D flip-flop 21. Delay time Δt
2 is the time difference between the clock CK2 'and the clock CK2. The delay time Δt13 is the sum of the delay time based on the wiring L3 and the input capacitance of the D flip-flop 21, the signal propagation delay time of the buffer gate 22, and the delay time based on the input capacitance of the wiring L4 and the D flip-flop 23. Is.

Generally, the delay time of the rising edge of the signal and the delay time of the falling edge of the signal are different from each other, but since the delay times obtained by the floor planning are approximate values, they are assumed to be the same. The library 13 also stores the input capacitance of the device, the signal propagation delay time, the setup time ST of the flip-flop, and the hold time HT as the device characteristics. Here is the setup time S
T is generally the time during which the signal level does not change before the trigger edge of the signal input to the first end of the circuit,
If it is shorter than the setup time ST, it means that the operation is not guaranteed. The hold time HT is generally a time that means that the operation is not guaranteed if the time during which the signal level does not change after the trigger edge of the signal input to the first end of the circuit is shorter than the hold time HT. . The setup time ST and the hold time HT differ depending on which range is regarded as a target circuit. In the case of a flip-flop, the first end and the second end are a clock input end and a data input end, respectively.

The logic synthesizer 11 analyzes and adjusts the timing of the flip-flops based on the floor planning result. Next, this process will be described with reference to FIG. For ease of understanding, the analysis and adjustment of the timing of the D flip-flop 23 will be mainly described. Hereinafter, numerical values in parentheses are step identification numbers in the figure. (50) Clock CK1 cycle TP1 and clock CK2
The greatest common divisor GCD with the period TP2 of is calculated. For example,
When TP1 = 10 ns and TP2 = 20 ns, GCD =
It is 10 ns.

(51-53) Trigger edge time difference T11
Is not 0, S = T11, H = GCD-T11, and if the trigger edge time difference T11 is 0, S = GC
Let D and H = 0. The times S and H correspond to the setup time ST and the hold time HT of the D flip-flop 23 seen from the input ends of the clocks CK1 and CK2. Therefore, considering the signal delay, the times S and H are
Time T2 corresponding to the setup time ST and the hold time HT viewed from the input end of the D flip-flop 23
1 and T22 need to be converted.

(54) To perform this conversion, clock C
The signal delay time from the input end of K1 to the data input end of the D flip-flop 23 and from the input end of the clock CK2 to D
The difference α from the signal delay time to the clock input terminal of the flip-flop 23 is calculated. The delay time difference α is expressed by the following equation using the symbols in FIG. α = Δt11 + Δt12 + Δt13−Δt2 (1) The times T21 and T22 are T21 (α) = S−α and T22 (α) = H + α (2), as is apparent from FIG.

(55) This delay time difference α is a normal value, but it changes according to voltage fluctuations, temperature fluctuations, fluctuations in semiconductor manufacturing process conditions, and the like. In this case, if the rate of change in the clock delay time and the rate of change in the data delay time are different, the change in the delay time difference α is larger than in the case where the two are the same, so that a timing error is likely to occur.
Therefore, in order to detect the timing error under such a bad condition, the clock delay coefficient λ and the data delay coefficient μ are introduced, and the delay time difference α in the above equation (1) is rewritten as the following equation.

Α = λ (Δt11−Δt2) + μ (Δt12 + Δt13) (3) The clock delay coefficient λ and the data delay coefficient μ are changed as shown in FIG. Generally, when the clock delay coefficient λ increases, the data delay coefficient μ also increases, and when the clock delay coefficient λ decreases, the data delay coefficient μ also decreases. Therefore, in the λ-μ Cartesian coordinate system, the point P (1,1) is a normal value, and the point A (0.85,0.85) point B (0.9,0.85) point C (1.25 , 1.1) Point D (1.25, 1.25) Point E (1.1, 1.25) Point F (0.85, 0.9) is connected in order with a straight line to obtain a hexagon ABCDEF Consider, and assume that λ and μ vary within this hexagon. Points A and D have λ / μ = 1, points B, C, E and F have λ
/ Μ ≠ 1. In general, λ / is less than when λ / μ = 1
Since it is considered that the variation of the delay time difference α is larger when μ ≠ 1, it is estimated that the timing error does not occur in the hexagon ABCDEF unless the timing error occurs at the four points B, C, E and F. .

From the above, points B, C, E and F
The value of the delay time difference α is obtained for each of the four points, and T21 (α) and T22 (α) are obtained correspondingly. (56) A timing error check is performed for each of the four delay time differences α. That is, if T21 (α)> ST and T22 (α)> HT (4) are satisfied for each of the four delay time differences α, it is determined that a timing error does not occur, and the process proceeds to step 58, and otherwise. Go to step 57.

(57) Timing error degree ST-T
21 (α) and H-T22 (α), the gate size of the buffer gate 22 is changed (buffer gate 22
Change the input capacitance and signal propagation time of), or wiring L1
Alternatively, a timing error is eliminated by inserting a buffer gate in the wiring L2. If the timing error is relatively small, it can be resolved by changing the buffer size.

(58) The trigger edge time difference T11 has an upper limit value and a lower limit value, and the above processing is performed for each of the upper limit value and the lower limit value. For example, the smaller one of the trigger edge time differences T11 and (GBD-T11) is set as the lower limit value, the larger one is set as the upper limit value, or the upper and lower limit values are described in the design specification 10. The above process is repeated for all the flip-flops designated by the design specification 10. For example, regarding the timing error of the D flip-flop 24, the D flip-flop 23 and the pair of the D flip-flops 23 and 24 are different from the pair of the D flip-flops 21 and 23.
It may be performed in the same manner as in the case of the timing error of the flip-flop 23. The timing error of the D flip-flop 21 is the same as that of the timing error of the D flip-flop 23 in the pair of the D flip-flops 21 and 23 with respect to the pair of the flip-flop and the D flip-flop 21 in the preceding stage. You can go to

Since the circuit configuration is partially changed by the timing adjustment, next, a netlist is extracted from the circuit on the floor 20 and is output. Based on this netlist, layout design and simulation are performed with a configuration not shown. In the present embodiment, in the logic design stage, rough floor planning is performed, and timing analysis is performed based on the result to detect the timing error. (1) Timing adjustment is more accurate and the number of repetitions of logic design and layout design is reduced as compared with the conventional method in which a timing simulation is performed by performing a logic simulation in consideration of delay, resulting in a semiconductor integrated circuit. Shortened the design period of
(2) Timing errors can be detected in a much shorter time than in the conventional logic simulation in which the entire circuit is intricately entangled, which shortens the design period of the semiconductor integrated circuit.

Further, in the timing analysis, since the timing error is detected on the assumption that the clock delay coefficient and the data delay coefficient are different due to voltage fluctuation, temperature fluctuation, semiconductor manufacturing process condition fluctuation, etc., timing error detection omission is made. Is reduced and the reliability of the semiconductor integrated circuit is improved. Since this process itself is simple, it hardly affects the logic design time.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a logic design device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of an element size determination method.

FIG. 3 is a flowchart showing timing analysis and adjustment.

FIG. 4 is a timing chart of a circuit on the floor shown in FIG.

FIG. 5 is a diagram showing changes in delay coefficients of clock and data used in timing error check.

[Explanation of symbols]

 10 Design Specifications 11 Logic Synthesis Section 12 Floor Planning Section 13 Library 20 Floors 21, 23, 24 D Flip-Flop 22 Buffer Gate

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[Procedure amendment]

[Submission date] May 9, 1996

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] All figures

[Correction method] Change

[Correction contents]

FIG.

[Fig. 2]

[Figure 5]

[Figure 3]

FIG. 4

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiaki Sugioka 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Hisashi Hayashi 3-28-1, Joto, Oyama City, Tochigi Prefecture Fujitsu Cadtech Co., Ltd. In-house (72) Inventor Shoichi Okawa 3-2-1, Joto, Oyama-shi, Tochigi Prefecture Fujitsu Cadtech Co., Ltd.

Claims (6)

[Claims] 1. The specifications of the semiconductor integrated circuit described in a hardware description language are registered in advance in the library with the names of the gate level elements and the areas of the elements according to the technology of the semiconductor integrated circuit to be manufactured. , A simplified element shape and characteristics of a clock to be given to the semiconductor integrated circuit are input to a data processing device, and the data processing device uses an element registered in the library, and a gate level circuit based on the specification. And a logic synthesis step of determining an element size based on the area of the element and the element shape registered in the library, and the semiconductor based on the netlist and the element size. A floor plan that performs automatic placement of the elements and automatic wiring between the elements on the floor corresponding to the chip of the integrated circuit more roughly than at the layout design stage. And a signal delay time is obtained based on the result of the automatic placement and the automatic wiring, and the timing analysis of the signal in the flip-flop in the semiconductor integrated circuit is performed based on the signal delay time and the characteristics of the clock. A logic design method characterized by executing a timing analysis step and. 2. A timing adjusting step of eliminating a timing error by correcting a circuit on the floor based on a result of the timing analysis, and a semiconductor integrated circuit on which the timing is adjusted on the floor. And a netlist extraction step of extracting a netlist from, and a logic design method characterized by: 3. The output of the first flip-flop is supplied to the second flip-flop on the floor, and the first clock from the first point and the second clock from the second point are respectively supplied to the first flip-flop and the second flip-flop. The second flip-flop is supplied to the clock input terminal, and the timing analysis step is substantially the same as the trigger edge of the second clock at the second point and the trigger edge of the first clock at the first point. And a second time difference T11 which is a difference (GDC-T11) between the greatest common divisor GDC between the cycle of the first clock and the cycle of the second clock and the trigger edge time difference T11.
12, a signal delay time between the first point and the data input terminal of the second flip-flop, and a signal delay time between the second point and the clock input terminal of the second flip-flop. The second step of obtaining the delay time difference α which is the difference from the signal delay time, the third step of obtaining the third time (T11−α) and the fourth time (T12 + α), the third time and the fourth time The setup time ST and the hold time H of the second flip-flop, respectively.
4. The logic design method according to claim 1, further comprising a fourth step of comparing with T to determine whether a timing error occurs. 4. In the second step, the clock delay time is multiplied by a first coefficient λ and the data delay time is multiplied by a second coefficient μ,
Assuming that the set (λ, μ) changes according to the change of the physical condition, the value of the delay time difference α with respect to the values of (λ, μ) of the plurality of sets is obtained, and in the third step, the delay time difference α is obtained. The logical design according to any one of claims 1 to 3, wherein the third time (T11-α) and the fourth time (T12 + α) are obtained corresponding to each of a plurality of values of Method. 5. A layout design is performed based on a logic design result obtained by executing the logic design method according to claim 1, and a mask is manufactured based on the result of the layout design. Then, a semiconductor integrated circuit is manufactured using the mask. 6. A library in which the names and areas of gate-level elements corresponding to the technology of manufactured semiconductor integrated circuits are registered, and the specifications of the semiconductor integrated circuits described in a hardware description language are simplified. A data processing device for inputting an element shape and characteristics of a clock to be given to the semiconductor integrated circuit, and performing a logic design based on the input; and the data processing device uses an element registered in the library. , Generating a netlist of gate level circuits based on the specifications, determining an element size based on the area of the element and the element shape registered in the library, and determining the netlist and the element size. On the basis of the above, on the floor corresponding to the chip of the semiconductor integrated circuit, the automatic arrangement of the elements and the automatic wiring between the elements are roughly performed from the layout design stage, A signal delay time is obtained based on a result of automatic placement and automatic wiring, and timing analysis of a signal in a flip-flop in the semiconductor integrated circuit is performed based on the signal delay time and the characteristics of the clock. Logic design device.