JPH09259072A - Communication controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve data transfer efficiency and to enhance the reliability of transfer data by providing a register capable of setting a required data byte number to a transmission/reception buffer for issuing the DMA critical request of priority higher than a transmission/reception dynamic memory access(DMA) request in a built-in serial part. SOLUTION: In this communication controller dedicated to transmission/ reception adapted to the transmission/reception by plural transmission/reception channels and provided with first in first out memories (FIFOs) 13, 14, 16 and 18 for plural stages, DMA critical request registers 10 and 20 for issuing the DMA critical request of the priority higher than the DMA request are provided. Then, by the emergency degree of data transfer, the transmission/reception operations of the respective channels are switched. Thus, bus arbitration is controlled by the priority of the data transfer for a bus right and the data are efficiently and quickly transmitted/received.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control device used in the data communication field.

[0002]

2. Description of the Related Art FIG. 8 shows the configuration of a conventional communication control device.

At the time of reception, serial data is fetched from the reception data bus 34 into the FIFO control circuit 35, and the received serial data is written into the reception FIFO 37. Receive FIF
The data written in O is taken into a direct memory access controller (hereinafter abbreviated as DMAC) 39, and passed through an internal data bus 42, and the received data is sent to the MPU of 40 and the memory of 41.

At the time of transmission, 40 MPUs and 41 memories send the transmitted data to the 39 via the internal data bus 42.
To the DMAC. The DMAC writes the transmission data in the transmission FIFO of 38, is transmitted to the FIFO control circuit of 35, and is transmitted from the transmission data bus of 33 as transmission data (serial data) to other MPUs, memories and the like.

As the reception / transmission start timing, the value set in the register for determining the threshold and the number of data written in the reception and transmission FIFO are set to 35.
If the formula of the value set in the register that determines (the number of data in FIFO)> (threshold) is satisfied by comparing in the FIFO control circuit,
A receive or send DMA request was issued.

[0006]

In the above prior art, since there is only one timing for starting data transfer for each of transmission and reception, when there are a plurality of transmission and reception channels, a transfer request for each channel is made. Since the urgent level cannot be judged from the data transfer side, it is necessary to set the threshold low in order to make the underrun and overrun margins even. Therefore, even when the amount of data transfer due to transmission and reception is small, a data transfer request is generated due to the accumulation of a small amount of data, which deteriorates the data transfer efficiency.

An object of the present invention is to solve the above-mentioned problems of the prior art, to provide a communication control device which has a high data transfer efficiency and can improve the reliability of the transfer data.

[0008]

In order to achieve the above object, a DMA critical request having a higher priority than a transmit and receive dynamic memory access (hereinafter abbreviated as DMA) request is issued to a built-in serial section. , A register was provided in the send and receive buffers to set the required number of data bytes.

In a communication control device applied to transmission and reception by a plurality of transmissions and reception channels, a transmission DMA critical request control register or a reception DMA critical request control register is provided so that a transfer request of each channel can be controlled. I chose

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A communication control device showing an embodiment of the present invention is shown in FIG.

Reference numeral 1 denotes a main body of the communication control device, which may be composed of a plurality of parts or one or a plurality of LSIs. Reference numerals 6 and 7 denote receivers which receive the reception data buses (serial) 2 and 3, convert them into parallel data, and store them in the reception FIFOs 13 and 15.
Reference numerals 8 and 9 denote transmitters that convert parallel transmission data input from the transmission FIFOs 16 and 18 into serial data.
It is transmitted as transmission data to the transmission data buses 4 and 5 (serial).

In the present embodiment, two receivers and two transmitters are drawn, and two serial channels are drawn. However, the present invention does not limit the number of serial channels and the number of receivers and transmitters. Absent. In this embodiment, the receiver and the transmitter can perform processing by a plurality of protocols such as bit synchronization, byte synchronization, and start-stop synchronization, but different combinations of these may be used. Further, other protocols (Ethernet, ISDN, frame relay, etc.) may be used alone or in combination to enable processing.

The data transferred from the receivers 6 and 7 is set to 1
Write to 3, 15 receive FIFOs.

The receive DMA request register 11 has a receive D
By setting the threshold for issuing the MA request, the DMA request is received by the 22 receive DMA request control circuit through the 12 and 14 receive FIFO control circuits according to the number of data bytes received. Compare the amount of data in the FIFO with the threshold value for issuing the receive DMA request, 24,
25 DMACs.

Reference numeral 21 is a transmission control register. This register sets the threshold value for issuing and releasing the transmission DMA request, and thereby issues and releases the DMA request according to the number of data bytes to be transmitted. 23, the transmission DMA request control circuit 23 compares the data amount in the transmission FIFO with the threshold value for issuing the transmission DMA request, and the DMACs 26 and 27 are compared.
Sent to

Reference numeral 10 is a receive DMA critical request register. This register sets a threshold value for issuing a receive DMA critical request so that the DMA critical request is passed through the FIFO control circuits of 12 and 14 and the receive DMA of 22 according to the number of data bytes received. The request control circuit compares the amount of data in the reception FIFO with the threshold value for issuing the reception DMA request.
25 DMAC. This reception critical request is set so that the side deprived of the right to use the bus does not overrun when data with high urgency must be transferred while transferring data with low urgency. Receive D
It is controlled by the MA request control circuit.

Reference numeral 20 is a transmission DMA critical request register. This register sets the threshold value for issuing the transmit DMA critical request, so that the DMA critical request is transmitted through the transmission FIFO control circuit of 17 and 19 according to the number of data bytes to be transmitted, and the transmission of 23 transmissions. The data is transferred to the DMACs 26 and 27 via the DMA request control circuit.

In this embodiment, 10, 11, 20, 21,
Although 22 and 23 are drawn one by one, the present invention does not limit the number of registers. 24, 25, 26, 2
Reference numeral 7 is a DMAC channel. The DMAC channel given the bus right by the bus arbitration circuit 31 is a reception FIFO 13, 15.
Data is transferred between the transmission FIFOs 16 and 18 and the internal data bus 28, and at the same time, the bus interface 29 is controlled to transfer data to and from the external bus 30.

When the bus acknowledge signal 32 is returned from the external bus master, the bus arbitration circuit 31 activates any one of the signal lines connecting the bus arbitration circuit 31 and the DMACs 24, 25, 26, 27, and the connection destination Give the bus right to the DMAC channel.

The bus arbitration method may be a rotation priority method that gives the bus right to each channel in sequence, a fixed priority method that gives the bus right to a specific channel preferentially, or a method that gives the bus right randomly. The present invention does not impose any restrictions on the priority scheme.

The bus master may exist externally,
It can also be built in the communication control device. Further, the number of bus masters may be one or more.

To the tip of the external data bus 30, any one or all of a bus master, a memory, and peripheral devices are connected. All of these may be located outside the communication control device, or any or all of them may be built in the communication control device. The transmission FIFOs 16 and 18 temporarily store the transmission data, and the reception FIFOs 13 and 15 temporarily store the reception data. In this embodiment, the number of stages of each FIFO is 64, but the number of stages of each FIFO can be set to any number.

FIG. 2 shows a receiving DMA request generator and a receiving DMA for one receiving channel in the first embodiment.
The structure of a critical request generation part is shown.

The operation will be described with reference to the reception operation flow of FIG.

The data received from the serial data bus 2 is taken into the receiver 6 and written in the receive FIFO 13. Information of the reception FIFO is stored in the reception FIFO of 12
If it is fetched by the control circuit and (the number of data in the reception FIFO) ≧ (the number of data in the reception DMA request register) is not satisfied, the reception data is fetched again.

(Number of data in reception FIFO) ≧ (reception D
(Number of data in MA request register), a receive DMA request is issued, and 24 DMACs start data transfer. If the other DMA channels are (the number of data in the reception FIFO) ≧ (the number of data of the reception DMA critical request register), the bus right is passed to the channel which issued the reception DMA critical request, and the DMA transfer is stopped. The control of the bus right is performed by 31 bus arbitration circuits.

(Number of data in reception FIFO) ≧ (reception D
If it is not the number of data in the MA critical request register), the receiving operation is continued.

FIG. 3 shows a transmission DMA request generator and a transmission DMA for one transmission channel in the first embodiment.
The structure of a critical request generation part is shown. 21-0,
Since 21-1 is used in the present embodiment, two 21-1 are divided.

Next, the transmission operation will be described with reference to the transmission operation flow of FIG. The transmission data is fetched from the external data bus 33, the bus interface 32 and the internal data bus 28 are returned, and the data is transmitted to the DMAC 27. 27 DMAC sends transmission data to 18 transmission F
The data is transferred to the IFO and the information in the transmission FIFO is extracted by the 19 transmission FIFO control circuit. Here, if the set value of the transmission DMA request register 0 of 21-0 is (the number of data in the transmission FIFO) ≦ (the number of data of the transmission DMA request register 0), the transmission DMA request is issued and the 27 DMAC Start data transfer. At this time, the bus arbitration circuit 31 acquires the bus right if another channel does not have the bus right.

If the set value of the transmission DMA request register 1 of 21-1 is (the number of data in the transmission FIFO) ≧ (the number of data of the transmission DMA request register 1), the transmission DMA request is canceled and the 27 DMAC Stop data transfer. At this time, the bus right is relinquished by the bus arbitration circuit 31.

Reference numeral 23 is a transmission DMA critical request register, which sets a threshold value for issuing a transmission DMA critical request. If the other DMA channels are (the number of data in the transmission FIFO) ≧ (the number of data of the transmission DMA critical request register), the bus right is immediately transferred to the above DMA channel,
The 27 DMAC stops the data transfer. If (the number of data in the transmission FIFO) ≧ (the number of data in the transmission DMA critical request register) is not satisfied, the transmission operation is continued. The bus right is controlled by the bus arbitration circuit 72.

The generation timing of the receive DMA request and the receive DMA critical request signal in the embodiment of the present invention will be described below with reference to the receive operation time chart of FIG.

A is a reception data 1-byte fetch period, and B is a reception FIFO pointer setting period.
In this embodiment, for the sake of convenience, the reception data acquisition period and reception
Although the setting period of the FIFO pointer is synchronized, it is not always necessary to synchronize.

C is a reception DMA request signal, and reception F
When the value of the IFO pointer is fixed, receive at E
The MA request is issued and the reception DMA is released at F. The issue timing of this receive DMA request is determined by the value of the receive DMA request register.

D is a generation period of the reception DMA critical request signal. G is a reception DMA critical request signal generation timing, and H is a reception DMA critical request signal release timing. The generation timing of the receive DMA critical request signal is determined by the value of the receive DMA critical request register.

The generation timing of the reception DMA request and the transmission DMA critical request signal in the embodiment of the present invention will be described below with reference to the transmission operation time chart of FIG.

I is a transmission data 1-byte fetch period, and J is a transmission FIFO pointer setting period.
In this embodiment, the transmission data acquisition period and the transmission FIFO
The pointer setting period is synchronized, but it is not always necessary to synchronize.

K is the generation period of the transmission DMA request signal, and when the value of the transmission FIFO pointer is fixed, the transmission DMA request is issued at M, and the transmission DMA is canceled at N.

The timing of issuing this transmission DMA request is
It is determined by the value of the transmission DMA request register 0, and the release timing of the transmission DMA request is determined by the value of the transmission DMA request register 1.

L is the generation period of the transmission DMA critical request signal. O is a transmission DMA critical request signal generation timing, and P is a transmission DMA critical request signal release timing. The generation timing of the transmission DMA critical request signal is determined by the value of the transmission DMA critical request register.

[0041]

According to the present invention, it is possible to easily control bus arbitration and transmit / receive data efficiently and quickly by controlling the bus right according to the priority of data transfer.

Since neither overrun nor underrun occurs, the reliability of data transfer can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a supplementary explanation of FIG.

FIG. 3 is a block diagram showing a supplementary explanation of FIG.

FIG. 4 shows the operation of the embodiment of FIG.

5 shows the operation of the embodiment of FIG.

FIG. 6 shows a timing chart at the time of data reception for explaining the embodiment of FIG.

FIG. 7 shows a timing chart at the time of data transmission for explaining the embodiment of FIG.

FIG. 8 shows a block diagram of a conventional technique.

[Explanation of symbols]

1, 36 ... Communication control circuit, 2, 3, 34 ... Reception data bus (serial), 4,5, 33 ... Transmission data bus (serial), 6, 7, 37 ... Receiver, 8, 9, 38 ... Transmission Device, 10 ... Receive DMA critical request register, 11
... reception DMA request register, 12, 14 ... reception FIFO
Control circuit, 13, 15 ... Reception FIFO, 16, 18 ... Transmission FIFO, 17, 19 ... Transmission FIFO control circuit, 20
... Transmission DMA critical request register 21,21-
0, 21-1 ... Transmission DMA request register, 22 ... Reception D
MA request control circuit, 23 ... Transmission DMA request control circuit, 2
4, 25, 26, 27, 39 ... DMAC, 28, 42 ...
Internal data bus, 29 ... Bus interface, 30 ... External data bus, 31 ... Bus arbitration circuit, 32, 33 ... Bus arbitration circuit control signal line, 35 ... FIFO control circuit, 40 ...
MPU, 41 ... Memory, A ... Received data 1 byte fetch period, B ... Receive FIFO pointer setting period, C ... Receive DMA request generation period, D ... Receive DMA critical request signal generation period, E ... Receive DMA request generation timing,
F ... Receive DMA request release timing, G ... Receive DMA critical request signal generation timing, H ... Receive DMA critical request signal release timing, I ... Transmission data 1
Byte fetch period, J ... Transmission FIFO pointer setting period, K ... Transmission DMA request signal generation period, L ... Transmission DM
A critical request signal generation period, M ... Transmission DMA request generation timing, N ... Transmission DMA request signal release timing, O ... Transmission DMA critical request signal generation timing, P ... Transmission DMA critical request signal release timing.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Keiji Ichige 3-1-1, Saiwaicho, Hitachi, Ibaraki Hitachi Ltd. Hitachi factory (72) Inventor Shigeo Kuboki Sanukicho, Hitachi, Ibaraki 1-1-1, Hitachi Ltd., Hitachi Works (72) Inventor, Toshihiko Okada 3-1-1, Saiwaicho, Hitachi City, Ibaraki Hitachi Ltd., Hitachi, Ltd. (72) Satoko Iwama, Hitachi, Ibaraki Prefecture 3-2-1, Saikou-cho, Ichi, Hitachi, Ltd. (72) Inventor, Yoshiaki Yasshima 3-2-1, Saiwai-cho, Hitachi, Hitachi, Ibaraki (72) Inventor, Takashi Kawaguchi, Ibaraki 1-1, Saiwaicho, Hitachi, Ltd. Hitachi Works, Hitachi Works

Claims (4)

[Claims] 1. In a transmission-only communication control device, which is applied to transmission by a plurality of transmission channels and has a plurality of first-in-first-out memories (FIFOs), a direct memory access (DMA) request DMA issuing high priority DMA critical request
A transmission-only communication control device that has a critical request register and can switch the transmission operation of each channel according to the urgency of data transfer. 2. A reception-only communication control device which is applied to reception by a plurality of reception channels and which has a plurality of stages of FIFOs, wherein a DMA critical request register for issuing a DMA critical request having a higher priority than a DMA request is provided.
A reception-only communication control device capable of switching the reception operation of each channel depending on the urgency of data transfer. 3. A DMA critical request which is applied to reception / transmission by a plurality of reception / transmission channels and which issues a DMA critical request having a higher priority than a DMA request in a reception / transmission shared communication control device having a plurality of FIFO stages. Receive request register /
A shared reception / transmission communication control device provided on the transmission side and capable of switching the reception / transmission operation of each channel depending on the urgency of data transfer. 4. A DMA request and D are externally transmitted according to claim 3.
A shared reception / transmission communication control device having a terminal for outputting the occurrence of an MA critical request.