JPH09258959A - Floating point arithmetic processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the hardware quantity of a floating point computing element dealing with the floating point of an IEEE-754 system and to shorten the processing time of the floating point computing element. SOLUTION: A part for judging whether read data applies to any special number and outputting a flag signal 668 showing the type and a part for rewriting rewritten data when rewritten data applies to the special number by a following flag signal 668 are added to a storage device at the outer side of a floating point arithmetic processor and a LOAD/STORE unit 660 for reading/ writing data. Routes 611, 612 and 631 for transferring the flag signals with numeric data are provided in the floating point arithmetic processor. Thus, only simple logic circuits 655 generating the flag signals 656 and 657 of input data and the flag signal 658 of output data from output data 653 of a computing element 650 are provided for the respective floating point computing elements 650.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating point arithmetic unit, and more particularly to a floating point arithmetic processing unit for arithmetically operating numerical data of the format specified in IEEE-754.

[0002]

2. Description of the Related Art As a floating-point data format, "IEEE
E Standard for Binary Flo
ating Point Arithmetic, AN
SI / IEEE std 754-1985 "(hereinafter,
The IEEE-754 format) has become the de facto standard. The IEEE-754 format divides floating-point numeric data into an exponent part and a mantissa part, and defines a normal number and five special numbers by combining these numbers.

When handling the IEEE-754 format in a floating point arithmetic unit, a special correspondence to a special number is required unlike an arithmetic unit corresponding to a format in which only normal numbers are always input. That is, it is determined whether each of the plurality of numerical data input to the arithmetic unit is a normal number or one of the special numbers, and as a result, any one of the input numerical data corresponds to the special number, If an exception such as an overflow or underflow occurs even in the operation of ordinary numbers, it is necessary to replace the numerical data of the output result of the arithmetic unit with the correct numerical data of the special number according to the result. In addition, “Japanese Patent Laid-Open No. 4-281518”
"Digital signal processor"
In a digital signal processor which did not handle the E-754 format, a method for handling numeric data of the IEEE-754 format arranged in an external memory by simple hardware is presented.

However, this shows a method of conversion into a numerical data format inside the digital signal processor. In this article, the hardware configuration for converting the special numbers in the IEEE-754 format into the two's complement format used inside the digital signal processor is described, but how the arithmetic unit itself handles these special numbers is described. Have not been touched.

[0005]

A first problem is that in a floating point arithmetic unit handling such an IEEE-754 format, the hardware amount of the entire arithmetic unit increases.

The reason for this is that, for each of a plurality of input numerical data, the hardware that determines which kind of numerical data defined by the IEEE-754 format corresponds to the numerical data, and the numerical data obtained here Type, or even if it is an operation between ordinary numbers, if an exception of overflow or underflow occurs, the hardware for replacing the numerical data of the output result from the arithmetic unit with the numerical data of an appropriate special number. This is because clothing is needed.
Recently, the degree of integration of LSIs has become extremely high, and it has become uncommon for a microprocessor to have multiple floating-point arithmetic units on a single chip if it has an architecture such as superscalar or VLIW. Serious to.

The second problem is that the performance deteriorates due to the increase in the processing time of the entire arithmetic unit.

The reason is that the new hardware described for the reason of the first problem is required, and therefore the processing by these additional hardware is required in addition to the processing by the normal arithmetic unit. Because. In particular, since the process of replacing the numerical data of the output result cannot be executed in parallel with other processes inside the arithmetic unit, the processing time in this part is increased as it is. Obviously, such an increase in the processing time of the arithmetic unit has a great influence on the acceleration of the clock cycle.

The present invention solves the above problems and reduces the amount of hardware and the arithmetic processing time in a floating point arithmetic processing unit that handles numerical data in the IEEE-754 format, especially when handling special numbers. It is an object of the present invention to provide a floating point arithmetic processing device capable of performing the above.

[0010]

A floating-point arithmetic processing unit according to the present invention includes at least one floating-point arithmetic unit, input data to the floating-point arithmetic unit, and output data from the floating-point arithmetic unit. A storage device for storing data, a means for reading input data to the floating point arithmetic unit from at least one or more of the storage units, and a transfer unit for transferring the read data between the reading unit and the floating point arithmetic unit. 1 or more paths, means for writing back output data from at least one or more of the floating point arithmetic units to the storage device, and transfer of writeback data between the floating point arithmetic units and the writing back means 1 One or more paths, and the read data is a predetermined floating value in the means for reading data from the storage device to the floating point arithmetic unit. Same as the means for detecting that the data matches the type of specific data of several points and outputting the state as data different from the read data, and the operation result of inputting the data representing the type of the specific data. Means for outputting data representing the specific data type and means for outputting the data representing the specific data type in the means for writing back the output data of the floating point arithmetic unit to the storage device. Accordingly, means for replacing the output data of the floating point arithmetic unit with the specific data is newly added.

[0011]

[Operation] Numerical data input to the floating point arithmetic unit is
In the means for reading data from a storage device external to the floating point arithmetic processing unit of the present invention and supplying it to an arithmetic unit, the IE
At the same time, whether a normal number of EE-754 format or a particular special number is detected is detected and a flag signal representing these particular types is added to the numerical data.

Further, in the means for writing back the numerical data from the floating point arithmetic processing unit of the present invention to the external storage device, the numerical data which is actually written back from the flag signal representing the specific special number in the IEEE-754 format is the correct data pattern. Replace with.

Each floating-point arithmetic unit in the floating-point arithmetic unit of the present invention looks at the input numerical data and the flag signal accompanying it, and if the flag signal represents a special number, the input flag signal A combination logic circuit generates a flag signal representing a special number of the output numerical data. At this time, the numerical data actually output from the arithmetic unit is ignored. By constantly transferring this flag signal together with the numerical data in the floating-point arithmetic unit of the present invention, it is possible to eliminate the hardware for detecting the special number in each arithmetic unit and the hardware for replacing the output.

[0014]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a double precision format of the IEEE-754 format and a data pattern representing the types of special numbers at that time.

In the double precision of the IEEE-754 format, it consists of a sign 1 bit, an exponent 11 bits, and a mantissa 52 bits.
Then, depending on the specific data pattern of the exponent and the mantissa, zero (Z
ERO), infinity (∞), two types of not-a-number (sNaN, q
A total of five special numbers, NaN) and minute fixed point numbers (denormal), are defined. The numbers other than these special numbers are called normal numbers.

FIG. 2 is a block diagram showing an example of a conventional floating point arithmetic unit that handles such an IEEE-754 format.

Two input operand data 200, 20
Floating point arithmetic unit (arithmetic unit main body) 240 with 1 as input
In addition to the input operand data 200, 20
It is detected whether 1 matches any one of the data patterns of the special numbers, and the flag signal of an appropriate format (hereinafter,
There are operand status generation circuits 251 and 252 for generating 210 and 211 (operand status). The output of the floating point arithmetic unit (arithmetic unit main body) 240 is sent to an exception processing circuit 260 which performs exception processing at the time of underflow or overflow. On the other hand, the operand statuses 210 and 211 are sent to the output status generation circuit 270 which is a simple combinational logic circuit for determining the operand status 230 of the output data according to the state. Output data 220 that has passed through the exception processing circuit 260
Is the operand status 23 of this output data 220.
If 0 indicates a special number, it needs to be replaced with a data pattern according to the type. The output replacement circuit 280 does this.

FIG. 3 is a block diagram for explaining the details of the operand status generation circuit 251 or 252 which constitutes such a floating point arithmetic unit.

The operand status generation circuit 251 or 252 detects a plurality of comparators 311 and 31 for detecting whether the input operand data 300 matches the special number data patterns 301, 302, 303, 304 and 305.
2, 313, 314, 315 and their comparators 31
1, 312, 313, 314, 315 and an encoder 320 for generating a desired operand status 330.

FIG. 4 is a block diagram for explaining the details of the output replacement circuit 280 which constitutes the floating point arithmetic unit as shown in FIG.

The output replacement circuit 280 is a selection circuit 430 which receives the output data 400 in the case of a normal number from the arithmetic unit and the data patterns 401, 402, 403, 404, 405 of each special number, and the output data to be replaced. And a decoder 420 for generating a switching control signal of the selection circuit 430 from the operand status 410 of the above.

As described above, the conventional floating-point arithmetic unit that handles the IEEE-754 format has a structure in which it is detected whether or not the input operand is a special number for each arithmetic unit, and the output data is replaced accordingly. I was collecting.

In the floating-point arithmetic processing unit according to the present invention, the operand status is carried around in the device at the same time as the operand, thereby simplifying the processing in the case of a special number.

FIG. 5 is a block diagram showing the configuration of each floating point arithmetic unit in the floating point arithmetic processing unit according to the embodiment of the present invention.

An arithmetic unit body 540 that performs an operation by a plurality of input operands 500 and 501 to generate an output operand 520, input operand statuses 510 and 511 associated with each input operand 500 and 501, and an output operand of the arithmetic unit body 540. An output operand status generation circuit 570 which is a combinational logic circuit for generating an operand status of the output operand 520 with 520 as an input.

When at least one of the input operand statuses represents a special number status, the output operand status outputs any special number status in accordance with a predetermined rule. Even if the input operand statuses are all normal numbers, underflow or overflow may occur depending on the output operand 520 of the arithmetic unit body 540. In IEEE-754, the output at underflow is Z
It is regulated to be ERO, and at the time of overflow, it is regulated to output either ∞ or the maximum value that can be taken as a normal number depending on the rounding mode. Therefore, the output operand status generation circuit 570 configures the logic circuit so that the output operand 520 is also used as an input and an appropriate output operand status is output when the above exception occurs.

It should be noted that the largest value (hereinafter, the maximum number) that can be taken from the normal number that may be output at the time of overflow is not a special number by nature, but is output at the time of an exception, and specific data. It is clear that it makes sense to add operand statuses other than the normal number in addition to the operand statuses of the five kinds of special numbers in consideration of the pattern.

FIG. 6 is a block diagram showing an embodiment of the entire floating point arithmetic processing unit according to the present invention.

In particular, this is an example applied to a floating point arithmetic processing system of a microprocessor in which an integer arithmetic processing system and a floating point arithmetic processing system are separated.

A floating point register file (RF) 640 having data read ports 641 and 642 and a data write port 643, and a floating point status register file (RF) 6 having status read ports 646 and 647 and a status write port 648.
45, a floating point arithmetic unit 650, an output operand status generation circuit 655, and a LOAD / STORE unit 66 for inputting / outputting data to / from a storage device outside the drawing.
0, and the respective constituent units are mutually connected by an operand data bus 601, 602, 621 and an operand status bus 611, 612, 631.

The operation of the floating point arithmetic processing unit according to this embodiment will be described with reference to the drawings.

Floating point register file (RF) 64
A plurality of floating point data are stored in 0. On the other hand, the operand status for each floating point data is stored in the floating point status register file (R
F) Floating point register file (RF) in 645
It is stored at the same address as the address of 640.
Necessary data from the floating point register file (RF) 640 is output to the read ports 641 and 642 at an address given by an instruction processing system outside the drawing. At this time, the same address is also given to the floating point status register file (RF) 645, and the operand status corresponding to each data is read out from the read port 64.
6, 647 is output. Operand data is read ports 641 and 6 of the floating point register file 640.
42, it outputs to the operand data buses 601 and 602, and transfers these operand data to other processing elements which require them. At the same time, the operand status is also read from the read ports 646 and 647 of the floating point status register file 645 from the operand status bus 61.
It is output to 1,612 and transferred.

The floating point arithmetic unit 650 has required operands 651 and 651 from the operand data buses 601 and 602.
652 is obtained and the calculation result 653 is output. At the same time, the output operand status generation circuit 655 acquires the respective operand statuses 656 and 657 on the operand status buses 611 and 612 in association with the input operands 651 and 652 to the floating point arithmetic unit 650, The operand status 658 to be attached to the output operand 653 is generated while also detecting the exception of the output operand 653 of 650. Output operand 653 and output operand status 6
58 is output to the operand data bus 621 and the operand status bus 631, respectively, and transferred to another processing element.

Usually, the data is often written back to the register file again, the operand data is written back from the write port 643 of the floating point register file (RF) 640, and the operand status is written back to the floating point register file (RF). ) Floating point status register file (RF) 6 identical to 640 address
It is written back from the write port 648 to the address in 45.

As described above, in the floating-point arithmetic processing unit of the present embodiment, the function of each arithmetic unit is omitted by transferring the operand data together with the operand status indicating the type of the data. . However, when accessing data to the outside of the floating point arithmetic processing unit of the present embodiment, it is necessary to make the data compliant with the original IEEE-754 format. This role is LOAD / ST
The ORE unit 660 is in charge.

FIG. 7 shows the LOAD / STORE unit 6
It is a block diagram showing the detail of 60 (refer FIG. 6).

The LOAD / STORE unit 660 (see FIG. 6) is an address adder 750 for generating an execution address for accessing an external storage device and a TLB which is a table for converting a logical address into a physical address. (Translation Lookaside
e Buffer) 760 and write-back data to IEEE
Operand replacement circuit 770 for conforming to the E-754 format, status generation circuit 780 for generating an operand status for use in the floating point arithmetic processing unit of this embodiment from read data, and write data for external memory Is output, or read data is input, and a switch 790 for switching the memory access path 740.

Next, the operation of the LOAD / STORE unit 660 (see FIG. 6) will be described.

Operand data 700 and 701 for calculating an execution address are input from an integer arithmetic processing system outside the floating point arithmetic processing unit of this embodiment. The address adder 750 adds these operand data 700 and 701 to obtain an execution logical address. In order to access the actual external memory, it is necessary to convert the logical address into a physical address. Therefore, a part of the output of the address adder 750 is used to access the TLB 760 to obtain the physical address 730. Note that the microprocessor of this embodiment adopts such a configuration because it needs to convert such a logical address into a physical address. However, when the microprocessor does not have a logical address, as in a digital signal processor, for example, It is clear that the TLB 760 described in the present embodiment is not required for the above.

On the other hand, the operation at the time of writing back data as the processing of the data system will be described first.

The normal write-back data may be output to the memory access path 740 as it is, but in the floating-point arithmetic processing unit of this embodiment, a special number in the IEEE-754 format is represented as an operand status, which is correct for an actual data pattern. No value has been set. Therefore, since only the data cannot be written back as it is, the operand replacement circuit 770 that replaces the data pattern of the write-back data 710 with an appropriate one according to the value of the operand status 711 is necessary. This operand replacement circuit 770 can be realized by adopting a configuration substantially the same as the circuit in which the output section of each conventional floating point arithmetic unit existed, and for example, the configuration shown in FIG. 4 can be used.

Next, the operation for reading data will be described.

When the read data is also a normal number, there is no particular problem, but when the special number of data is read, the special number can be recognized in the floating-point arithmetic processing unit of the present invention if the operand status does not exist. Can not.
Therefore, when the data pattern of the read (Read) data 720 is checked and it is a special number, the status generation circuit 780 which simultaneously outputs the appropriate operand status 721 is required. This status generation circuit 78
0 can also be realized by adopting almost the same configuration as the circuit existing in the input part of the conventional floating point arithmetic unit, and for example, the configuration shown in FIG. 3 can be used.

Returning to the embodiment of the present invention shown in FIG. 6, when the data is written back to the external memory from the LOAD / STORE unit 660, the write-back data 661 is transferred from the operand data bus 601 to the operand. The operand status 666 associated with the data is transferred from the status bus 611 to the LOAD / STORE unit 660, the operands are replaced according to the above operation, and then the data is written back to the external memory using the memory access path 680. The operand data 661 and the operand status 666 input to the LOAD / STORE unit 660 are often directly transferred from the floating point register file (RF) 640 and the floating point status register file (RF) 645.

On the other hand, in the case of reading data from the external memory, the data input from the memory access path 680 is generated in the LOAD / STORE unit 660 in accordance with the above operation to generate the operand data 663 and the operand status 668 accompanying it. . Then, they are transferred to other components by the operand data bus 621 and the operand status bus 631, respectively. These data and status are often written as they are to the floating point register file (RF) 640 and the address of the floating point status register file (RF) 645 which is the same as the address written to the floating point register file.

As described above, in the present embodiment, the processing for the special number, which is conventionally performed individually for each arithmetic unit, is made unnecessary by adding the operand status signal to each operand data, and the floating point arithmetic of this embodiment is performed. Hardware is reduced and processing is simplified by integrating the processing for the special number in a portion that accesses data with the outside of the processing device.

FIG. 8 shows a generalized example of the above embodiment.

N arithmetic units 850-1, ..., 850-
, 855-n, output operand status decision logic circuits 855-1, ..., 855-n, and m load / store units 860-1 ,. Also, the operand data bus is multiplexed 801-1, ..., 8
01-u, 802-1, ..., 802-u, 821-1,
, 821-v, and each operand status bus 811-1, ..., 811-u, 812-1, ..., 812.
-U, 831-1, ..., 831-v are also multiplexed according to the operand data bus. Of course, a floating point register file (RF) 840 for transferring multiple data simultaneously between each processing element on a multiplexed bus.
And floating point status register file (RF) 84
5 is also multi-ported.

The basic operation is the same as the operation described with reference to FIG. 6, a plurality of different data are transferred at the same time, and different arithmetic processes are executed by a plurality of processing elements.

In FIG. 8, the register file which is each processing element, the arithmetic unit and the LOAD / STORE unit are connected by a multiplexed bus structure. However, it is needless to say that the connection method is not limited to this. It is obvious that modifications such as a configuration in which each port and a specific processing element are directly connected, or conversely, a crossbar configuration in which the connection destination can be freely changed are possible.

An example of such a modification is shown in FIG.

Arithmetic unit # 1 (950-1) and arithmetic unit # 2
It has two arithmetic units of (950-2). Two output operand status decision logic circuits are provided for each arithmetic unit 955-
There are 1,955-2. In the input operand section of each arithmetic unit, a selection circuit 9 for switching the input of the operand from the operand data bus and the output operand of the other arithmetic unit.
91-1, 992-1, and 991-2, 992-2 are present. The same selection circuit 9 is also provided in the input parts of the corresponding output operand status determination circuits 955-1 and 955-2.
There are 96-1,997-1, and 996-2,997-2.

When it is desired to immediately use the output of one arithmetic unit in the other arithmetic unit, instead of writing it back to the register file via the bus once, the selection circuit is switched to directly input the output operand of the other arithmetic unit. By doing so, the processing time is shortened. Even in such a case, the present invention can be applied by providing a path for directly inputting the operand status together with the operand data and a selection circuit therefor.

Although the structure having the register file has been mainly described in the embodiment, it is obvious that the existence of the register file is not essential in the present invention. The present invention can be applied as long as there is a processing element that executes access to the outside and a processing element that performs actual calculation.

On the contrary, it is also clear that the storage device included in the floating point arithmetic processing unit of this embodiment is not limited to the register file. Especially for a primary data cache or the like integrated in the same microprocessor that needs to have a high access speed, if a slight increase in delay time due to an additional circuit in the LOAD / STORE unit according to the embodiment of the present invention poses a problem. The present invention can be applied by providing an area for simultaneously recording the status signal also in the primary data cache.

Further, in the above embodiment, if any one of the input operands to each arithmetic unit has a status indicating a special number, only the status signal is actually effective and the actual input to the arithmetic unit is The operand data and the output operand data that is the result of these operations are all ignored as invalid data. Therefore, it is possible to configure so as not to perform a wasteful operation on invalid data, and although not shown, for example, when one of the inputs from the output operand status determination logic circuit is a special number, the operation unit It is possible to stop the unnecessary calculation by issuing a control signal such as stopping the clock supply to the original or putting all the F / Fs in the calculation supply main unit into the hold state to reduce power consumption. Is.

[0058]

The first effect is that it is possible to reduce the amount of hardware of a floating point arithmetic unit that handles the IEEE-754 format. As a result, IEEE-7
It is possible to reduce the mounting area of the floating point arithmetic unit handling the 54 format on the LSI and improve the degree of integration of the microprocessor or the like.

The reason for this is that a part of the hardware conventionally held in each floating point arithmetic unit is aggregated in an interface portion with a storage device outside the floating point arithmetic processing unit of the present invention, and each floating point arithmetic unit is integrated. Because it has been reduced from. This effect is a superscalar processor and VLIW
This becomes more remarkable when a plurality of floating point arithmetic units such as a processor and a parallel arithmetic processor for image processing are built in one chip.

The second effect is that the processing time of the floating point arithmetic unit handling the IEEE-754 format can be shortened. As a result, it is possible to reduce the number of pipeline stages of the floating-point arithmetic unit that handles the IEEE-754 format and speed up the clock cycle, and it is possible to improve the performance of the microprocessor and the like.

The reason is that the floating point arithmetic unit according to the present invention is deleted by eliminating the replacement process for the data pattern of the special number of the IEEE-754 format which cannot be processed in parallel with the processing of the floating point unit. This is because the data is written back to the storage device outside the processing device. This is because the floating-point arithmetic processing is generally completed in about three times the clock cycle, whereas when accessing data to an external storage device, the processing time is several to several tens of times the clock cycle. Therefore, a slight increase in processing time in this part is possible because it has almost no effect on the processing performance of the entire microprocessor.

[Brief description of drawings]

FIG. 1 IEEE-754 format (double precision)
FIG. 3 is a diagram illustrating a data pattern representing a specific data type.

FIG. 2 is a block diagram illustrating a conventional floating point arithmetic unit.

FIG. 3 is a diagram illustrating details of a block that generates an operand status.

FIG. 4 is a diagram illustrating details of a block for replacing an output result of a floating point arithmetic unit according to an operand status.

FIG. 5 is a diagram illustrating a floating point arithmetic unit according to an embodiment of the present invention.

FIG. 6 is a block diagram showing an embodiment in which the present invention is applied to a microprocessor having a register file.

FIG. 7 is a diagram illustrating the details of a LOAD / STORE unit in FIG.

FIG. 8 is a block diagram showing an embodiment having a plurality of connection paths in the modified embodiment of FIG. 6;

FIG. 9 is a block diagram showing an embodiment having a interconnection path between a plurality of floating point arithmetic units in the modified embodiment of FIG. 6;

[Explanation of symbols]

210 X operand status signal 211 Y operand status signal 251 X operand status generation circuit 252 Y operand status generation circuit 510 Input operand status X 511 Input operand status Y 570 Output operand status determination logic circuit 640 Floating point data register file 641 Floating point data register File Read Port 1 642 Floating Point Data Register File Read Port 2 643 Floating Point Data Register File Write Port 645 Floating Point Status Register File 646 Floating Point Status Register File Read Port 1 647 Floating Point Status Register File Read Port 2 648 Floating Point Status Register File writing Port 650 Floating-point arithmetic unit body 651 Floating-point arithmetic unit input operand data 1 652 Floating-point arithmetic unit input operand data 2 653 Floating-point arithmetic unit output operand data 655 Floating-point arithmetic unit output operand status determination logic circuit 656 Floating-point arithmetic unit input Operand status 1 657 Floating-point calculator input Operand status 2 658 Floating-point calculator output operand status 660 LOAD / STORE unit 661 STORE operand data 663 LOAD Operand data 666 STORE Operand status 668 LOAD Operand status 680 Memory access port 801-1 Floating-point Operand data bus 1 # 1 801-u Floating point operand data bus 1 # 802-1 floating point operand data bus 2 # 1 802-u floating point operand data bus 2 # u 811-1 floating point operand status bus 1
# 1 811-u Floating point operand status bus 1
#U 812-1 Floating point operand status bus 2
# 1 812-u floating-point operand status bus 2
#U 821-1 floating point operand data bus 3 # 1 821-v floating point operand data bus 3 #v 831-1 floating point operand status bus 3
# 1 831-v floating point operand status bus 3
#V 840 Multiport floating point data register file 845 Multiport floating point status register file 850-1 Floating point arithmetic unit body # 1 850-n Floating point arithmetic unit body #n 855-1 Output operand status determination for arithmetic unit # 1 Logic circuit 855-n Output operand status determination logic circuit for arithmetic unit #n 860-1 LOAD / STORE unit # 1 860-m LOAD / STORE unit #m 950-1 Floating point arithmetic unit main unit # 1 950-2 Floating point arithmetic Main unit # 2 953-1 Floating-point arithmetic unit # 1 output operand data 953-2 Floating-point arithmetic unit # 2 output operand data 955-1 Output operand status decision logic circuit 955-2 For arithmetic unit # 2 Output operand status Decision logic circuit 958-1 Output operand status for arithmetic unit # 1 858-2 Output operand status for arithmetic unit # 2 991-1 X operand data input selection circuit for arithmetic unit # 1 991-2 X operand data for arithmetic unit # 2 Input selection circuit 992-1 Y operand data input selection circuit for arithmetic unit # 1 992-2 Y operand data input selection circuit for arithmetic unit # 2 996-1 X operand status input selection circuit for arithmetic unit # 1 996-2 Operation unit X operand status input selection circuit for # 2 997-1 Y operand status input selection circuit for arithmetic unit # 997-2 Y operand status input selection circuit for arithmetic unit # 2

Claims (4)

[Claims] 1. At least one floating point arithmetic unit, and a storage device for storing input data to the floating point arithmetic unit and output data from the floating point arithmetic unit.
Means for reading input data to the floating point arithmetic unit from at least one or more storage devices, one or more paths for transferring the read data between the reading means and the floating point arithmetic unit, Means for writing back the output data from the one or more floating point arithmetic units to the storage device; and one or more paths for transferring the writeback data between the floating point arithmetic units and the write back means. In the processing device, the means for reading data from the storage device to the floating-point arithmetic unit detects that the read data matches a specific data type of a predetermined floating-point format, and the state is detected as the read data. And a means for outputting as data different from the above, and a calculation result obtained by inputting data representing the type of the specific data According to data obtained by means for outputting data representing the type of data and means for outputting data representing the specific data type in the means for writing back the output data of the floating point arithmetic unit to the storage device. A floating point arithmetic processing device, comprising means for replacing output data of the floating point arithmetic unit with the specific data. 2. The floating point arithmetic unit has means for selecting a plurality of input data, a path for transferring the output data of the arithmetic result to the input of another floating point arithmetic unit, and a specific type of the output data. And a path for transferring output data representing the data to an input of another floating point arithmetic unit, and the plurality of floating point arithmetic units are mutually connected by the path. Processing unit. 3. Data from the data reading means and data from the one or more floating point arithmetic units,
A storage device for temporarily storing the data, a data representing a specific data type of the read data, and a data representing a specific data type of the write-back data. The floating-point arithmetic processing device according to claim 1, wherein 4. The floating point arithmetic unit further comprises means for stopping the execution of an operation based on normal input data when the data representing a specific type of input data is valid data. The floating point arithmetic processing unit according to Item 1.