JPH09257885A - Method for generating analyzing waveform of combinational logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively generate an analyzing waveform in a combinational logic circuit. SOLUTION: A truth table which indicates the corresponding relationship between an input signal pattern and an output signal pattern is formed (S1). Then, one input signal pattern is corresponded to one node, the input signal pattern in the table is expressed as a plurality of nodes, a pair of transition paths directed in bidirectional directions are defined between a pair of the nodes for satisfying the two conditions that Hamming distance is 1 and the output signal patterns are different, and a group made of one group of nodes is formed (S2). One cyclic route passing all the nodes in the group is obtained while tracing all the defined transition paths in forward direction (S3). Thereafter, the input pattern is transferred sequentially at the nodes along the one cyclic route to generate an input signal waveform, and a corresponding output signal waveform is generated based on the table (S4).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of generating a waveform for analysis in a logic circuit, and more particularly, to a combinational logic circuit formed by combining a plurality of logic gates with a waveform for analysis composed of an input signal waveform and an output signal waveform. Regarding how to generate.

[0002]

2. Description of the Related Art With the development of semiconductor circuit manufacturing technology, the degree of integration of circuits has been improved more and more, and LSIs in which a huge number of logic gates are integrated to realize complicated functions have come into widespread use. Generally, a logic circuit is an AND gate, O
It can be roughly classified into a combinational logic circuit formed by combining a large number of simple logic gates such as R gates, and a sequential circuit incorporating elements such as flip-flops. Since the operation of the sequential circuit depends on the logic state of the previous stage, its analysis requires information on the past logic operation, but the operation of the combinational logic circuit does not depend on the past logic state.
The logic pattern of the output signal can be uniquely determined based on the logic pattern given as the input signal. Therefore, a truth table showing the relationship between the input signal pattern and the output signal pattern can be defined, and all the logical operations of the combinational logic circuit can be expressed by this truth table.

When a new LSI logic circuit is designed, it is necessary to perform a logic analysis as to whether or not the logic circuit to be designed operates normally. Even if the correct design is done at the logic level, if the logic gate is realized by an actual transistor element, etc., the signal may be distorted or delayed due to the influence of the parasitic capacitance and parasitic resistance of each part. This is because the operation may not be performed. Such logic analysis is usually performed in the form of verification using a logic simulator. That is, it is determined by simulation whether a correct output signal waveform at the logic level can be obtained when a predetermined input signal waveform is given to this logic circuit. In order to perform analysis by such a simulation, an analysis waveform composed of a combination of an input signal waveform and an output signal waveform is required.

As described above, the analysis waveform in the combinational logic circuit is composed of the input signal waveform and the output signal waveform. Of course, in theory, any analysis waveform may be created, but in order to perform efficient verification, an analysis waveform that satisfies the following two conditions is created in practice. Is common.

First, the first condition is that the input signal waveform changes bit by bit. For example, 3
In the case of a logic circuit having a bit input signal, a waveform in which the input signal changes in the order of (000) → (001) → (011) → (111) has a 3-bit waveform. Since only one of these bits has changed, this means that the first condition is satisfied.
However, the signal waveform changing in the order of (000) → (011) → (100) does not satisfy the first condition. When performing verification by simulation, it is necessary to identify which input bit caused a change in a certain output bit, so a signal waveform in which multiple input bits change simultaneously is not desirable. Of.

The second condition is that a change in the input signal must cause some change in the output signal. For example, as described above, the input signal is (0
Even if the change is made in the order of (00) → (001) → (011) → (111), it is meaningless to verify if the output signal does not change at all. Since the original purpose of the verification is to check whether or not the output signal has a logically correct change by changing the input signal, if the output signal does not change, change the input signal. However, no meaningful verification result is obtained.

[0007]

As described above, in order to perform efficient verification, it is necessary to create an analysis waveform satisfying the above two conditions as much as possible. However, conventionally, such an analysis waveform has been created by trial and error. Such a trial-and-error creation method has no problem in the case of a small-scale logic circuit, but in the case of a large-scale logic circuit, the work load increases and it is not efficient.
When the number of bits of the input signal of the logic circuit (that is, the number of input terminals of the logic circuit) is m, the input signal pattern is 2 ^m.
The number of input signal patterns increases exponentially as the number of m increases. As described above, when the input signal pattern has a huge variation, the conventional method by trial and error requires a great deal of time and labor to create the optimum analysis waveform.

Therefore, an object of the present invention is to provide a method for efficiently generating an analysis waveform in a combinational logic circuit.

[0009]

[Means for Solving the Problems]

(1) A first aspect of the present invention is a method of generating an analysis waveform composed of an input signal waveform and an output signal waveform in a combinational logic circuit formed by combining a plurality of logic gates. The first step of creating a truth table showing the correspondence between the signal pattern and the output signal pattern, and one input signal pattern corresponding to one node, and a plurality of input signal patterns in the truth table to a plurality of nodes , The Hamming distance between them is 1, and the output signal patterns associated with each other in the truth table are different, between a pair of nodes satisfying the two conditions, a transition path from one to the other and another Define a pair of transition paths that have a direction consisting of a transition path from one to the other, and construct a group consisting of a group of nodes connected to each other by these transition paths. The second stage of formation, the third stage of finding a round route that passes through all the nodes that make up the group while following all defined transition paths in the forward direction, and the order of the nodes along this round route. A fourth step of generating an input signal waveform by transitioning the input signal pattern and generating an output signal waveform corresponding to the generated input signal waveform based on the truth table. is there.

(2) The second aspect of the present invention is the above-mentioned first aspect.
In the waveform generating method for analysis according to the above aspect, when there is no unregistered transition path from the processing target node to the adjacent node in the third step of obtaining a round path, this processing is immediately completed, and the processing target node is connected to the adjacent node. If there is an unregistered transition path that goes to a node, register this unregistered transition path, and if the adjacent node has never been the processing target in the past (a), (b)
After executing the above two tasks, register the transition path that returns from the adjacent node to the processing target node, and if the adjacent node has been the processing target in the past, execute the following two tasks (a) and (b) The process of registering a transition path that returns from the adjacent node to the processing target node without doing it is performed recursively for all nodes starting from any node, and the registered transition paths are combined in the registration order to obtain a roundabout route. It was done like this. (a) Work of deleting unregistered transition path from adjacent node to processing target node (b) Work of recursively executing this processing with the adjacent node as a new processing target (3) Third aspect of the present invention In the above-described analysis waveform generation method according to the first or second aspect, when a plurality of groups independent of each other are formed in the second step, the third step is executed for each individual group. By determining a loop route for each and defining a transition path between groups that connects a specific one node in one group and a specific one node in another group to each other, each group forms a line in a predetermined order. Are connected to each other, and a general loop path that passes through all nodes belonging to all groups is obtained. In the fourth stage, the input signal pattern is changed in the order of the nodes along the general loop path. wave Generates, on the basis of the truth table is the generated input signal waveform that so as to generate an output signal waveforms corresponding.

(4) The fourth aspect of the present invention is the above-mentioned third aspect.
In the analysis waveform generating method according to the aspect (1), an arbitrary group is selected when performing the processing for obtaining the general loop route, and from among the nodes belonging to this selected group, the other is selected with the smallest Hamming distance. The smallest Hamming distance of the nodes that belong to the group and that can be connected by the transition path between groups is determined, and of the pair of nodes that constitute the end points of one transition path between groups or multiple transition paths between groups The process of determining the nodes that can be connected to another unconnected group with a new inter-group transition path and connecting this new inter-group transition path to one end point is the inter-group transition between all groups. It is repeatedly executed until it is connected by a road, and all the loop routes and all the inter-group transition routes form a general loop route. .

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on an embodiment shown in the drawings.

§1. General logic circuit and analysis waveform
Relationship Here, for convenience of description, consider a logic circuit as shown in FIG. 1 (from a practical point of view, the logical operation of this circuit is not necessarily meaningful, but the description of the present invention is easy. In order to do so, the following explanation will be given here by taking this logic circuit as an example). This logic circuit is composed of four logic gates of a three-input AND gate 1, a two-input Ex-OR gate 2, a two-input OR gate 3 and a two-input OR gate 4, and receives an input signal ABC of 3 bits. ,
It has a function of outputting an output signal Q of 1 bit.
The truth table of this logic circuit is shown in FIG. This truth table shows output signal patterns obtained corresponding to each of the eight input signal patterns ~. For example, the input signal pattern is a 3-bit pattern "000", and a 1-bit output signal pattern "0" is obtained for this input signal pattern. Such a truth table can be obtained by following the logical operation of each logic gate when each bit is given for each input signal pattern.

Now, when such a logic circuit is designed, an analysis for verifying its logic operation is required. This analysis is usually performed by logic simulation using an analysis waveform as shown in FIG. The analysis waveform shown in FIG. 3 is composed of input signal waveforms A, B, C and an output signal waveform Q. When the input signal waveforms A, B, C are given to the logic circuit shown in FIG. It shows that the output of the signal waveform Q is expected. Of course, in an actual logic circuit, transistor elements, parasitic capacitance elements,
Due to the influence of the parasitic resistance element and the like, the waveform of the input signal may be distorted or delayed during the propagation, so that the results shown in the analysis waveform cannot be obtained. This analysis waveform only describes the operation of this circuit at the logic level. Therefore, the output signal waveform Q is uniquely determined based on the truth table shown in FIG.
The pattern numbers shown in the lower column of FIG. 3 correspond to the numbers of the input patterns shown in this truth table.

The analysis of the logic operation using the logic simulator shows that the output signal waveform Q as expected can be obtained when the input signal waveforms A, B and C shown in FIG. 3 are applied to the circuit shown in FIG. It is done by checking. In order to efficiently perform such an analysis, it is necessary to use an analysis waveform that satisfies the following two conditions, as described above. That is, the first condition is that the input signal waveform changes bit by bit, and the second condition is that the output signal must be changed by the change of the input signal. is there. The analysis waveform illustrated in FIG. 3 is a waveform that satisfies both of these two conditions.

For example, when examining the first condition, only the input signal C changes to “0 → 1” at the time of changing the pattern →, and at the time of changing to the subsequent pattern → the input signal C. Only B changes to "0 → 1", and only the input signal A changes to "0 → 1" at the time of changing to the next pattern →. As described above, the 3-bit input signals A, B, and C are constantly changing by 1 bit, and 2 bits or more do not change at the same timing. In order to perform verification by simulation, it is necessary to identify which input bit has caused the change in the output signal, so that the input signal waveform is changed bit by bit in this way. The first condition is important.

The analysis waveform illustrated in FIG. 3 also satisfies the second condition. That is, focusing on the output signal waveform Q, “0 →
1 "or" 1 → 0 ", and the output signal is always changed by the change of the input signal. The purpose of verification by logic simulation is to check whether or not the output signal is logically correct by changing the input signal. If the input signal is not changed on the premise of, the meaningful verification result cannot be obtained. In the logic circuit illustrated in FIG. 1, since the output signal waveform is composed only of the waveform of the 1-bit output signal Q, the output signal Q is inevitably "0 → 1 → 0 → 1 → 0 ... However, in the actual circuit, it is common to obtain an output signal composed of a larger number of bits. In this case, at least the output signal is changed due to the change of the input signal. It suffices if any one of these changes.

As described above, in order to perform efficient verification, it is necessary to create an analysis waveform satisfying the above two conditions as much as possible. However, in the past, since such an analysis waveform was created by trial and error, there is a problem that the work load increases exponentially as the scale of the logic circuit increases. Is. A logic circuit having a complicated function currently in practical use does not have a simple structure as shown in FIG. 1, but is composed of a huge number of logic gates, and an input signal pattern becomes a huge number. Regarding such a large-scale logic circuit, the above 2
In order to generate an analysis waveform that satisfies the conditions, some useful methods have been proposed in the past, but all of them have a heavy calculation load and cannot obtain a solution within a finite time. There are cases. The present invention proposes a new method for solving such a problem,
The solution will always be obtained within a finite time.

§2. Basic Principle of the Present Invention In the method according to the present invention, one input signal pattern is represented as one node, and a change in the input signal pattern is represented as a directional transition path connecting these nodes. For example, the analysis waveform shown in FIG. 3 is represented by the transition diagram between nodes as shown in FIG. In this transition diagram, each ellipse represents each node, and each arrow represents a directional transition path. Further, the 3-bit numerical value described in each node indicates the logical value of the 3-bit input signals A, B, and C, and corresponds to any of eight input signal patterns ~. For example,
The upper left node "000" in FIG. 4 corresponds to the input signal pattern, the right node "001" corresponds to the input signal pattern, and the next node "011" corresponds to the input signal pattern. Also, a transition path is drawn from the last node "100" shown in the lower right to the first node "000" shown in the upper left, and all the nodes are connected in a loop. It shows that a periodic analysis waveform can be obtained.

As described above, the transition diagram between nodes shown in FIG. 4 is equivalent to the input signal waveforms A, B and C. Moreover,
When the input signal waveforms A, B, and C are obtained, the output signal waveform Q can be uniquely obtained by referring to the truth table shown in FIG. 2, so that the transition diagram between nodes shown in FIG. 4 is eventually obtained. Therefore, the analysis waveform shown in FIG. 3 can be uniquely generated. The basic idea of the present invention is to generate an analysis waveform based on such a transition diagram between nodes.

FIG. 5 is a flowchart showing the basic procedure of the analysis waveform generating method according to the present invention. The procedure of the present invention will be described in detail below with reference to this flowchart. First, in step S1, a truth table showing the correspondence between the input signal pattern and the output signal pattern of the target logic circuit is created.
For example, in the case of the logic circuit shown in FIG. 1, a truth table as shown in FIG. 2 is created. Since various methods are already known as methods for creating such a truth table, description thereof will be omitted here.

In the subsequent step S2, each input signal pattern is made to correspond to one node and a transition path is defined between each node to form a group of one group of nodes. Specifically, eight input signal patterns in the truth table of FIG.
Are expressed as nodes, and a pair of transition paths are defined between the nodes. However, the transition path is defined only between nodes that satisfy the following two conditions. That is, the first condition is that the mutual Hamming distance is 1, and the second condition is that the output signal patterns associated with each other in the truth table are different from each other. Here, the “Hamming distance” is an index indicating how many bits have different logical values in two bit patterns. For example, considering the Hamming distances for eight types of input signal patterns ~ shown in the truth table of FIG. 2, the Hamming distance between patterns is 1 because only the input signal C differs, and The Hamming distance to the pattern is 2 because the input signals B and C are different, and the Hamming distance to the pattern is 3 because all the input signals are different.

When a pair of nodes satisfying the above two conditions is found, a bidirectional transition path (a directivity consisting of a transition path from one to the other and a transition path from the other to the one is located between the nodes. A pair of transition paths with is defined. Then, a group consisting of a group of nodes connected to each other by these transition paths is formed. A specific method of forming a group by such a method is shown in FIGS. 6 to 8.

First, as shown in FIG. 6, attention is paid to the leading node "000" of the truth table. Then, this node "00
For "0", all the nodes with a Hamming distance of 1 are listed. A node having a Hamming distance of 1 for a specific node can be easily obtained by inverting each bit of the original node. For example, the node "0
For "00", the first bit, the second bit, and the third bit are inverted to obtain the node "100",
The node “010” and the node “001” are obtained. In this way, when the nodes having the Hamming distance of 1 are enumerated, it is subsequently determined whether or not the output signal pattern for these enumerated nodes is different from the output signal pattern for the original node. In the above example, the value of the output signal Q corresponding to the original node "000" (input signal pattern) is "0" as shown in the truth table of FIG.
The value of the output signal Q corresponding to the enumerated node “100” (input signal pattern), node “010” (input signal pattern), and node “001” (input signal pattern) is the truth value of FIG. As shown in the table, all are "1". Therefore, with respect to the original node “000”, the listed nodes “100”, “010”, “00” are listed.
“1” all satisfy the above-mentioned two conditions.

Therefore, as shown in FIG. 7, these three nodes “100”, “010”, and “001” are arranged at positions adjacent to the original node “000”, and a pair of nodes is provided between the nodes. The transition path (arrow in the figure) of is defined. Thus,
Focusing on one node “000”, if several adjacent nodes “100”, “010”, “001” are found,
Then, the same processing is performed on the remaining unfocused nodes. For example, if the node “001” is set as a new node of interest, a new node “0” other than the node “000” is set as a node satisfying the above two conditions with respect to this node “001”.
11 ”is found. Further, if this node "011" is set as a new node of interest, the above-mentioned 2
In addition to the node "001", a new node "111" and an existing node "010" are found as the nodes satisfying the condition. In this way, if a node satisfying the above-mentioned two conditions is found for each node and a transition path indicated by a pair of arrows is defined between both nodes, the final result is shown in FIG. Thus, a group consisting of a group of nodes connected to each other by a transition path is formed.

Actually, the transition diagram between nodes shown in FIG. 4 is nothing but the transition between the six nodes shown in FIG. 8 in a predetermined order. That is, all transition paths (arrows) shown in FIG. 8 are forwarded (directions indicated by arrows).
If it is possible to find a roundabout route that passes through all the nodes in this group while following the above, the roundabout route becomes the one shown in the internode transition diagram of FIG. The process of step S3 in the flowchart of FIG. 5 is a process for obtaining such a roundabout route. In this way, when the roundabout route is obtained, in step S4, the nodes along the roundabout route are arranged in order.
The input signal waveform is generated by transitioning the input signal pattern, and the processing to generate the output signal waveform corresponding to the generated input signal waveform is executed based on the truth table, and the target analysis waveform is obtained. become. In other words, the analysis waveform shown in FIG. 3 is generated based on the internode transition diagram shown in FIG. 4 and the truth table shown in FIG.

§3. Specific Method for Obtaining Circular Route The basic principle of the present invention has been described above based on the flowchart of FIG. 5, but here, step S3 in this flowchart is described.
A specific method of the processing of (1), that is, the processing of obtaining a roundabout path through all the nodes in the group while tracing all the transition paths defined in step S2 in the forward direction will be described. This one-round path can be obtained by a method of connecting each node by, so to speak, “one stroke writing”. For example, in the example shown in FIG. 8, six nodes are connected by arrows (transition paths), but the number of arrows entering and leaving each node is an even number. As described above, since the group forming process in step S2 is performed by defining a pair of transition paths having different directions between adjacent nodes, the number of arrows entering and leaving each node is always an even number. Become. According to Euler's theorem regarding "one-stroke writing", in such a case, there is always a "one-stroke writing" path starting from an arbitrary node, and the starting point and the end point are the same node. Therefore, theoretically, a roundabout route is always obtained for the group configured by the processing in step S2 described above.

Here, an example of a specific method for obtaining such a roundabout route will be described with reference to the flowchart of FIG. In the method illustrated here, it is necessary to repeatedly execute a predetermined process recursively. The flowchart shown in FIG. 9 shows a procedure for one recursive process that is repeatedly executed as described above, and describes the process to be executed for an arbitrary process target node (N). . here,
In this way, the processing executed for an arbitrary processing target node (N) will be referred to as processing (N).

First, in step S31, it is determined whether or not there is an unregistered transition path toward the adjacent node (N + 1). For example, when the node “000” shown in FIG. 8 is the processing target node (N), the nodes “100”, “010”,
Any one of "001" is an adjacent node (N +
The arrow corresponding to 1) and pointing to these adjacent nodes is an unregistered transition path. It should be noted that the term "unregistered" here indicates a state in which registration processing, which will be described later, is not performed, and all transition paths are unregistered transition paths at the initial stage. If it is determined in step S31 that there is no unregistered transition path toward the adjacent node (N + 1), the process (N) for this process target node (N) ends immediately.

On the other hand, when it is determined that there is an unregistered transition path toward the adjacent node (N + 1), this unregistered transition path is registered in step S32. Then, in the following step S33, it is determined whether or not the adjacent node (N + 1) has been a processing target in the past. In other words, processing (N + 1) in which the adjacent node (N + 1) is set as the processing target node in the past is performed, and it is determined whether or not the recursive processing is currently being performed. If a negative determination is made here, the work (a) is executed in the subsequent step S34, and further the work (b) is executed in step S35. The work (a) is a work for erasing an unregistered transition path from the adjacent node (N + 1) to the processing target node (N). If explained in the figure, from the adjacent node (N + 1) to the processing target node (N). The arrow pointed to will be erased. The subsequent work (b) is a work for executing the recursive processing (N + 1) with the adjacent node (N + 1) as a new processing target. This recursive processing (N + 1) is exactly the same as the entire processing procedure shown in FIG. 9 except that the processing target node is not the node (N) but the node (N + 1). That is,
In the work (b) of step S35, the whole process (N) shown in FIG. 9 is recursively called.

In this way, when the recursive processing in step S35 is completed or the affirmative judgment is made in step S33, the transition path from the adjacent node (N + 1) to the processing target node (N) is determined in step S36. Once registered, the process returns to the first step S31. When step S36 is executed through steps S34 and S35, the “unregistered transition path from the adjacent node (N + 1) to the processing target node (N)” that was once deleted in step S34 is restored in step S36. You will be registered later. in this way,
The reason why the data is deleted once in step S34 and then restored and registered in step S36 is as follows.
In the recursive processing of step S35, the “unregistered transition path from the adjacent node (N + 1) to the processing target node (N)” is made invisible, and until the necessary processing for the node (N + 1) is completed, This is a measure to prevent returning to N).

The processing shown in FIG. 9 is performed recursively for all nodes starting from an arbitrary node, and the registered transition paths are combined in the order of registration, so that the target roundabout path can be obtained. Hereinafter, as an example thereof, a case where the processing of FIG. 9 is applied to the six nodes shown in FIG. 8 will be shown.

Any of the six nodes may be selected as the first processing target node (N). Here, an example will be described in which the node “000” is the first processing target node (N). First, in step S31, it is determined whether or not there is an unregistered transition path toward the adjacent node (N + 1).
As shown in FIG. 10, there are three transition paths Ta, Tb, and Tc as such unregistered transition paths. In this way, when there are a plurality of corresponding transition paths, any one of them may be selected. Here, the following description will be continued assuming that the transition path Tc is selected. That is, the node “000” corresponds to the processing target node (N),
The node “001” corresponds to the adjacent node (N + 1).

In the subsequent step S32, registration is performed for this unregistered transition path Tc. Here, it is assumed that this transition path Tc is registered as the transition path T1. FIG.
A transition path T1 indicated by a thick arrow at 0 indicates a transition path registered in this way. Hereinafter, for convenience of explanation, unregistered transition paths are indicated by thin arrows, registered transition paths are indicated by thick arrows, and registered transition paths are denoted by T1, T2, T3, ... In the order of registration. I will call it with. Also, regarding the nodes, the nodes that have been the processing target in FIG. 9 are indicated by thick ellipses.

In the next step S33, the adjacent node (N +
It is determined whether 1) has been processed in the past. The adjacent node (N + 1) at the present time is the node “0” shown in FIG.
01 ”, and this node has never been a processing target in the past, as indicated by a thin line ellipse. Therefore, a negative determination is made in step S33, and the work (a) in step S34 is performed. That is, the unregistered transition path from the adjacent node (N + 1) to the processing target node (N) is deleted. After all, as shown in FIG. 11, the processing target node “000” is changed from the adjacent node “001”.
The thin arrow pointing to will be erased.

In the following step S35, the adjacent node (N +
A recursive process (N + 1) with 1) as a new process target is executed. That is, this time, the entire processing shown in FIG. 9 is recursively called with the node “001” as the processing target node. In FIG. 11, the node “001” is indicated by a bold ellipse, which indicates that the process for the node “001” has been executed. Of course, this recursively called process is the work (b) of step S35 in the process for which the node "000" is the processing target.
However, after the recursive call processing is completed, the process proceeds to step S36. By the way, in the process of step S36, since the transition path from the adjacent node (N + 1) to the process target node (N) is registered,
The transition path deleted in FIG. 11 is restored and registered (process of FIG. 23 described later).

Now, let us consider the processing work to be performed assuming that the processing shown in FIG. 9 is recursively called with the node "001" as a new processing target node. First, in step S31, the adjacent node (N +
It is determined whether or not there is an unregistered transition path toward 1). FIG.
As shown in, the only unregistered transition path from the node "001" to the adjacent node is the transition path Td. Therefore, in step S32, this transition path Td is registered as the transition path T2. FIG. 12 shows the state at this time.
In a succeeding step S33, it is determined whether or not the adjacent node "011" has been a processing target in the past. As shown by the thin line ellipse in FIG. 12, since the node “011” has not yet been processed, a negative determination is made in step S33, and the operation in step S34 is performed.
(a) is implemented. That is, as shown in FIG. 13, the unregistered transition path from the adjacent node “011” to the processing target node “001” is deleted. Then, in the following step S35, recursive processing is performed with the adjacent node "011" as a new processing target.

In this way, when the process in which the node "011" is the new processing target node is recursively called, first, in step S31, it is determined whether or not there is an unregistered transition path from the node "011" to the adjacent node. It As shown in FIG. 13, there are a transition path Te and a transition path Tf in the unregistered transition path from the node “011” to the adjacent node. It does not matter which one is selected, but here, the description will be continued assuming that the transition path Te is selected and the node “111” is set as the adjacent node. In step S32, the transition path Te is the transition path T3.
Will be registered as. FIG. 14 shows the state at this time. In the following step S33, the adjacent node "111"
Is determined to be the processing target in the past. FIG.
As indicated by the thin line ellipse, the node "111" has not yet been processed, so a negative determination is made in step S33, and the operation (a) in step S34 is performed. That is, as shown in FIG. 15, the unregistered transition path from the adjacent node “111” to the processing target node “011” is deleted. And
In the following step S35, recursive processing is performed with the adjacent node "111" as a new processing target.

When the process with the node "111" as a new target node is recursively called, first, step S3 is performed.
In 1, it is determined whether or not there is an unregistered transition path from the node “111” to the adjacent node. As shown in FIG. 15, there is no unregistered transition path from the node “111” to the adjacent node. Therefore, the process of setting the node “111” as the process target node immediately ends. This completed process corresponds to the end of the work (b) of step S35 in the process in which the node “011” in the previous stage is set as the process target node.
Step S36 will be executed. That is, the transition path from the adjacent node “111” to the processing target node “011” is registered as the transition path T4 (which has been erased once but will be re-registered). FIG. 16 shows the state at this time.

Thus, when step S36 is completed,
It will return to step S31 again. That is, first, in step S31, it is determined whether or not there is an unregistered transition path from the node "011" to the adjacent node. FIG.
As shown in, the only unregistered transition path from the node "011" to the adjacent node is the transition path Tf. Therefore, in step S32, the transition path Tf is registered as the transition path T5. FIG. 17 shows the state at this time.
In a succeeding step S33, it is determined whether or not the adjacent node "010" has been a processing target in the past. As shown by the thin line ellipse in FIG. 17, since the node “010” has not yet been processed, a negative determination is made in step S33, and the operation in step S34 is performed.
(a) is implemented. That is, as shown in FIG. 18, the unregistered transition path from the adjacent node “010” to the processing target node “011” is deleted. Then, in the following step S35, recursive processing is performed with the adjacent node "010" as a new processing target.

When the process with the node "010" as a new target node is recursively called, first, step S3 is executed.
In 1, it is determined whether or not there is an unregistered transition path from the node “010” to the adjacent node. As shown in FIG. 18, the unregistered transition path from the node “010” to the adjacent node is only the transition path Tg. Therefore, in step S32,
This transition path Tg will be registered as the transition path T6. FIG. 19 shows the state at this time. Subsequent step S3
In 3, it is determined whether or not the adjacent node “000” has been processed in the past. As shown by the thick line ellipse in FIG. 19, the node “000” has already been the processing target (to be precise, the current processing of the node “010” is the processing target node is This is equivalent to multiple nested recursive call processing in the processing in which the node "000" is the processing target node). Therefore, step S33
In step S, a positive determination is made and immediately, step S
I will proceed to 36. In step S36, the transition path Th from the adjacent node “000” to the processing target node “010” is registered as the transition path T7. FIG. 20 shows the state at this time.

Thus, when step S36 is completed,
It will return to step S31 again. That is, first, in step S31, it is determined whether or not there is an unregistered transition path from the node "010" to the adjacent node. FIG.
As shown in, there is no unregistered transition path from the node “010” to the adjacent node. Therefore, the process of setting the node "010" as the process target node is immediately terminated. This finished process corresponds to the end of the work (b) of step S35 in the process in which the node "011" in the previous stage is the process target node, so that step S36 is subsequently executed. That is, the transition path extending from the adjacent node “010” to the processing target node “011” is registered as the transition path T8 (although it was once deleted, it will be re-registered). FIG. 21 shows the state at this time.

The node to be processed at present is the node "01".
1 ”, and the process returns to step S31 again. Then, in step S31, the node "01
It is determined whether or not there is an unregistered transition path from "1" to the adjacent node. As shown in FIG. 21, there is no unregistered transition path from the node “011” to the adjacent node. Therefore, this node "0
The process with “11” as the processing target node ends immediately. This completed process corresponds to the end of the work (b) of step S35 in the process in which the node "001" of the previous stage is the process target node, and therefore step S36 is subsequently executed. That is, the transition path from the adjacent node “011” to the processing target node “001” is registered as the transition path T9 (it has been deleted once but will be re-registered). FIG. 22 shows the state at this time.

Thus, the processing target node is the node "001".
When the process returns to step S31, the process returns to step S31. Then, in step S31, it is determined whether or not there is an unregistered transition path from the node "001" to the adjacent node. FIG.
As shown in, there is no unregistered transition path from the node "001" to the adjacent node. Therefore, the processing in which this node "001" is the processing target node is immediately terminated. This completed process corresponds to the end of the work (b) of step S35 in the process in which the node "000" at the first stage is the process target node, so that step S36 is subsequently executed. That is, the transition path from the adjacent node “001” to the processing target node “000” is registered as the transition path T10 (which was once deleted but will be re-registered). FIG. 23 shows the state at this time.

In the state shown in FIG. 23, the processing has returned to the processing for the first node "000" again. Then, the processing from step S31 is repeatedly executed, and it is determined whether or not there is an unregistered transition path from the node "000" to the adjacent node. As shown in FIG. 23, the transition path Ti still remains as an unregistered transition path from the node “000” to the adjacent node. Therefore, this transition path Ti is registered as the transition path T11. FIG.
4 shows the state at this time. In the following step S33,
It is determined whether or not the adjacent node “100” has been a processing target in the past. As shown by the thin line ellipse in FIG. 24,
Since the node “100” has never been the processing target, a negative determination is made in step S33,
Work (a) in step S34 is performed. That is, as shown in FIG. 25, the unregistered transition path from the adjacent node “100” to the processing target node “000” is deleted. Then, in the subsequent step S35, recursive processing is performed with the adjacent node "100" as a new processing target.

When the process with the node "100" as a new target node is recursively called, first, step S3 is performed.
In 1, it is determined whether or not there is an unregistered transition path from the node “100” to the adjacent node. As shown in FIG. 25, there is no unregistered transition path from the node “100” to the adjacent node. Therefore, the process of setting the node "100" as the process target node immediately ends. This completed process corresponds to the end of the work (b) of step S35 in the process in which the node “000” in the previous stage is set as the process target node.
Step S36 will be executed. That is, the transition path from the adjacent node “100” to the processing target node “000” is registered as the transition path T12 (it has been deleted once but will be revived and registered). FIG. 26 shows the state at this time.

Thus, the process again starts with the first node "00".
The process returns to step S31 for "0". However, as shown in FIG. 26, there is no longer an unregistered transition path from the node “000” to the adjacent node.
Therefore, the process of setting the node “000” as the process target node ends. By the above work, all the recursive processing executed by selecting the node "000" as the first processing target is completed. That is, if the registered transition paths T1 to T12 indicated by the bold arrows in FIG. 26 are traced in the order of registration, a roundabout path passing through all the nodes can be obtained. Is described, the transition diagram between nodes shown in FIG. 4 can be obtained.

§4. When a plurality of groups are configured The basic principle of the present invention is that the truth table (FIG. 2) is created in step S1 and the transition path is created in step S2 as already described with reference to the flowchart of FIG. A group (FIG. 8) composed of a group of nodes connected by is formed, and in step S3, a loop route (FIG. 26) that follows all transition paths is obtained, and in step S4, based on this loop route and the truth table. The point is to obtain the analysis waveform by the procedure of generating the analysis waveform (FIG. 3) by using the above procedure. However, up to now, the description has been given by using the example in which only a single group is formed by the process of step S2, but in the case of a complicated logic circuit actually used, the process of step S2 is performed. , Generally, a plurality of groups are configured. Here, the handling when a plurality of groups are thus configured will be described.

In the above description, the simple logic circuit shown in FIG. 1 is taken as an example to describe that the group shown in FIG. 8 is formed. However, the nodes shown in FIG. 8 do not correspond to all the input signal patterns shown in the truth table of FIG. That is, among the eight types of input signal patterns 1 to 3 shown in the truth table of FIG. 2, the input signal pattern (node “1
01 ") and input signal pattern (node" 110 ")
(Corresponding to) is not shown in FIG. This is because these two nodes do not have nodes that should be paired so as to satisfy the two conditions shown in step S2. For example, with respect to the node “101”, the nodes whose Hamming distance is 1 are the node “001” and the node “1”.
11 ”and the node“ 100 ”exist, but the logical value of the output signal Q is the same as“ 1 ”, and thus the second condition“ the output signal patterns are different from each other ”is not satisfied. The same applies to the node “110”. Therefore, if these two nodes are intentionally shown in the figure, they will be represented as isolated nodes as shown in FIG.

In this way, if isolated nodes are treated as if they constitute one independent group, FIG.
As indicated by a broken line in FIG. 7, 3 of groups G1, G2, and G3
One group will be formed. However, normally, even if such an isolated node is ignored and an analysis waveform is generated, no significant trouble occurs. Actually, the analysis waveform shown in FIG. 3 is a waveform in which the isolated nodes “101” and “110” are ignored.
The pattern does not appear. If necessary, after generating the waveform shown in FIG. 3, the pattern,
Can be inserted at an appropriate place. Of course, if such an insertion is performed, the condition that the input signal always changes by one bit and the output signal always changes will not be completely satisfied.

In this way, when a completely isolated node occurs, it is sufficient to ignore it and generate an analysis waveform or add it manually later, as described above. However, many practical logic circuits (usually much more complex circuits than the logic circuit shown in FIG. 1)
In this case, the process in step S2 generally forms a plurality of substantial groups, each of which includes a plurality of nodes. In this way, when a plurality of substantial groups are formed in step S2, the process of step S3 may be performed for each individual group, and a loop route may be obtained for each individual group. FIG. 28 shows four groups G1 to G1 in this manner.
FIG. 11 is a conceptual diagram showing an example in which a roundabout route is obtained for G4. Here, the points labeled with a to z are
Each node is shown, and a circle connecting these nodes shows a loop route for each group. In other words, in FIG. 28, the portions surrounded by broken lines correspond to the inter-node transition diagram shown in FIG. 4, respectively. Therefore, for example, the nodes a and b in the group G1 satisfy the two conditions that the Hamming distance is 1 from each other and the output signal patterns are different from each other. Any connected node is
This means that these two conditions are satisfied.

However, the four independent
Generating an analysis waveform based on each of the two groups G1 to G4 is not preferable because four sets of discrete waveforms are generated. Therefore, in order to finally generate one aggregated analysis waveform, as shown in FIG. 29, the inter-group transition paths TT1, TT2, T for connecting each group.
T3 is defined and all groups are connected to each other to form an integrated circuit route. In the example shown in FIG. 29, an inter-group transition path TT1 is defined between the nodes d and n, an inter-group transition path TT2 is defined between the nodes n and z, and an inter-group transition path TT2 is defined between the nodes z and k. By defining the inter-group transition path TT3,
As a whole, one integrated circuit route is constructed. That is, the nodes d-e-f-g-
h-a-b-c-d = n-o-p-q-r-s-n = z
-T-u-v-w-x-y-z = k-j-i-m-l-
k will be arranged in this order (here, − represents a transition path within a group, and = represents an inter-group transition path). Furthermore, if an inter-group transition path TT4 is defined between the nodes k and d, it is possible to form an integrated loop path which is closed in a loop shape as a whole.

If such an integrated circuit route can be formed,
By transitioning the input signal pattern in the order of the nodes along the integrated circuit route, the target input signal waveform can be generated, and the output signal waveform corresponding to this input signal waveform is generated based on the truth table. Can be generated.

FIG. 30 is a flow chart showing the processing procedure of the present invention when a plurality of groups are thus formed. The difference between the flow chart shown in FIG. 5 and the flow chart shown in FIG. 30 is that, in the latter case, a plurality of groups are finally formed in step S2, and each group is separated and independent in step S3. The point that a roundabout route is obtained, and the point that step S5 that configures a general roundabout route by connecting inter-group transition paths connecting each group is inserted between steps S3 and S4. This is the point where the input signal waveform is generated based on the integrated loop path.

§5. A concrete way to form an integrated circuit
Method Here, a specific method of the process of step S5 in the flowchart of FIG. 30, that is, the process of obtaining the integrated circuit route will be described. As shown in FIG. 29, in order to form a general loop route when four groups G1 to G4 are configured as in the example shown in FIG. 28, an inter-group transition path for connecting the groups is used. It is sufficient to define TT1, TT2 and TT3. In other words, the process of obtaining the integrated loop route in step S5 is substantially a process of defining an inter-group transition route.

The inter-group transition path is a transition path that connects the nodes in one group and the nodes in the other group, so if it is a transition path that connects randomly selected nodes, Even such a transition path can temporarily function as an inter-group transition path. However, in order to obtain the finally generated analysis waveform that is optimized as much as possible, it is preferable to adopt a transition path that connects nodes with a Hamming distance as small as possible as an inter-group transition path. As described above, on the integrated loop route formed in FIG. 29,
Node d-e-f-g-h-a-b-c-d = n-o-p
-Q-r-s-n = z-t-u-v-w-x-y-z =
k-j-i-m-l-k are arranged in this order, where-is a transition path within a group and a transition path between nodes with a Hamming distance of 1. Therefore, it is preferable that the inter-group transition path indicated by = is also a transition path between nodes of the Hamming distance 1 if possible. However, in reality, the Hamming distance 1
Since it is difficult to set, it is realistic to select an inter-group transition path with a Hamming distance as small as possible.

An example of such a method of selecting an inter-group transition path will be described with reference to the flowchart of FIG. In the strict sense, the inter-group transition path selected by the method shown here may not necessarily be the most ideal combination with the smallest Hamming distance, but according to this method, it is relatively simple. It is possible to obtain a combination that is close to the ideal with a computational burden.

First, in step S41, one arbitrary group is selected. For example, assume that the group G1 is selected in the example shown in FIG. Continue,
In step S42, one node that can be connected to another group with the smallest Hamming distance is determined from the nodes in the selected group, and the determined node and the node of the partner are determined by the inter-group transition path. Connecting. Specifically, for example, first, an initial value 1 is set as the set value of the Hamming distance, and the Hamming distance between the node a in the group G1 and the individual nodes of the other groups is checked, and the set value is equal to 1. Search for something or not. If no such other group of nodes is found for node a, then a similar search is made for node b. In this way, the same search is performed for the nodes c, d, e, f, g, and h, and if a combination of nodes satisfying the condition is found, the search is interrupted at that point, and between the pair of nodes. The transition path between groups is defined in. If the corresponding node pair is not found even after the search for the node h, the setting value of the Hamming distance is increased to 2 and the same process is performed. In this way, if the set value is sequentially incremented by 1 and the same processing is performed, the node pairs that meet the conditions will be found.

In order to search for another node having a Hamming distance of H with respect to a certain node A, all bit patterns formed by inverting H bits of the bit pattern of the node A are generated. , It suffices to find a node having the same bit pattern as the generated bit pattern.

Here, for example, the set value is 2, and
It is assumed that the node n of another group is found as a node satisfying the condition while executing the search for the node d. In this case, the Hamming distance between the node pair d-n is 2. Of course, there may be other node pairs having a Hamming distance of 2, but in this method, an inter-group transition path is defined between the first node pair dn found. Thus, the groups G1 and G3 are shown in FIG.
Are connected by the inter-group transition paths TT1 shown in FIG. 29 (the inter-group transition paths TT2 and TT3 shown in FIG. 29).
Is not yet defined at this stage).

Subsequently, in step S43, a process of inserting both nodes determined in step S42 into the end point list is performed. This end point list is a list showing a pair of nodes forming both end points of one inter-group transition path or a plurality of inter-group transition paths defined up to the present stage. In the case of the above example, both nodes d and n of one inter-group transition path TT1 defined up to the present stage are put in the end point list.

Next, in step S44, the processes of steps S45 and S46 are repeatedly executed until it is determined that all the groups are connected. That is, first, in step S45, a node that can be connected to another unconnected group with the smallest Hamming distance is determined from the nodes in the end point list, and the determined node and the node of the partner are determined by the inter-group transition path. Connecting. In this way, by connecting a new inter-group transition path, the end point is changed.
At, the end point list is updated.

The processes of steps S45 and S46 can be easily understood by referring to the actual example of FIG. Now, in step S42, the inter-group transition path TT1 is defined,
It is assumed that step S45 is executed through step S44 in the state where the nodes d and n are included in the end point list in step S43. In this case, from the nodes d and n in the end point list, one node that can be connected to another group with the smallest Hamming distance is determined, and the determined node and the node of the other party are new inter-group transition paths. Will be connected by. Specifically, again, the initial value 1 is set as the set value of the Hamming distance, and the Hamming distance between one node d in the end point list and the individual nodes of the other groups is checked, and it is set to 1 equal to the set value. Search whether there is something. If no such other group of nodes is found for node d, then a similar search is performed for the other node n in the endpoint list. If no such node of the other party is found with respect to the node n, this time, the set value of the Hamming distance is increased to 2 and the same process is performed. In this way, if the set value is sequentially incremented by 1 and the same processing is performed, the node pairs that meet the conditions will be found.

Here, for example, the set value is 3, and
It is assumed that the node z of another group is found as a node satisfying the condition while executing the search for the node n. In this case, the Hamming distance between the node pair nz is 3. In this way, a new inter-group transition path TT2 is defined between the node pair nz. in this way,
At the stage when the inter-group transition path TT2 is defined, the node n is no longer an end point, so the two inter-group transition paths (TT) defined up to the present stage are connected.
The pair of nodes d and z forming the end points of (1 + TT2) become members of the new end point list. Therefore, step S
At 46, the members of the new end point list are added to the nodes d, z.
The update process of rewriting is executed.

Next, it is assumed that step S45 is executed again through step S44. In this case, from the nodes d and z in the end point list, one node that can be connected to another group with the smallest Hamming distance is determined, and the determined node and the node of the other party are new transition paths between groups. Will be connected by. here,
For example, it is assumed that the set value is set to 2 and the node k of another group is found as a node satisfying the condition while executing the search for the node z. In this case, the Hamming distance between the node pair zk is 2. In this way, a new inter-group transition path TT3 is defined between the node pair zk. In this way, the inter-group transition path TT3
At the stage when is defined, the node z is no longer an end point, so a pair of nodes d, which form the end points of the three inter-group transition paths (TT1 + TT2 + TT3) defined up to the present stage, k becomes a member of the new endpoint list. Therefore, in step S46, an update process of rewriting the members of the new end point list to the nodes d and k is executed.

Here, the process returns to step S44 again, but at this time point, all the groups are already connected. Therefore, the processing shown in FIG. 31 ends here,
Finally, three inter-group transition paths TT1, TT2, TT3 as shown in FIG. 29 are obtained.

Finally, an example of the result of obtaining the integrated circuit route by the above method will be illustrated. For example, consider a case where three groups G1, G2, G3 as shown in FIG. 32 are formed. In this case, for example, as shown in FIG. 33, the node “0001” in the group G1 and the node “1111” in the group G2 are connected to each other through the inter-group transition path TT.
and the node "111" in this group G2.
It is assumed that "1" and the node "1100" in the group G3 are connected by the inter-group transition path TTb. When such random connection is performed, the Hamming distance of the inter-group transition path TTa becomes 3, and the Hamming distance of the inter-group transition path TTb becomes 2, so that the total Hamming distance of the inter-group transition path becomes 5. On the other hand, when the process based on the flowchart of FIG. 31 described above is performed to define the inter-group transition path, the result as shown in FIG. 34 is obtained. That is, the node “0000” in the group G1 and the node “0” in the group G3.
100 "is connected by the inter-group transition path TTc, and the node" 0100 "in the group G3 and the node" 0111 "in the group G2 are connected by the inter-group transition path TTd. In this case, the Hamming distance of the inter-group transition path TTc is 1 and the Hamming distance of the inter-group transition path TTd is 2, so the total Hamming distance of the inter-group transition path is 3, which is shorter than the example shown in FIG. .

In the above description, the case where each group has a plurality of nodes has been taken as an example.
, A group G having only isolated nodes
It is also possible to perform processing based on the flowchart of FIG. 31 for 2 and G3 as well to form an integrated circuit route including these isolated nodes.

[0069]

As described above, according to the analyzing waveform generating method of the present invention, it is possible to efficiently generate the analyzing waveform in the combinational logic circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of a simple logic circuit.

FIG. 2 is a diagram showing a truth table of the logic circuit shown in FIG.

FIG. 3 is a waveform chart showing an example of an analysis waveform used for analysis of the logic circuit shown in FIG.

FIG. 4 is a transition diagram between nodes corresponding to the analysis waveform shown in FIG.

FIG. 5 is a flowchart showing a basic procedure of an analysis waveform generating method according to the present invention.

6 is a diagram showing the state of the first stage of the process of step S2 in the flow chart shown in FIG. 5. FIG.

7 is a diagram showing a state of a second stage of the process of step S2 in the flowchart shown in FIG.

8 is a diagram showing a state of a third stage of the process of step S2 in the flowchart shown in FIG.

9 is a flowchart showing an example of a specific method for obtaining the one-round route of step S3 in the flowchart shown in FIG.

FIG. 10 is a diagram showing a state where step S32 shown in FIG. 9 is executed when a node “000” is set as a processing target node.

FIG. 11 is a diagram showing a state in which steps S34 and S35 shown in FIG. 9 are executed when the node “000” is set as a processing target node.

FIG. 12 is a diagram showing a state where step S32 shown in FIG. 9 is executed when the node “001” is set as a processing target node.

FIG. 13 is a diagram showing a state in which steps S34 and S35 shown in FIG. 9 are executed when the node “001” is set as a processing target node.

FIG. 14 is a diagram showing a state where step S32 shown in FIG. 9 is executed when the node “011” is set as a processing target node.

FIG. 15 is a diagram showing a state in which steps S34 and S35 shown in FIG. 9 are executed when the node “011” is set as a processing target node.

FIG. 16 is a diagram showing a state where step S36 shown in FIG. 9 is executed when the node “011” is the processing target node.

FIG. 17 is a diagram showing a state where step S32 shown in FIG. 9 is executed when the node “011” is set as a processing target node.

FIG. 18 is a diagram showing a state in which steps S34 and S35 shown in FIG. 9 are executed when the node “011” is set as a processing target node.

FIG. 19 is a diagram showing a state where step S32 shown in FIG. 9 is executed when the node “010” is set as a processing target node.

FIG. 20 is a diagram showing a state where step S36 shown in FIG. 9 is executed when the node “010” is set as a processing target node.

FIG. 21 is a diagram showing a state in which step S36 shown in FIG. 9 is executed when the node “011” is set as a processing target node.

FIG. 22 is a diagram showing a state where step S36 shown in FIG. 9 is executed when the node “001” is set as a processing target node.

FIG. 23 is a diagram showing a state where step S36 shown in FIG. 9 is executed when the node “000” is set as a processing target node.

FIG. 24 is a diagram showing a state where step S32 shown in FIG. 9 is executed when the node “000” is set as a processing target node.

25 is a diagram showing a state in which steps S34 and S35 shown in FIG. 9 are executed when the node “000” is set as a processing target node.

FIG. 26 is a diagram showing a state where step S36 shown in FIG. 9 is executed when the node “000” is set as a processing target node.

FIG. 27 is a diagram showing a group structure including isolated nodes.

FIG. 28 is a diagram showing a state in which a loop route is formed for each of a plurality of groups.

29 is a diagram showing a state in which inter-group transition paths TT1, TT2, TT3 are defined in order to connect the four groups shown in FIG.

FIG. 30 is a flowchart showing the basic procedure of the analysis waveform generating method according to the present invention when a plurality of groups are formed.

FIG. 31 is a flowchart showing an example of a specific method for obtaining an integrated loop route in step S5 in the flowchart shown in FIG. 30.

FIG. 32 is a diagram showing an example of three group configurations each including a plurality of nodes.

33 is a diagram showing an example of an inter-group transition path for connecting the three groups shown in FIG. 32.

FIG. 34 shows three groups shown in FIG.
6 is a diagram showing an example of an inter-group transition path defined by applying the method shown in the flowchart of FIG.

[Explanation of symbols]

 1 to 4 ... Logic gates A to C ... Input signals G1 to G4 ... Group Q ... Output signals T1 to T12 ... Registered transition path Ta to Ti ... Unregistered transition path TT1 to TT3 ... Inter-group transition path TTa to TTd ... Group Transition path a to z ... Node

Claims (4)

[Claims] 1. A method for generating an analysis waveform composed of an input signal waveform and an output signal waveform for a combinational logic circuit formed by combining a plurality of logic gates, wherein the logic circuit has an input signal pattern and an output signal. A first step of creating a truth table showing a correspondence relationship with a pattern, one input signal pattern is made to correspond to one node, and a plurality of input signal patterns in the truth table are expressed as a plurality of nodes, Between the pair of nodes satisfying the two conditions that the mutual Hamming distance is 1 and the output signal patterns associated in the truth table are different from each other, a transition path from one to the other and one from the other to the one Defining a pair of directional transition paths consisting of a transition path going to each other, and forming a group consisting of a group of nodes connected to each other by these transition paths A second step, a third step in which all defined transition paths are traced in the forward direction to obtain a round path that passes through all the nodes that make up the group, and the nodes along the round path are arranged in this order. A fourth step of generating an input signal waveform by transitioning the input signal pattern, and generating an output signal waveform corresponding to the generated input signal waveform based on the truth table. Waveform generation method for analysis in combinatorial logic circuit. 2. The method for generating a waveform for analysis according to claim 1, wherein in the third step of determining a loop path, if there is no unregistered transition path from the processing target node to the adjacent node, this processing is immediately completed. However, if there is an unregistered transition path from the processing target node to the adjacent node, this unregistered transition path is registered, and if the adjacent node has never been the processing target in the past, (a), ( After performing the two operations of b), register a transition path that returns from the adjacent node to the processing target node, and if the adjacent node has been a processing target in the past, the following (a) and (b) The process of registering a transition path that returns from the adjacent node to the processing target node without executing two tasks is performed recursively for all nodes starting from any node, and the registered transition paths are combined in the order of registration. So that a round trip route is obtained by A method for generating a waveform for analysis in a combinational logic circuit characterized in that, (a) work of erasing an unregistered transition path from the adjacent node to the processing target node, (b) the adjacent node as a new processing target Work for recursively executing the above processing. 3. The analysis waveform generating method according to claim 1, wherein when a plurality of groups independent of each other are formed in the second step, the third step is executed for each individual group. Each of the groups is determined in a predetermined order by defining a transition path between groups that connects one specific node in one group and one specific node in another group. In a fourth step, the input signal pattern is changed in the order of the nodes along the integrated loop route in the fourth step so that the integrated loop route passing through all the nodes belonging to all groups is obtained. Analysis in combinational logic circuit characterized by generating an input signal waveform and generating an output signal waveform corresponding to the generated input signal waveform based on a truth table Waveform generation method. 4. The method for generating a waveform for analysis according to claim 3, wherein when performing a process for obtaining a general loop route, one arbitrary group is selected, and from among the nodes belonging to the selected group, A node that belongs to another group with the smallest hamming distance and that can be connected by an inter-group transition path is determined, and a pair of nodes that configure both end points of one inter-group transition path or multiple inter-group transition paths. Among these, the process of connecting the node belonging to the other unconnected group and the new inter-group transition path with the smallest Hamming distance, and connecting this new inter-group transition path to one end point, Repeatedly executed until all groups are connected by an inter-group transition path, and all loop paths and all inter-group transition paths form a general loop path. A method of generating a waveform for analysis in a combinational logic circuit characterized by the above.