JPH09252057A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the integration degree of memory cells, without increasing the production process by forming first gate electrodes formed in parallel on a semiconductor substrate, interconnection breaking insulation films, and second gate electrodes self-aligned to the 1st electrodes. SOLUTION: First gate electrodes 5 are formed nearly in parallel on a semiconductor substrate 1 of a semiconductor device through a first insulation film 4, interconnection breaking insulation films 14, 15 are formed on desired regions as thick as the first electrode 5, and second gate electrodes 9 are formed self- alignedly in recesses defined by the first electrodes 5 and insulation films 14, 15. Since the electrodes 5 and 9 are formed at a pitch equal to that of the min. working method, and hence a high-density element is realizable to form a large-scale circuit and reduce the cost by reducing the chip size.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device using a large capacity memory cell circuit such as a mask programmable ROM and a manufacturing method thereof.

[0002]

2. Description of the Related Art Semiconductor memory devices using large-capacity memory cell circuits include DRAM, SRAM, EEPROM, mask ROM and the like. Among them, the mask ROM is the simplest and the most highly integrated memory cell in which one transistor constitutes one memory cell.

A mask ROM will be described below as an example of a technique in a conventional semiconductor memory device. As a memory cell method of a mask ROM, a plurality of cell transistors are connected in series to form a transistor row, and an enhancement type transistor and a depletion type transistor are selectively arranged in these transistor rows to write ROM data. NAND ROM
There is a NOR type ROM in which a plurality of cell transistors are connected in parallel to a bit line to form a transistor array, and in these transistor arrays, a threshold voltage is selectively set to a power supply voltage or higher and ROM data is written.

Generally, the NAND type ROM is excellent in high integration, but is inferior in high speed operation, and the NOR type ROM is high speed operation.
It excels in quick delivery, but inferior in high integration. That is, the conventional NOR type ROM requires one contact hole for connecting the wiring to one of the two memory cell transistors. Therefore, it is very difficult to miniaturize the memory cell because a region for forming the contact hole and a mask alignment margin at the time of forming the contact hole must be secured.

Therefore, for high integration, NAN is mainly used.
D-type ROM has been used. In the NAND type ROM, a plurality of cell transistors are connected in series to form a transistor row, and contact holes may be provided at both ends of the transistor row. Therefore, the higher the number of transistors connected in series, the higher the degree of integration becomes. Can be achieved. However, in recent years, there has been a demand for higher integration of memory cells.
In order to achieve higher integration by using a type ROM, measures have been taken to reduce the dimensional shift and step difference in the element isolation region.

Therefore, as one method, a high-density NOR type ROM memory cell has been proposed which performs element isolation without forming an element isolation film and has the advantages of both a NAND type ROM and a NOR type ROM. . This memory cell, as shown in FIGS.
In the memory cell formation region on the semiconductor substrate 51, the high-concentration diffusion layer 5 serving as the source / drain region and the bit line wiring is formed.
A plurality of 5 are formed in parallel, and the semiconductor substrate 51
A plurality of gate electrodes (word lines) 53 are arranged above the gate insulating film 52 so as to be orthogonal to the high-concentration diffusion layers 55 to be bit lines. Further, a region 57 where the gate electrode 53 and the high concentration diffusion layer 55 are not formed
An impurity having a conductivity type different from that of the source / drain regions is ion-implanted into the region, and this region 57 is made to function as an element isolation between the cell transistor a and the cell transistor b.

In the memory cell having such a structure, since the element isolation film such as the LOCOS film is not formed, the surface of the semiconductor substrate 51 is flat, and the gate electrode 53 is arranged at a pitch below the normally used processing limit. Can be arranged, and since the gate electrode 53 can be used as a mask to perform ion implantation in the element isolation region 57 in a self-aligned manner, there is a great effect on high integration of the memory cell. However, in this case, the element isolation oxide film is used in the peripheral circuit portion.

However, the demand for large capacity of the semiconductor device is very strict, and various studies have been made for higher integration. For example, in a NAND type ROM or high density NOR type ROM memory cell system, a method using a double polysilicon structure has been proposed in which a gate electrode formed in another step is formed between gate electrodes formed in the same step. . An example of a NAND type ROM is disclosed in JP-A-63-104469 and JP-A-63-239976.
Japanese Patent Laid-Open No. 64-31456 shows an example of NOR type ROM.

Japanese Patent Laid-Open Nos. 63-104469 and 6
In No. 4-31456, 2 is applied to the first-layer gate electrode.
Aligning the gate electrode of the second layer with an alignment margin,
It is formed so as to overlap. For this reason, there is a problem that the memory cell becomes large by the overlapping, and as a countermeasure against this, Japanese Patent Laid-Open No. 63-104469 deals with using three layers of gate electrodes. There is also a drawback that the process becomes complicated.

In view of this, in Japanese Patent Laid-Open No. 63-239976, a method of forming a second-layer gate electrode by self-alignment between the first-layer gate electrodes is adopted to form a memory cell with a minimum processing size. . The above method will be described with reference to FIG. First, as shown in FIG. 18A, on the semiconductor substrate 201 on which the element isolation oxide film 203 is formed,
The gate electrode 207 of the first layer is provided through the gate insulating film 202.
To form A second-layer polysilicon 209 to be a second-layer gate electrode is deposited on top of this with an insulating film 208 interposed therebetween. After that, a resist 231 for flattening the surface is applied to the entire surface.

Next, as shown in FIG. 18B, etching is performed so that the etching selection ratio between the resist 231 and the second layer polysilicon 209 is the same, and the second layer is formed between the first layer gate electrodes 207. The eye gate electrode 233 is formed. Further, when the second layer polysilicon is etched back, an unnecessary portion is left on the semiconductor substrate 201, so that the unnecessary portion is removed using the resist pattern 235 as a mask as shown in FIG. 18C.

Then, as shown in FIG.
Ion implantation is performed by using the gate electrodes 207 and 233 of the second layer and the second layer as masks to form diffusion layers 215 and 217. After that, as shown in FIG. 18E, ion implantation for data writing is performed in the channel regions below the desired gate electrodes 207 and 233. Next, as shown in FIG. 18F, the bit line 225 connected to the interlayer insulating film 223 and the diffusion layer 215 is formed to complete the memory.

[0013]

However, the above-mentioned Japanese Unexamined Patent Application Publication No.
Also in the method of No. 3-239976, in order to finally form the second-layer gate electrode 233, a mask process for processing the end of the second-layer gate electrode 233 (see FIG. 18).
The problem of requiring (c)) and complicating the process has not been solved.

Therefore, the present invention proposes a simple manufacturing method that does not increase the number of manufacturing steps, and aims at high integration of memory cells.

[0015]

According to the present invention, a plurality of first gate electrodes are formed in parallel on a semiconductor substrate via a first gate insulating film, and formed in a desired region on the semiconductor substrate. And a self-aligned recess formed between the first gate electrodes or between the first gate electrode and the wiring cutting insulating film via the second gate insulating film on the semiconductor substrate. There is provided a semiconductor device having a plurality of second gate electrodes formed on the substrate.

The memory cell portion and its peripheral circuit portion are provided. In the memory cell portion, except for the element isolation insulating film formed on the semiconductor substrate and the region where the element isolation insulating film is formed. A plurality of first gate electrodes formed in parallel in a region via a first gate insulating film, a wiring cutting insulating film formed in a desired region on a semiconductor substrate, and a second gate insulating film on the semiconductor substrate A plurality of self-aligned recesses are formed between the first gate electrodes, between the first gate electrodes, and between the first gate electrodes and the wiring cutting insulating film or between the first gate electrode and the element isolation insulating film through the film. There is provided a semiconductor device having two gate electrodes, and having an element isolation insulating film formed at the same time as the wiring cutting insulating film in at least the memory cell section in the peripheral circuit section.

According to another aspect of the present invention,
(i) forming a wiring cutting insulating film in a desired region on the semiconductor substrate, and (ii) covering a part of the wiring cutting insulating film on the obtained semiconductor substrate through the first gate insulating film. like,
Forming a plurality of first gate electrodes in parallel, (iii) between the first gate electrodes or the first gate via a second gate insulating film on the semiconductor substrate including the wiring cutting insulating film and the first gate electrode Provided is a method for manufacturing a semiconductor device, which comprises forming a plurality of second gate electrodes in a self-aligned manner in a recess between an electrode and the wiring cutting insulating film.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor device according to the present invention is a semiconductor device using a large-capacity memory cell circuit, such as a DRAM,
It can be applied to a part of the memory cell portion such as SRAM, EEPROM, mask ROM or the like, or to a part of the peripheral circuit portion thereof. In particular, it is preferably applied to the memory cell portion of the mask ROM, which is the simplest and has the highest degree of integration.

That is, in the semiconductor device of the present invention, at least a plurality of first gate electrodes formed in parallel on the semiconductor substrate, a wiring cutting insulating film formed in a desired region on the semiconductor substrate, It has a plurality of second gate electrodes formed in a self-aligned manner with respect to one gate electrode. The semiconductor substrate is not particularly limited as long as it is a commonly used substrate, and examples thereof include a silicon substrate.
Further, the first and second gate electrodes and the like may be formed on the semiconductor substrate, but desired elements, wiring layers and the like are formed underneath thereof, and the first and second gate electrodes are further covered with an interlayer insulating film. Also, the second gate electrode and the like may be formed. When forming the first and second gate electrodes and the like on the semiconductor substrate,
It is preferable that a source / drain region that forms a transistor together with first and second gate electrodes described below is formed in a desired region of the semiconductor substrate.

The first gate electrode is formed on the semiconductor substrate via the first gate insulating film, and it is preferable that a plurality of first gate electrodes are formed substantially in parallel. The first gate insulating film is made of a commonly used material, for example, SiO ₂ or the like.
It is preferably formed with a film thickness of about 0 to 300Å. The first gate electrode is preferably formed of a commonly used material, for example, a single layer film or a laminated film of polysilicon, silicide, polycide, etc., with a total film thickness of about 2000 to 5000 Å. Note that the first gate electrode is preferably formed to have a film thickness that is approximately the same as or smaller than the film thickness of the wiring cutting insulating film described later. In addition, the first gate electrode is formed on the upper layer, for example, with Si.
It may have an insulating film such as O ₂ or SiN, or may have a sidewall spacer on the side wall.

The wiring cutting insulating film is formed for cutting the first gate electrode and / or the second gate electrode. That is, if the second gate electrode described later is formed in a self-aligned manner with respect to the first gate electrode after forming the first gate electrode, all the second gate electrodes will be connected. In order to surely cut such a second gate electrode, an insulating film for cutting a wiring is formed, and it may be formed so as to cut only the second gate electrode (FIG. 2, upper part). 15), the first gate electrode is formed so as to be cut, and even if the alignment is deviated, the portion to be cut surely is cut, and
A margin may be provided so as not to disconnect a defective portion when disconnection occurs (see FIG. 2, lower part 15). In these cases, a part of the side surface of the first gate electrode and / or the second gate electrode is in contact with one side surface of the wiring cutting insulating film. As the wiring cutting insulating film, a commonly used insulating film such as SiO ₂ or SiN is preferably formed into a desired shape with a film thickness of about 2000 to 6000 Å.

The second gate electrode is electrically separated from the first gate electrode through at least the second gate insulating film formed on the semiconductor substrate, and the space between the first gate electrodes and / or the wiring with the first gate electrode is provided. It is preferable that the first gate electrode and the wiring cutting insulating film are formed in a self-aligning manner in such a manner that the recess formed between the cutting insulating film and the insulating film is completely buried. The second gate insulating film and the second gate electrode can be formed of the same material as the first gate insulating film and the second gate electrode. The surface of the second gate electrode is preferably covered with an insulating film such as SiO ₂ or SiN.

In the above semiconductor device, the first gate electrode and the second gate electrode can be formed at a pitch equal to the minimum processing dimension, and thus a high density device can be obtained. Further, the semiconductor device may be formed as a semiconductor device including a memory cell section and a peripheral circuit section.

In that case, in the memory cell portion, an element isolation insulating film is formed on the semiconductor substrate to define an active region, and the active region is defined by the first gate electrode,
It is preferable that the wiring cutting insulating film and the second gate electrode are formed, and at least the element isolation insulating film formed at the same time as the wiring cutting insulating film of the memory cell portion is provided in the peripheral circuit portion. The peripheral circuit portion also has a gate electrode formed at the same time as the first gate electrode of the memory cell portion and / or a wiring cutting insulating film formed at the same time as the wiring cutting insulating film of the memory cell portion. May be.

The insulating film for element isolation in the memory cell portion is formed by a known method such as thermal oxidation, CVD method or LOCO.
It can be formed by the S method or the like. Further, in order to improve the element isolation characteristics, an impurity of the same conductivity type as that of the semiconductor substrate may be implanted under the element isolation insulating film. The element isolation insulating film formed here is preferably formed at the same time as the wiring disconnection insulating film also present in the memory cell portion and the element isolation insulating film present in a peripheral circuit described later.

The first gate electrode is formed via the first gate insulating film and can be formed in the same manner as described above. In addition, the second gate electrode is electrically isolated from the first gate electrode via the second gate insulating film.
The recesses are formed between the gate electrodes and between the first gate electrode and the element isolation insulating film or the wiring cutting insulating film, and are formed in self-alignment with the first gate electrodes and the like.

The insulating film for element isolation in the peripheral circuit section is
Although it can be formed by a known method, it is preferably formed at the same time as the element isolation insulating film or the wiring cutting insulating film in the memory cell portion as described above. In addition, in the semiconductor device, other electrodes such as a source / drain electrode connected to the source / drain region, an element isolation electrode, a dummy electrode, a selection line electrode, etc. are provided together with the first gate electrode or the second gate electrode. You may form. Also, when these electrodes are directly connected to the semiconductor substrate and the electrode material contains impurities, the impurities in the electrode material are diffused from the connection surface with the semiconductor substrate, so that the source / drain is self-aligned. A diffusion layer such as a region can be formed. These electrodes can be directly connected to the semiconductor substrate by removing the insulating film previously formed in the electrode formation region and forming electrodes in the region. With this configuration, without making major changes to the process,
Source / drain electrodes can be formed.

Further, the semiconductor device of the present invention can be formed by the following steps. In step (i), first, a wiring cutting insulating film is formed in a desired region on a semiconductor substrate. The wiring cutting insulating film can be formed by a known method as described above. When an element isolation insulating film is arbitrarily formed, it can be formed at the same time.

In step (ii), a plurality of first gate electrodes are formed in parallel on the obtained semiconductor substrate with the first gate insulating film interposed therebetween so as to cover a part of the wiring cutting insulating film. That is, the wiring cutting insulating film is formed to cut the first gate electrode and the second gate electrode, and the first gate electrode formed on the wiring cutting insulating film is It will be cut when etching or the like in the process. The first gate electrode can be formed by depositing the above electrode material and then patterning it into a desired shape by photolithography and etching processes. At this time, the insulating film may be used as a mask, and the insulating film may be left as it is on the first gate electrode.
In this case, the total thickness of the first gate electrode and the insulating film is
It is preferable that the thickness is equal to or less than that of the wiring cutting insulating film. In addition, a sidewall spacer may be formed on the sidewall of the first gate electrode.

In step (iii), first, a second gate insulating film is formed on the semiconductor substrate including the wiring cutting insulating film and the first gate electrode. At this time, the second gate insulating film also covers the sidewall portion of the first gate insulating film at the same time, so that
It can also be used as an insulating film for electrically separating the gate electrode and the first gate electrode and an insulating film for covering the first gate electrode. Then, between the first gate electrodes or the first
A plurality of second gate electrodes are formed in a self-aligned manner in the concave portion between the gate electrode and the wiring cutting insulating film. To form the second gate electrode, after depositing the second gate electrode material, the second gate electrode material is first deposited by burying etch back, CMP (chemical mechanical polishing) or a combination thereof.
There is a method of leaving it in a recess between the gate electrodes or between the first gate electrode and the wiring cutting insulating film. Etching back or the like at this time is preferably performed until finally the surface of the previously formed insulating film for wiring cutting is completely exposed. Therefore, the film thickness of the second gate electrode is preferably formed to be approximately the same as the film thickness of the wiring cutting insulating film. Thereby, it is possible to prevent a short circuit of the plurality of second gate electrodes, and it is possible to reliably cut the first gate electrode formed on the wiring cutting insulating film, and at the end portion of the first gate electrode. The first gate electrode can be formed in self-alignment with the wiring cutting insulating film. Moreover, it is preferable that the obtained semiconductor substrate is subjected to an oxidation treatment after the second gate electrode is formed. By performing such an oxidation treatment, even when the first and / or second gate electrode material remains on the wiring cutting insulating film and / or the element isolation insulating film, the electrode material becomes an insulator. Since the conversion can be performed, a short circuit between the first gate electrode and / or the second gate electrode can be prevented, and the manufacturing yield of the semiconductor device can be improved.

In the above process, the first gate electrode or the second gate electrode is formed, and at the same time, another electrode on the semiconductor substrate, for example, a source / drain electrode connected to the source / drain region, an element isolation electrode, Dummy electrodes, select line electrodes, etc. can be formed. These electrodes
When the electrode material is directly connected to the semiconductor substrate and the electrode material contains impurities, the impurities in the electrode material are diffused from the connection surface with the semiconductor substrate to self-align the diffusion layers such as the source / drain regions. Therefore, it is possible to obtain a device having a high-performance and high-reliability transistor having a junction in which the source / drain region in the substrate is extremely shallow, without a large change in the process.

Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings. The present invention is not limited by these examples.

First Embodiment FIG. 1 is a mask ROM constituting a semiconductor device according to the present invention.
2 is a plan view of the memory cell of FIG. 2, and FIG. 2 shows a plan view of the peripheral circuit from the gate electrode lead-out portion at the end of the memory cell. Further, FIGS. 7A to 7D are sectional views of FIGS. 1 and 2, respectively.

In the semiconductor device according to the present invention, a plurality of first gate electrodes 5 are formed substantially parallel to each other on the semiconductor substrate 1 with the first insulating film 4 interposed therebetween, and the first gate electrode 5 is formed on a desired region.
The wiring cutting insulating films 14 and 15 have a film thickness approximately the same as that of the first gate electrode 5. In addition, the second gate electrode 9 formed in a self-aligned manner in the concave portion formed by the first gate electrode 5 and the wiring cutting insulating films 14 and 15.
Have multiple.

Although this semiconductor device is constructed according to the high density NOR type ROM memory cell system (Japanese Patent Laid-Open No. 64-31456), it has the above-mentioned double poly structure N-type.
An AND type ROM (Japanese Patent Laid-Open No. 63-104469, Japanese Patent Laid-Open No. 63-239976, etc.) can be used in the same manner. The method for manufacturing the above-described semiconductor device will be described below with reference to FIGS. Here, in FIGS. 3 to 7, (a), (b),
(C), (d), (e) are A- of FIG. 1 or 2, respectively.
Line A ', line BB', line CC ', line DD' and line E-
It is an E'line sectional view.

First, a pre-implantation oxide film (not shown) is formed on the semiconductor substrate 1. Subsequently, a plurality of resist patterns (not shown) parallel to each other are formed on the semiconductor substrate 1, and using this as a mask, ion conduction of a conductivity type opposite to that of the semiconductor substrate 1 is performed to form a plurality of source / drain regions 2. The books are formed parallel to each other. At this time, since the semiconductor substrate 1 has a flat surface, a resist pattern can be formed with a minimum processing line width, and a high-density cell can be obtained. Further, the ion implantation is, for example, in the case of forming an NMOS, arsenic ions (As ⁺ ) at a dose of 10 ¹⁵ cm ^-2 , 40 k
The implantation energy is eV.

Next, an oxide film having a film thickness of about 2000 to 5000 Å is deposited by a method such as CVD and patterned to form an element isolation oxide film 3 in a desired region. Although the LOCOS oxidation method may be used for forming the element isolation oxide film 3, a treatment at the lowest possible temperature is desirable in order to prevent diffusion of the source / drain regions 2. Then, in order to improve the element isolation characteristics, field ion implantation of the same conductivity type as the substrate is performed on the semiconductor substrate 1 below the element isolation oxide film 3 (not shown). Further, at this time, as shown in FIGS. 1 and 2, the element isolation oxide film 14 in the peripheral circuit region and the wiring cutting oxide film 15 are simultaneously formed in the vicinity of the end portion of the memory cell, and the source / source of the memory cell is formed. The oxide film 1 for cutting the wiring is also formed on the contact region 11 of the drain region 2.
5 is formed.

Then, a film having a thickness of 5 is formed on the obtained semiconductor substrate 1.
A first gate insulating film 4 having a thickness of 0 to 300 Å is formed, and a plurality of first gate electrodes 5 are arranged on the first gate insulating film 4 so as to be orthogonal to the source / drain regions 2 and parallel to each other. The gate electrode 5 includes, for example, a two-layer structure composed of a lower layer N ⁺ polysilicon film having a thickness of 1000 Å and a tungsten silicide film having a thickness of 1000 Å. It is preferable to set the film thickness to the same level as. As shown in FIG. 2, the gate electrode 5 is formed on the element isolation oxide film 14 in the peripheral circuit region and on the wiring isolation oxide film 15 formed at the same time as the element isolation oxide film 14 at and near the edges. Arrange so that they overlap. The formation of the gate electrode 5 at this time needs to prevent the disconnection failure of the second electrode formed in a later step due to misalignment or the like. Further, since alternate contact holes are formed on the gate electrode 5 in a later step, the wiring cutting oxide film 15 is formed so that the gate electrode 5 is cut at the end of the gate electrode 5 where no contact hole is formed. Need to be formed.

After that, as shown in FIG. 3, the second gate insulating film 6 and the insulating film 7 between the gate electrodes are formed. Subsequently, as shown in FIG. 4, a conductive film 8 is deposited on the obtained semiconductor substrate 1 to form the first gate electrode 5, the element isolation oxide film 3, the element isolation oxide film 14, and the wiring cutting oxide film. 15 and it is fully embedded. As the conductive film 8, for example, 2
An N ⁺ polysilicon film with a thickness of 000Å to 6000Å is used.

Next, as shown in FIG. 5, the buried conductive film 8 is self-aligned with the first gate electrode 5, the element isolation oxide film 3, the element isolation oxide film 14 and the wiring cutting oxide film 15. The second gate electrode 9 and the separation electrode 9a are formed by leaving them in between. As this method, for example, first, C
The conductive film 8 is removed by MP until the insulating film 7 between the gate electrodes 5 is partially exposed on the surface, and then the insulating film 7 between the gate electrodes 5 and the conductive film 8 are etched under the same etching rate. A method of backing up and finally using CMP to stop etching on the surfaces of the element isolation oxide film 3, the element isolation oxide film 14, and the wiring cutting oxide film 15 may be used.

Further, as shown in FIG. 6, an oxidation step is performed to form an oxide film 13 on the entire surface of the obtained semiconductor substrate 1, so that the element isolation oxide film 3 and the element isolation film 3 are separated due to variations in film thickness. The thin conductive film 8 left on the oxide film 14 and the wiring cutting oxide film 15 and on the first gate electrode 5 is oxidized to prevent a short circuit between the second gate electrodes 9. Then, ROM data is written (not shown). RO
In the NOR type cell transistor, M data is written by selectively setting the threshold voltage to the power source voltage or more by setting the OFF transistor by ion implantation of the same conductivity type as the substrate. For example, in the case of NMOS,
Boron ions (B ⁺ ) are implanted using the ROM data writing resist pattern as a mask. Further, since channels are generated in the substrate immediately below the first gate electrode 5 and the second gate electrode 9, this ROM data writing ion implantation is used to prevent the operation of the parasitic transistor.

Next, as shown in FIG. 7, formation of an interlayer insulating film 10, formation of a contact hole 11, and metal wiring 1
The second half process of the semiconductor device is completed through the process of forming 2 and the protective film forming process. As the writing of ROM data is performed in a later step, the step after inserting the ROM is shortened and the delivery time can be shortened. Therefore, after further stacking the interlayer insulating film 10,
Ion implantation for ROM data writing may be performed using implantation of high energy after the opening of the contact 11 or after the formation of the metal wiring 12.

Further, the steps after the formation of the interlayer insulating film are completely flattened, the step of forming the metal wiring 12 becomes very easy, and it is effective in increasing the density. Further, the latter half of the assembly process is performed, and the semiconductor device is completed. Further, although the NMOS has been described in the above example,
It can be similarly formed by PMOS or CMOS.

Embodiment 2 FIG. 8 shows another plan view of a memory cell of a mask ROM which constitutes a semiconductor device according to the present invention. According to this semiconductor device, at the same time as the first gate electrode 5 of the memory cell, the selection line 5a of the bank transistor B and the element isolation electrode 5b are formed of the same material, and the first gate electrode 5 is formed on a desired region. It has a wiring cutting insulating film 15 having a film thickness approximately the same as that of the electrode 5. Further, at the same time as the second gate electrode 9 and the second gate electrode 9 formed in a self-aligned manner in the recess formed by the first gate electrode 5, the selection line 5a and the wiring cutting insulating film 15, the same material is used. It has the formed element isolation electrode 9a and the selection line 9b. Note that the channel portion not used as a transistor is an off transistor at the time of writing ROM data or the like to perform element isolation.

In FIG. 8, the first gate electrode 5 and the second gate electrode 9 may be arranged in the reverse layout. Also in a semiconductor device having such a planar structure, it can be formed substantially in the same manner as in the above-described embodiment.

Embodiment 3 FIG. 9 shows another mask R constituting the semiconductor device according to the present invention.
FIG. 10 is a plan view of an OM memory cell, and FIG. 10 is a plan view of a transistor in a peripheral circuit which constitutes this semiconductor device. In addition, FIGS.
The cross-sectional views of FIG.

In the mask ROM of the semiconductor device of the present invention, the first gate electrode 25 is formed on the semiconductor substrate 21 by the first gate electrode 25.
A plurality of insulating films 23 are formed substantially parallel to each other with the insulating film 23 interposed therebetween, and the wiring cutting insulating film 17 is formed on a desired region with a film thickness substantially equal to that of the first gate electrode 25. Further, a plurality of second gate electrodes 30 formed in a self-aligned manner are provided in the recesses formed between the first gate electrodes 25 and between the first gate electrodes 25 and the wiring cutting insulating film 17.

In the peripheral circuit, the semiconductor substrate 2
A first gate electrode 25 is formed on the first electrode, and
The element isolation region 16 is formed in the periphery thereof. Also,
Source / drain electrodes 31 formed in a self-aligned manner are formed in the recesses formed between the first gate electrode 25 and the element isolation region 16. The method for manufacturing the above-described semiconductor device will be described below with reference to FIGS. Here, (f), (g), (h), (i) in FIGS.
Are FF ′ line, GG ′ line of FIG. 9 or 10, respectively.
FIG. 6 is a cross-sectional view taken along line HH 'and line II'.

First, a film thickness of 2000- is formed on the semiconductor substrate 21.
An oxide film of about 5000 Å is deposited by a method such as thermal oxidation or CVD and patterned to form an element isolation oxide film 1
6 is formed. Here, the LOCOS oxidation method may be used. Thereafter, in order to improve element isolation characteristics, field ion implantation of the same conductivity type as the substrate is performed on the semiconductor substrate 21 under the element isolation oxide film 16. At this time, as shown in FIGS. 9 and 10, a wiring cutting oxide film 17 is formed at the same time as the element isolation oxidation region 16.

Next, a pre-implantation oxide film (not shown) (or may be the gate insulating film 23) is formed on the semiconductor substrate 21, and a plurality of parallel resist patterns (not shown) are formed on the semiconductor substrate 21. Is formed, and using this as a mask, ion implantation of the opposite conductivity type to the semiconductor substrate 21 is performed to form a plurality of source / drain regions 24 in parallel with each other. At this time, since the semiconductor substrate 21 has a flat surface, a resist pattern can be formed with a minimum processing line width, and a high-density cell can be obtained. Further, for example, in the case of forming an NMOS, the ion implantation is performed by implanting arsenic ions (As ⁺ ) with a dose of 10 ¹⁵ cm ^{−2 and} an implantation energy of 40 keV.

Further, as shown in FIG.
A first gate insulating film 23 having a thickness of about 300 Å is formed, and a plurality of first gate electrodes 25 are arranged on the gate insulating film 23 so as to be orthogonal to the source / drain regions 24 and parallel to each other. As the gate electrode 25, for example, a two-layer structure including a lower layer N ⁺ polysilicon film having a thickness of 1000 Å and an upper tungsten silicide film having a thickness of 1000 Å is used. The gate electrode 25 may be covered with an insulating film 26 used as a mask when patterning the gate electrode. The thickness of the gate electrode 25 is equal to that of the insulating film 26.
It is preferable that the total film thickness is the same as that of the element isolation oxide film 16. The source / drain regions 24 of the memory cell
In the region that will be the contact portion of the first gate electrode 25.
Are arranged so as to overlap on the wiring cutting oxide film 17 between the contacts. Thereby, it can be separated from the source / drain electrode 31 in a later step. Further, since the first gate electrode 25 on the wiring cutting oxide film 17 is cut in a later step, the first gate electrodes 25 arranged on both sides of the contact can be used without any problem.
Further, as shown in FIG. 10, the first gate electrode 25 is
It is arranged so as to overlap the element isolation oxide film 16 in the peripheral circuit region. In addition, the first
The formation of the gate electrode 25 needs to prevent short-circuiting or the like of the source / drain electrode 31 formed in a later step due to misalignment or the like.

Next, as shown in FIG. 12, a sidewall spacer 27 is formed on the first gate electrode 25 by an existing method. The insulating film 26 and the sidewall spacers 27 also have a role of preventing the first gate electrode 25 from being exposed when the second gate insulating film is etched in a later step. Then, the obtained semiconductor substrate 21 is subjected to an oxidation treatment to form a second gate insulating film 28.

Further, as shown in FIG. 13, the resist pattern 29 is used to remove the second gate insulating film 28 on a portion of the second gate insulating film 28 where the source / drain electrodes 31 are to be formed. (Indicated by A in FIG. 13). Next, the resist pattern 29 is removed, and then a conductive film is deposited on the entire surface of the obtained semiconductor substrate 21, and the first gate electrode 25, the element isolation oxide film 16 and the wiring cutting oxide film 1 are deposited.
7 and 7 are embedded sufficiently. As the conductive film, for example,
An N ⁺ polysilicon film having a thickness of 2000 Å to 6000 Å is used.

Next, as shown in FIG. 14, the buried conductive film is left self-aligned between the first gate electrode 25, the element isolation oxide film 16 and the wiring cutting oxide film 15, and the second gate electrode is formed. 30 and source / drain electrode 31
To form As this method, for example, first, the conductive film is removed by CMP until a part of the insulating film 26 on the first gate electrode 25 is exposed on the surface, and then the insulating film 26 between the first gate electrodes 25 and the sidewall. Etching back may be performed under the conditions that the spacer 27 and the conductive film have the same etching rate, and finally, CMP may be used to stop at the surfaces of the element isolation oxide film 16 and the wiring cutting oxide film 15.

Subsequently, an oxide film 32 is formed on the surface of the obtained semiconductor substrate 21, so that the element isolation oxide film 16 and the wiring cutting oxide film 17 and the first gate electrode 25 are formed due to variations in film thickness. The thin remaining conductive film is oxidized and the second
Short circuits between the gate electrodes 30 and between the second gate electrode 30 and the source / drain electrodes 31 are prevented. By the heat treatment after the oxidation step, impurities of the conductivity type opposite to that of the substrate included in the source / drain electrode 31 are diffused into the semiconductor substrate 21 below the source / drain electrode 31, and a shallow source / drain junction region 33 is formed. can do.

Further, ROM data is written (not shown). In the NOR type cell transistor, the ROM data is written by selectively setting the threshold voltage to the power source voltage or more and setting the OFF transistor by ion implantation of the same conductivity type as the substrate. For example, N
In the case of MOS, boron ions (B ⁺ ) are implanted using the ROM data writing resist pattern as a mask. Further, since channels are generated in the substrate immediately below the first gate electrode 25 and the second gate electrode 30, all of the ROM data writing ion implantation is used to prevent the operation of the parasitic transistor.

Subsequently, as shown in FIG. 15, the first half step of the semiconductor device is completed through the formation of the interlayer insulating film 34, the formation of the contact hole 35, the formation of the metal wiring 36, the protective film formation step, and the like. Further, the assembly process of the latter half process is performed to complete the semiconductor device. As the ROM data is written in a later process, the process after inserting the ROM becomes shorter and the delivery time can be shortened.
Alternatively, high energy implantation may be used in a step such as after stacking, after opening the contact 35, or after forming the metal wiring 36.

In the above example, the case of NMOS has been described, but PMOS and CMOS can be similarly formed.

Fourth Embodiment FIG. 16 shows another plan view of a memory cell of a mask ROM which constitutes a semiconductor device according to the present invention.

According to this semiconductor device, the select line 25a and the element isolation electrode 25b of the bank transistor C are formed of the same material at the same time as the first gate electrode 25 of the memory cell, and the first gate electrode 25 of the memory cell is formed on the desired region. 1 gate electrode 2
5 has an insulating film 17 for cutting a wiring with a film thickness of approximately the same as that of No. 5. In addition, the second gate electrode 30 and the second gate electrode 30 which are formed in a self-aligned manner in the concave portion formed by the first gate electrode 25, the selection line 25a, the element isolation electrode 25b, and the wiring cutting insulating film 17. At the same time, it has a select line 30a and a source / drain electrode 31a of the bank transistor which are made of the same material.

Also in the semiconductor device having such a planar structure, it can be formed substantially in the same manner as the above-mentioned embodiment.

Fifth Embodiment In a NOR type ROM, the memory cells can be highly integrated by making the memory cell transistors multi-valued. As one example, if the thresholds of the NOR type memory cell transistors are selectively changed to have four values, the integration degree of the first and third embodiments is doubled to four times. Furthermore, if the multilevel levels are set in multiple stages, higher integration can be achieved. As a manufacturing method, for example, the number of times of ion implantation may be changed at the time of information writing implantation and the implantation may be performed plural times.

[0063]

According to the semiconductor device of the present invention, since the first and second gate electrodes are obtained at a pitch equal to the minimum processing size, it is possible to realize a high density element (twice as large as the conventional one). It is effective for cost reduction through large scale circuit and chip reduction. Further, by applying the above semiconductor device to a semiconductor device including a memory cell portion and a peripheral circuit portion,
A semiconductor memory device such as a large capacity mask ROM can be obtained.

Further, according to the method for manufacturing a semiconductor device of the present invention, the second gate electrode can be formed in a self-aligning and accurate manner by a relatively easy method without using a mask pattern. It is possible to realize a large-scale circuit, a high-density device, and the like, and it is possible to realize manufacturing of a large-capacity memory and suppression of process cost. Therefore, in the semiconductor process, it is effective to improve the processing accuracy and the yield, and the performance and reliability of the semiconductor device can be improved.

[Brief description of drawings]

FIG. 1 is a mask ROM which is an example of a semiconductor device of the present invention.
It is a schematic plan view of a memory cell.

2 is a schematic plan view in the vicinity of a gate electrode end of the semiconductor device in FIG.

FIG. 3 is a schematic cross-sectional view for explaining the manufacturing process of the semiconductor device of the present invention. (A) to (e) are A-A ', BB', C-C 'in FIG. 1 and D- in FIG.
It is D ', EE' sectional drawing.

FIG. 4 is a schematic cross-sectional view for explaining the manufacturing process of the semiconductor device of the present invention.

FIG. 5 is a schematic cross sectional view for illustrating a manufacturing process for the semiconductor device of the present invention.

FIG. 6 is a schematic cross sectional view for illustrating the manufacturing process for the semiconductor device of the present invention.

FIG. 7 is a schematic cross sectional view for illustrating the manufacturing process for the semiconductor device of the present invention.

FIG. 8 is a schematic plan view showing another embodiment of the semiconductor device of the present invention.

FIG. 9 is another mask R which is an example of the semiconductor device of the present invention.
It is a schematic plan view of an OM memory cell.

10 is a schematic plan view in the vicinity of a gate electrode end of the semiconductor device in FIG.

FIG. 11 is a schematic cross-sectional view for explaining the manufacturing process for the semiconductor device of the present invention. Note that (f) to (i) are FF 'and GG' in FIG. 9, H-H 'in FIG.
It is an II 'sectional view.

FIG. 12 is a schematic cross sectional view for illustrating the manufacturing process for the semiconductor device of the present invention.

FIG. 13 is a schematic cross sectional view for illustrating the manufacturing process for the semiconductor device of the present invention.

FIG. 14 is a schematic cross-sectional view for explaining the manufacturing process for the semiconductor device of the present invention.

FIG. 15 is a schematic cross sectional view for illustrating the manufacturing process for the semiconductor device of the present invention.

FIG. 16 is a schematic plan view showing still another embodiment of the semiconductor device of the present invention.

FIG. 17 is a schematic plan view and a schematic cross-sectional view showing a conventional NOR type mask ROM memory cell.

FIG. 18 is a conventional NAND-type mask R having a double poly structure.
It is a schematic sectional drawing which shows the manufacturing process of an OM memory cell.

[Explanation of symbols]

 1, 21 Semiconductor substrate 2, 24 Source / drain region 4, 23 First gate insulating film 5, 25 First gate electrode 5a, 9b, 25a, 30a Select line 6, 28 Second gate insulating film 7 Insulating film 8 Conductive film 9, 30 Second gate electrode 9a, 25b Element isolation electrode 10, 34 Interlayer insulating film 11, 35 Contact hole 12 36 Metal wiring 14, 16 Element isolation insulating film 15, 17 Wiring cutting insulating film 26 Insulating film 27 Side Wall spacer 29 Resist pattern 31 Source / drain electrode 31a Source / drain electrode of bank transistor 32 Oxide film 33 Shallow source / drain junction region A Second gate insulating film removal region B, C Bank transistor

Claims (9)

[Claims] 1. A first gate electrode formed in parallel on a semiconductor substrate via a first gate insulating film, an insulating film for cutting a wiring formed in a desired region on the semiconductor substrate, A plurality of second gate electrodes formed on the semiconductor substrate in a self-aligned manner in a recess between the first gate electrodes or between the first gate electrode and the wiring cutting insulating film via a second gate insulating film. A semiconductor device comprising: 2. A memory cell portion and a peripheral circuit portion thereof, the element isolation insulating film formed on a semiconductor substrate in the memory cell portion, and a region other than the region where the element isolation insulating film is formed. A plurality of first gate electrodes formed in parallel in a region via a first gate insulating film, a wiring cutting insulating film formed in a desired region on a semiconductor substrate, and a second gate insulating film on the semiconductor substrate A plurality of self-aligned recesses are formed between the first gate electrodes, between the first gate electrodes, and between the first gate electrodes and the wiring cutting insulating film or between the first gate electrode and the element isolation insulating film through the film. A semiconductor device having two gate electrodes, and having at least the element isolation insulating film formed at the same time as the wiring cutting insulating film in the memory cell section in the peripheral circuit section. 3. The recess is formed between the first gate electrodes or between the first gate electrode and the wiring cutting insulating film, is directly connected to the semiconductor substrate, and is formed in a self-aligned manner simultaneously with the second electrode. A source / drain electrode having a closed source / drain electrode.
Or the semiconductor device according to 2. 4. A wiring cutting insulating film is formed in a desired region on a semiconductor substrate, and (ii) a first gate insulating film is provided on the obtained semiconductor substrate.
A plurality of first gate electrodes are formed in parallel so as to cover a part of the wiring cutting insulating film, and (iii) a second gate is formed on the semiconductor substrate including the wiring cutting insulating film and the first gate electrode. A method of manufacturing a semiconductor device, comprising forming a plurality of second gate electrodes in a self-aligned manner in a recess between the first gate electrodes or between the first gate electrode and the wiring cutting insulating film via an insulating film. . 5. The source / drain directly connected to the semiconductor substrate in the step (iii), together with the second gate electrode, in the concave portion between the first gate electrodes or between the first gate electrode and the wiring cutting insulating film. The semiconductor device according to claim 4, wherein an electrode is formed. 6. The method for manufacturing a semiconductor device according to claim 4, wherein the second gate electrode is formed by buried etchback, CMP, or a combination thereof. 7. The method of manufacturing a semiconductor device according to claim 4, wherein the second gate electrode is set to have a film thickness approximately the same as the film thickness of the wiring cutting insulating film. 8. The semiconductor according to claim 4, wherein, when forming the second gate electrode, the first gate electrode arranged on the wiring cutting insulating film is cut on the wiring cutting insulating film. Device manufacturing method. 9. The method for manufacturing a semiconductor device according to claim 4, wherein the second gate electrode is formed and then subjected to an oxidation treatment.