JPH09252053A - Programming circuit, semiconductor device provided therewith, and redundancy relief method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the current consumption of a programming circuit in and the area exclusively occupied by it. SOLUTION: A programming circuit is equipped with a first fuse device FU1 to which a power supply potential Vcc is applied, a second fuse device FU2 to which a power supply potential Vcc or a grounding potential Vss can be selectively applied, and a common nodal point BR which is jointly owned by the first fuse device FU1 and the second fuse device FU2. When a normal area is actuated, the second fuse device FU2 is cut off or a potential equal to that of the first fuse device FU1 is applied to the second fuse device FU2 to keep the nodal point at the power supply potential Vcc, and when a redundant area is substituted for a defective area, either the first fuse device FU1 or the second fuse device FU2 is cut off, and the common nodal point BR is kept at a grounding potential Vss or a power supply potential Vcc through either the first fuse device FU2 or the second fuse device FU1 to form relief data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to circuit technology in a semiconductor device, and more particularly to repairing defective memory cells and defective lines (row lines, column lines) existing in a plurality of memory cells formed in a memory array. And effective technology.

[0002]

2. Description of the Related Art In semiconductor devices, as memory capacity has increased, it has become more and more difficult to manufacture a memory array that does not include any defective memory cells. In particular, in the case of a memory developed by using a new manufacturing technique, the defect level at the time of initial trial production may be high, and the yield may be extremely low if no measures are taken. As a means to solve such a problem, a redundant memory cell is configured in advance by adding several spare or redundant rows and columns,
Redundant circuits that replace defective memory cells or lines (row lines, column lines) are used.

As an example in which a technique for relieving such a defective memory cell is described in detail, for example, "Advanced Electronics I-" issued by Baifukan Co., Ltd.
9 Super LSI Memory "(issued November 5, 1994), P181-P1
There are 83.

In a redundant decoder (redundant row decoder / redundant column decoder) which is one of the repair circuits for generating repair information, a conventional programming circuit for specifically assigning a specific redundant line to a defective line is, for example, The defective line may be switched to the redundant line by the ground potential Vss, and the address of the defective line (hereinafter referred to as "relief address") may be generated by using a programming circuit to be relieved. At this time, a fuse element whose one end is connected to a power supply potential terminal (hereinafter referred to as “power supply terminal”) and a conduction resistance element whose one end is connected to a ground potential terminal (hereinafter referred to as “ground terminal”) And a node shared by the fuse element and the other end of the conduction resistance element, and an inverter having the node as an input. At this time, as the conduction resistance element, for example, a plurality of, for example, three MOSFETs connected in series so that the output level of the preceding stage is input to the gate is used. In such a circuit, when repairing a defective line, the fuse is blown and the node is set to the ground potential Vss. The relief address is programmed by cutting or uncutting the fuse.

[0005]

However, the present inventor has pointed out that such a conventional programming circuit has the following problems. One of the problems is that a through current is unavoidably generated when it is not necessary to disconnect the fuse element, which increases the current consumption of the entire device. The other is a problem that the area occupied by the programming circuit for the semiconductor device increases.

The former problem will be described in detail below.

The resistance value of the conduction resistance element between the node and the ground terminal is designed to be sufficiently larger than the conduction resistance value of the fuse element so that the node becomes the power supply potential Vcc when the fuse element is not cut. Is better. That is,
When the fuse element is not blown, if the resistance value of the conduction resistance element is small, the power supply potential V of the node for the inverter is generated.
This is because the High level potential of cc decreases, which causes a malfunction, and an excessive through current is generated between the power supply terminal and the ground terminal via the fuse element and the conduction resistance element. This is because it causes an increase in current consumption during operation.

On the other hand, when the fuse element is blown, the node must hold the ground potential Vss at the low level. In particular, even if the node is at the high level for some reason, it is necessary to bring the node to the low level as soon as the power is turned on. It is desirable that the resistance value of the conduction resistance element is small.

As described above, the resistance value of the conductive resistance element arranged between the node of the programming circuit and the ground terminal is required to have characteristics which are contradictory when the fuse element is cut and when not cut. It is expected that the gate resistance will be increased to some extent and then the conduction resistance of the fuse element will be increased as much as possible.

However, since it is necessary for the structure to electrically connect the power supply terminal and the ground terminal, even if the resistance value is increased, a weak through current as shown in FIG. 6 flows. . If the through current is, for example, about 15 μA, and the programming circuit using this is a 4 Mbit SRAM, the total current consumption per semiconductor device is about 2.1 mA. It will reach 5% to 10%.

The latter problem will be described in detail below.

When the fuse element is cut off, the node when the power is turned on is reliably kept at the low level, or the node is kept at the low level when the chip selector becomes the high level when the chip is not selected. In order to do so, it is necessary to configure a capacitor or transistor to give the circuit capacity, or to configure a flip-flop to control the potential, which increases the occupied area of the programming circuit. Is.

According to the simulation by the present inventor, the occupied area is about 0.0038 mm ² per programming circuit.
Will be required. The number of programming circuits in one chip is determined by the sum of the number of row addresses multiplied by the number of redundant row decoders, the number of column addresses multiplied by the number of redundant column decoders, and the number required for other circuit configurations. However, for example, in the above-described 4 Mbit SRAM, the total occupied area is 100 tens per chip.
It will be about 0.53 mm ² .

These problems are the same in programming circuits using either volatile elements or electrical fuse elements.

Therefore, an object of the present invention is to provide a technique capable of reducing current consumption in a programming circuit.

Another object of the present invention is to provide a technique capable of reducing the area occupied by a programming circuit in a semiconductor device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0018]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones are briefly described as follows.

That is, the programming circuit according to the present invention comprises: a first fuse element to which a first potential is applied;
It has a second fuse element to which the first potential and the second potential can be selectively applied, and a shared node shared by the first and second fuse elements, and the shared node is the first node. The second fuse element is cut to bring it to the potential, the first fuse element is cut to put the shared node to the second potential, and the shared node is separated from the shared node via the second fuse element. The second potential is applied to the node. Further, the semiconductor device according to the present invention uses such a programming circuit.

The redundancy repairing method according to the present invention repairs a defective area by using the programming circuit described above. The first potential is applied to the second fuse element to set the shared node to the first potential. If the relief circuit is made to correspond to the normal area by distinguishing between the normal area and the defective area and disconnecting the second fuse, the shared node is set to the first potential or the first potential is applied to the second fuse. If the redundant area is assigned to the defective area, the second fuse element is set to the second area.
Is applied to cut the first fuse or the second fuse to set the shared node to the first potential or the second potential, thereby generating the relief information. When operating the normal area, the first potential can be applied to the second fuse.

According to this, in the detection of the defective area, the first fuse element and the second fuse element have the same potential, so that no through current is generated. Further, when the redundant relief circuit is made to correspond to the normal area, the second fuse is blown to set the shared node to the first potential, or the first potential is applied to the second fuse. No current is generated. Then, in the redundant relief of the defective area, the second potential is applied to the second fuse element to disconnect either the first or the second fuse element. Does not flow. As a result, the current consumption during the operation of the programming circuit can be significantly reduced.

Further, since such a programming circuit in which a through current does not occur can be realized with a simple structure using two fuse elements, the area occupied by the programming circuit in the semiconductor device can be greatly reduced. Will be possible.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and a repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is a circuit diagram showing a semiconductor device in which a programming circuit according to an embodiment of the present invention is used, and FIG. 2 is a circuit diagram showing a redundant row decoder in the semiconductor device of FIG. 3 is a circuit diagram showing a programming circuit in the redundant row decoder of FIG. 2, and FIG. 4 is an explanatory diagram showing a method of handling the programming circuit of FIG.

The semiconductor device of this embodiment has, for example, 0
It is an SRAM having (k + 1) redundant rows 11 up to k and (n + 1) redundant columns 12 up to 0-n. Then, a normal memory cell M of the memory array 13
If there is a defective memory cell MC, a defective row or a defective column (hereinafter also referred to as a “defective area”) in a normal row or a normal column (hereinafter also referred to as a “normal area”), a spare. A redundant row decoder 14 and a redundant column decoder 15 for replacing the redundant row 11 or the redundant column 12 (hereinafter also referred to as “redundant area”) of
Is provided. Then, for example, when the SRAM is selected by the active row chip selector 16 and the redundant row decoder 14 and the redundant column decoder 15 are activated, the programming circuits RCT0 to RCTi + formed in the decoders 14 and 15 respectively.
The redundant row 11 and the redundant column 12 are allocated by programming the RCT (FIGS. 2 and 3) so that the selecting operation is performed in response to the address signal corresponding to the defective area and generating the relief information. It has become.

External input pads IX0 to IXi, IY0
~ Row address buffer 1 with the address input to IYj
8 and column address buffer 19 so that a predetermined memory cell MC in memory array 13 can be accessed between these buffers 18, 19 and memory array 13 by a regular row decoder 20 and column decoder 21. Is provided.

Therefore, when an address including a defective area is input to input pads IX0 to IXi, IY0 to IYj, internal row address signals X0 to Xi, BX0 to B are passed through row address buffer 18 and column address buffer 19.
Xi and internal column address signals Y0 to Yj, BY0 to BY
j is input to the redundant row decoder 14 or the redundant column decoder 15 to select either the redundant word activation signal RWD0 to RWDk or the redundant column activation signal RC0 to RCn, and at the same time, to the normal row decoder 20. On the other hand, the selection prohibition signal iNHR is output and the corresponding normal word activation signals WD0 to WDj are deactivated, or the selection prohibition signal iNHC is output to the normal column decoder 21 and the normal column selection switch / read / write circuit 22. Then, the corresponding normal column activation signals C0 to Cj are deactivated. As a result, either the redundant row 11 or the redundant column 12 is selected instead of the regular row or column.

Here, a circuit diagram of the redundant row decoder 14 is shown in FIG.
Shown in The redundant column decoder 15 is also the redundant row decoder 1
The redundant column decoder 15 will not be described because it has a configuration similar to that of the redundant column decoder 15.

As shown in the figure, the redundant row decoder 14 has internal address signals X0 to Xi and BX0 to BXi,
And a chip selection signal CS are input, programming circuits RCT0 to RCTi + 1 having first and second fuse elements FU1 and FU2, inverters INV0 to INVi + 1, and N-type MOS transistors. (Hereinafter referred to as "NMOS") and a P-type MOS transistor (hereinafter referred to as "PMOS"). Programming circuits RCT0 to RCTi and an inverter IN.
Internal address signals X0 to Xi or BX0 to B depending on the high level and low level output signals from V0 to INVi.
Transfer gate transistors Tr0 to Tri and Tr for selectively sending Xi to NAND circuits NAND0 to NANDi
0B to TriB, the output of the inverter INVi + 1 that receives the output of the programming circuit RCTi + 1 and the NAND circuit NANDi + 1 that receives the chip selection signal CS, and the output of this NAND circuit NANDi + 1. INVR
And And the NAND circuits NAND0 to NA
Inverter INV0 with each output of NDi as input
-INVi, NAND circuit NANDc which receives the outputs of the inverters INVN0-INVNi, and NAND circuit NAN
A decode circuit DEC including an inverter INVc which receives the output of Dc is provided, and a redundant word activation signal RWD0 is output, for example.

As shown in FIG. 3, the programming circuit R
CT is a first fuse element FU1 connected to a power supply terminal T of a power supply potential (first potential) Vcc, a second fuse element FU2 connected to a bonding pad BP, and these first and second fuse elements FU2. The fuse elements FU1 and FU2 are formed by a common node BR shared by the fuse elements FU1 and FU2. The power supply potential Vcc and the ground potential (second potential) Vss are selectively applied to the bonding pad BP. The fuse element FU in the present embodiment
1, FU2 is made of poly-Si wiring and is designed to be cut by a laser.
Alternatively, it may be formed of a non-volatile element. Therefore, the fuse element referred to in this specification includes all of them.

The programming circuit RC having such a configuration
At T, the shared node BR is at a high level by the power supply potential Vcc when the second fuse element FU2 is cut off, and is at a low level when the first fuse element FU1 is cut off and the bonding pad BP is at the ground potential Vss. Respectively held in. Therefore, in the first wafer probing test for detecting the defective memory cell MC, the defective row or the defective column, the bonding pad BP is tested with the power supply potential Vcc, and as a result, the second fuse is repaired when the repair is not required. When the element FU2 is cut off and the redundancy repair is performed, the first fuse element FU1 of the programming circuit RCTi + 1 is cut off, and the programming circuits RCT0 ...
Fuse element FU1 or fuse element FU of RCTi
Be sure to disconnect either of the two and generate the relief information corresponding to the defective area. Then, in the case of the second wafer probing test or product assembly, the bonding pad BP is used.
To the ground potential Vss, the shared node BR becomes High
It is possible to set a desired potential of level (when the second fuse element FU2 is cut off) or low level (when the first fuse element FU1 is cut off).

Redundant relief of a defective area in the semiconductor device having such a configuration is performed as follows.

First, in the first wafer probing test, the potential of the bonding pad BP is set to the power source potential V.
Testing as cc, defective memory cell M
C, defective row or column is detected. At this time, the first and second fuse elements F of RCT in the programming circuit
Since U1 and FU2 are connected in series between the bonding pad BP and the power supply potential Vcc, and the potential of the bonding pad BP is the power supply potential Vcc, a through current flowing from the power supply terminal T to the bonding pad BP is not generated.
In addition, the programming circuit RCTi + 1 and the inverter IN
The output of this circuit is at a low level due to Vi + 1, and therefore the redundant word activation signal RWD0 is inactive.

Here, as a result of the first wafer probing test, for example, when the row address of the defective memory cell MC in the memory array 13 in FIG. 1 is the highest address, the highest address of the row address is externally applied. When input, the redundant word activation signal RWD0 is set to a high level and programmed so as to be in a selected state.

That is, as shown in FIG. 4, in the programming circuits RCT0 to RCTi, the second fuse element FU is used.
2 is cut off (Fig. 4 (a)), and the programming circuit RCT
At i + 1, the first fuse element FU1 is cut off (see FIG. 4).
(B)). Then, at the time of the second wafer probing test and assembling as a product, the bonding pad BP is set to the ground potential Vss level. FIG.
When the second fuse element FU2 shown in (a) is cut, the bonding pad BP does not have to be fixed to the ground potential Vss.

As a result, the programming circuits RCT0 ...
The output of the common node BR of RCTi is at the high level, the outputs from the inverters INV0 to INVi are at the low level, and the transfer gate transistors Tr0 to Tri are in the conductive state, and T
r0B to TriB are turned off, the output of the programming circuit RCTi + 1 is low level, and the inverter IN
The output of Vi + 1 is High level and the chip select signal CS is High.
And the NAND circuit NANDi + 1 becomes Low level,
The inverter INVR goes high, and the outputs of the NAND circuits NAND0 to NANDi of the decoding circuit DEC are Lo.
w level, the output of inverters INVN0 to INVNi
High level, the output of the NAND circuit NANDc becomes Low level, and the redundant word activation signal RWD0 output from the inverter INVc becomes High level and shifts to the selected state.

At this time, 2 of RCT in the programming circuit
Since one of the two fuse elements FU1 and FU2 is always cut off, no through current is generated between the power supply terminal T having the power supply potential Vcc and the bonding pad BP having the ground potential Vss. Further, the input level of the inverters INV0 to INVi + 1 is also the level of the power supply potential Vcc or the ground potential Vss, and no through current is generated. Therefore, it becomes possible to reduce the current consumption in the circuit.

Further, since the circuit can be constructed by using the two fuse elements FU1 and FU2 instead of many transistors and capacitors, the area occupied by the programming circuit RCT in the semiconductor device is greatly reduced. be able to.

(Second Embodiment) FIG. 6 is a circuit diagram showing a main part of a semiconductor device using a programming circuit according to another embodiment of the present invention in FIG.

As shown in the figure, in the semiconductor device of this embodiment, the conventional programming circuit R is applied to the input of the second fuse element of the programming circuits RCT0 to RCTi + 1.
CTV is connected.

This conventional programming circuit RCTV
Is composed of a fuse element FU having one end connected to the power supply terminal T of the power supply potential Vcc and, for example, three MOSFETs connected in series, one end of which is set to the ground potential Vss and turned on by the chip selection signal CS. Conductive resistance element R
And a shared node S shared by the fuse element and the other end of the conduction resistance element, and an inverter I having the shared node S as an input.
And an inverter INVk which receives the output of the inverter INVj as an input.
Is connected to the second fuse element FU2.
Therefore, from the conventional programming circuit RCTV, when the fuse element FU is not cut off, the power supply potential V
When cc is output and the fuse element FU is cut off, the ground potential Vss is output.

Redundant relief of a defective area in the semiconductor device having such a structure is performed as follows.

In the first wafer probing test, the fuse element FU of the conventional programming circuit RCTV is used.
Is disconnected to bring the power supply terminal T and the common node S in the circuit into conduction, and the potential of the common node S is used as the power supply potential Vcc for testing to detect a defective memory cell MC, a defective row or a defective column. Here, since the output of the programming circuit RCTi + 1 of the present invention is at the Low level, the redundant word activation signal RWD0 is inactive. At this time, the first and second fuse elements FU1 and FU2 in the programming circuits RCT0 to RCTi + 1 according to the present invention are connected to the power supply terminal T.
Connected in series between the output of the conventional programming circuit RCTV and the conventional programming circuit RTV.
Since the output of CTV is the power supply potential Vcc, no through current is generated in the programming circuits RCT0 to RCTi + 1 of the present invention.

When the row address of the defective memory cell MC found as a result of the wafer probing test is the highest address, the row address in which the defective memory cell MC exists is input from the outside, for example, redundant word activation. The signal RWD0 goes to the high level to bring it into the selected state, and the program is performed to relieve the defective memory cell MC and the relief information is generated by the following procedure.

First, the programming circuits RCT0 to RC
The second fuse element FU2 of Ti is blown, the first fuse element FU1 of the programming circuit RCTi + 1 is blown, and the fuse element FU of the conventional programming circuit RCTV is blown.

As a result, as in the case of the first embodiment described above, when the highest row address in which the defective memory cell MC exists is input from the outside, the outputs of the NAND circuits NAND0 to NANDi in the decode circuit DEC are all Low. Then, the redundant word activation signal RWD0 output from the inverter INVc becomes High level and shifts to the selected state.

At this time, the programming circuits RCT0 ...
Since one of the two fuse elements FU1 and FU2 in RCTi + 1 is always cut off, the programming circuit RC
No through current is generated from T0 to RCTi + 1. Further, the input level of the inverters INV0 to INVi + 1 is also the level of the power supply potential Vcc or the ground potential Vss, and no through current is generated. Therefore, it becomes possible to reduce the current consumption in the circuit.

Since a structure in which such a through current does not occur can be realized by the programming circuits RCT0 to RCTi + 1 and the two fuse elements FU1 and FU2 and the conventional programming circuit RCTV, the programming circuit in the semiconductor device can be realized. RCT0 to RCTi +
1, The area occupied by RCTV can be greatly reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, the first and second fuses FU
1, the potential applied to FU2 is reversed from that of this embodiment, the first fuse element FU1 is set to the ground potential Vss, and the second fuse element FU2 is set to the ground potential Vss in the first probing test to inspect the memory cell MC. And the second fuse element FU during the next probing test and assembly.
2 can also be used as the power supply potential Vcc.

[0051]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1). That is, according to the redundancy repair programming technique of the present invention, the second method is used for detecting a defective area.
Since the testing is performed with the fuse element of No. 1 as the first potential, the first fuse element and the second fuse element have the same potential, so that no through current is generated. Then, for the redundant relief of the defective area, the second potential is applied to the second fuse element to disconnect either the first or the second fuse element to generate the relief information. In that case, no through current flows. Therefore, the current consumption during the operation of the programming circuit can be reduced to almost zero.

(2) Further, since the structure of the programming circuit in which such a through current does not occur can be realized by the two fuse elements without using many transistors and capacitors, the programming in the semiconductor device can be performed. The area occupied by the circuit can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor device in which a programming circuit according to a first embodiment of the present invention is used.

FIG. 2 is a circuit diagram showing a redundant row decoder in the semiconductor device of FIG.

FIG. 3 is a circuit diagram showing a programming circuit in the redundant row decoder of FIG.

4A and 4B are explanatory views showing a method of handling the programming circuit of FIG.

FIG. 5 is a circuit diagram showing a main part of a semiconductor device using a programming circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a shoot-through current assumed in a conventional programming circuit examined by the present inventor.

[Explanation of symbols]

 11 redundant row 12 redundant column 13 memory array 14 redundant row decoder 15 redundant column decoder 16 chip selector 18 row address buffer 19 column address buffer 20 row decoder 21 column decoder 22 column selection switch / read / write circuit BP bonding pad BR shared node DEC Decode circuit FU Fuse element FU1 First fuse element FU2 Second fuse element INV0 to INVi inverter INVN0 to INVNi inverter INVR inverter INVc inverter INVj inverter INVk inverter IX0 to IXi input pad IJN NAND pad IY0 to IY0 memory cell 1 NAND circuit NANDc NAND circuit R Conductive resistance element RCT0 to RCTi + 1 Programming circuit RCTV Conventional programming circuit Path RCT programming circuit S shared node T power supply terminal Tr0 to Tri transfer gate transistor Tr0B to TriB transfer gate transistor Vcc power supply potential Vss ground potential

Front page continued (72) Inventor Kenka Watanabe, Nakajima, 145, Nanae-cho, Kameda-gun, Hokkaido Inside Hitachi Kitami Semiconductor Co., Ltd. (72) Yoshito Fujimoto, 145 Nakajima, Nanae-cho, Kameda-gun, Hokkaido Inside Hitachi North Sea Semiconductor Co., Ltd.

Claims (4)

[Claims] 1. A first fuse element to which a first potential is applied, a second fuse element to which a first potential and a second potential can be selectively applied, and the first and second fuse elements. A programming circuit having a shared node shared by a second fuse element, wherein the second fuse element is cut off when the shared node is at a first potential, and the shared node is at a second potential. In the case of the above, the first fuse element is cut, and the second fuse element is connected to the second node at a node different from the shared node.
A programming circuit characterized by applying the electric potential of. 2. A semiconductor device, wherein the programming circuit according to claim 1 is used. 3. A redundancy relieving method comprising the programming circuit according to claim 1 and using a relieving circuit for allocating a predetermined redundant area in place of a defective area to relieve the defective area. A first potential is applied to set the shared node to the first potential to discriminate between a normal area and a defective area, and when the relief circuit corresponds to the normal area, the second fuse of the programming circuit is cut off. Then, when the shared node is set to the first potential and the redundant area is assigned to the defective area, the second potential is applied to the second fuse element, so that the first fuse element or the second fuse element A redundant relief method, wherein relief information is generated by cutting either of the shared nodes to a first potential or a second potential. 4. The redundancy repair method according to claim 3, wherein when the normal area of the redundancy repair method is operated, a first potential is applied to the second fuse.