JPH09251783A - Refresh control method, semiconductor storage device, and data processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a refreshing operation time in a dynamic operation mode of a shadow RAM. SOLUTION: This device is provided with a first control means 185 in which refreshing operation of a storage region is stopped and memory access has priority, a storage means 193 which can store a storage region in which refreshing operation is stopped, a second control means 192 for performing the next time memory access for a memory region in which refreshing is stopped with a non-volatile operation mode based on storage information. And when refreshing operation and external memory access conflicts each other, a refreshing time is made apparently zero by making external memory access have priority.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a refresh control technique for a semiconductor memory device in which a plurality of memory cells are formed to include a capacitor made of a ferroelectric thin film, and more particularly to a technique effectively applied to a data processing device.

[0002]

2. Description of the Related Art PZT (lead zirconate)
A ferroelectric memory is known as a memory that performs a non-volatile operation by utilizing the polarization characteristics of a ferroelectric having a perovskite type crystal structure such as a titanate). Since the nonvolatile operation is performed, in a computer system, etc. equipped with a ferroelectric memory, the state when the power was turned off can be immediately restored when the power is turned on again, and the stored information is backed up by the battery. There is no need.

However, in the ferroelectric memory, the number of times of rewriting is 1 because the polarization inversion operation is involved.
It is limited to about ¹⁰ times, and cannot be used for 10 years in applications such as the main memory of a computer system for performing random access. A memory cell formed of a ferroelectric substance such as PZT basically functions as a memory cell of a DRAM (Dynamic Random Access Memory). It is effective to perform a read / write operation as in the case of a DRAM, and use a polarization characteristic of a ferroelectric substance to perform a nonvolatile operation when the power is cut off.

A mode of non-volatile operation utilizing the polarization characteristics of the ferroelectric substance is referred to as "non-volatile operation mode", and a mode of volatile operation utilizing the charge storage function of the capacitor is referred to as "dynamic operation mode". . Since the dynamic operation mode operates in the same manner as a normal DRAM, it is necessary to refresh the stored information at predetermined time intervals. The semiconductor memory in which the memory cell is thus formed including the capacitor made of the ferroelectric thin film such as PZT and realizes the nonvolatile operation mode and the dynamic operation mode as described above is called "shadow RAM".

As an example of a document describing the shadow RAM, there is JP-A-7-21784.

[0006]

In the shadow RAM, the number of memory cells operating at the same time is limited in order to prevent an increase in power consumption. In the dynamic operation mode of the shadow RAM, refresh is required as in the case of the DRAM, so that the number of refresh cycles tends to increase as the storage capacity increases. Basically, the refresh operation is prioritized during the refresh operation and random access from the outside of the chip is prohibited. Therefore, if the number of refresh cycles increases as the storage capacity increases, the refresh time becomes longer. Data cannot be read and written efficiently. This hinders reduction of data processing time in a data processing device such as a computer system.

An object of the present invention is to shorten the refresh operation time of shadow RAM.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, it is determined whether the memory mat corresponding to the internally generated refresh address is in the nonvolatile operation mode or the dynamic operation mode,
If it is determined that the memory mat is in the dynamic operation mode, the memory mat corresponding to the refresh address is refreshed (step S54), and the memory mat corresponding to the address externally provided for memory access is being refreshed. Is determined (step S62), and when it is determined that the memory is being refreshed, the refresh operation of the memory mat is stopped and the memory access based on the external address is prioritized (step S63). For the memory mat for which the refresh operation has been stopped, the next memory access is performed in the non-volatile operation mode.

Also, when the memory area corresponding to the address given from the outside for memory access is undergoing the refresh operation, the refresh operation of the memory area is stopped and the memory access is prioritized. 18
5) and storage means (19) capable of storing the identification information of the storage area in which the refresh operation has been stopped by the first means.
And 3) and second control means (191, 192) for performing the next memory access to the storage area for which the refresh is stopped in the non-volatile operation mode based on the storage information of the storage means. Configure the device.

Further, a data processing device can be formed by including the semiconductor memory device and a central processing unit that can access the semiconductor memory device.

In the shadow RAM, if the operation method in which the information due to the charge storage of the capacitor and the information utilizing the polarization characteristic always match at the time of operation, the area where refresh is not performed in the dynamic operation mode is Information stored due to charge accumulation in the capacitor is destroyed, but stored information using polarization characteristics is not destroyed. Therefore, when the refresh operation conflicts with the external memory access, the refresh operation is stopped and the external memory access is prioritized, so that the refresh time is apparently set to zero. This achieves a shorter refresh time. The stored information in the storage area related to the suspension of refresh is read in the non-volatile operation mode using the polarization characteristic.

[0014]

FIG. 2 shows a computer system which is an embodiment of a data processing device according to the present invention.

The computer system shown in FIG.
Although not particularly limited, C via the system bus BUS
PU (Central Processing Unit) 31, Shadow RAM (Random Access Memory) 33, ROM (Read Only)
The memory) 34, the peripheral device control unit 35, the display system 36, and the like are coupled so that signals can be exchanged with each other, and predetermined data processing can be performed according to a predetermined program. The CPU 31 is a logical core of the present system, and mainly includes address designation, reading and writing of information, data operation, sequence of instructions, acceptance of interrupts, activation of information exchange between a storage device and an input / output device, and the like. And has an arithmetic control unit, a bus control unit, a memory access control unit, and the like. The shadow RAM 33 and the ROM 34 are positioned as an internal storage device. Various programs and data are stored in the ROM 34. The shadow RAM 33 is loaded with programs and data required for calculation and control by the CPU 31. The peripheral device control unit 35 controls the operation of the storage device 38,
Information input control from the keyboard 39 or the like is performed. As the storage device 38, an auxiliary storage device such as a hard disk device is applied.

FIG. 1 shows a configuration example of the shadow RAM 33.

Although not particularly limited, the shadow RAM 33 shown in FIG. 1 is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

Reference numerals 9-1 to 9-n denote memory cell arrays, which are schematically shown in a mat-divided state. The divided mat is called a memory mat. Each of the memory mats 9-1 to 9-n has a plurality of memory cells arranged in an array. Although the memory cell is not particularly limited, it is formed of a ferroelectric thin film such as PZT. Therefore, the polarization characteristic of the ferroelectric is used to make a non-volatile operation mode and a charge storage function of a capacitor formed of the ferroelectric. A dynamic operation mode utilizing is realized. Row decoders (XD) 12-1 to 12 corresponding to the memory mats 9-1 to 9-n, respectively.
-N are arranged, and a signal for driving the word line to the selection level is generated. Also, the memory mat 9-
Sense amplifier groups 8-1 to 8-n are arranged corresponding to 1 to 9-n so that minute signals (memory cell data) output from the corresponding memory mats are amplified. Further, an input / output circuit (I / O) 10 is provided, and an external output (Do) of the signal amplified by the sense amplifiers 8-1 to 8-n and an input data Di externally given as write data are provided. It is designed to be imported. The input / output circuit 10 includes a column selection circuit for selectively coupling a plurality of bit lines to a common data line, and this column selection circuit is controlled by a column selection signal generated by a column decoder (YD) 11. .

As a clock signal fetched for external memory access, a row address strobe signal RAS * (in this specification, * indicates row active or signal inversion) indicating the validity of a row address, and a column There is a column address strobe signal CAS * or the like indicating the validity of the address, and these are input to the timing control circuit 13. In the timing control circuit 13, the row address strobe signal RAS *,
Based on the input of the column address strobe signal CAS *, an operation control signal for each unit is generated.

The address ADR for external memory access is latched by the latch circuit 15. The address ADR is taken in by the address multi method, the address ADD input during the period when the row address strobe signal RAS * is asserted to the low level is latched as a row address in the latch circuit 15, and the column address strobe signal CAS * is also used. The address ADR input during the period when is asserted to the low level is latched by the latch circuit 16 as a column address. The row address latched by the latch circuit 15 is predecoded by the predecoder 17 arranged in the subsequent stage, and the decoded output signal is transmitted to the row decoders 12-1 to 12-n. on the other hand,
The column address latched by the latch circuit 16 is transmitted to the column decoder 11.

Further, the memory mats 9-1 to 9-n are provided.
In the dynamic operation mode, the auto-refresh controller 18 is provided to refresh the memory mats 9-1 to 9-n in units of mats. The auto-refresh control unit 18 uses the memory mat 9
By internally generating a refresh address for refreshing -1 to 9-n, the refresh cycle is automatically activated at a predetermined time interval without receiving an instruction to activate the refresh cycle from the outside.
The refresh address generated in the auto-refresh controller 18 is predecoded internally and then transmitted to the row address decoders 12-1 to 12-n. Then, the mode control unit 19 determines whether the selected memory mat is in the dynamic operation mode or the nonvolatile operation mode and controls the operation of each unit.

Next, the detailed structure of each part will be described.

The auto-refresh control section 18 has a timer 181 for measuring time, and a refresh clock (simply called a clock) under the control of the timer 181.
A clock generation circuit 182 for generating CLK, a refresh counter 182 for sequentially generating refresh addresses, a latch circuit 184 for latching an output address of the refresh counter 183 based on an output clock of the clock generation circuit 182, A predecoder 186 for predecoding the output address of the latch circuit 184 and a memory mat corresponding to the address ADR input for external memory access are provided.
And a refresh determination circuit 185 for determining whether or not refresh is currently being performed. This predecoder 1
The output signal of 86 is the row decoders 12-1 to 12-n.
Is transmitted to The output address from the latch circuit 15 and the output address from the latch circuit 184 are input for the determination of the refresh determination circuit 185, and the addresses input for memory access from the outside by comparing the input addresses. It is determined whether the memory mat corresponding to ADR is currently being refreshed,
The determination result is transmitted to the clock generation circuit 182 and the timing control circuit 13. Specifically, when it is determined that the memory mat corresponding to the address ADR input for external memory access is currently being refreshed, the clock generation circuit 182 is instructed to stop clock generation. It By stopping the clock generation in accordance with this instruction, the latch circuit 184 does not latch the output address of the refresh counter 183. Further, the timing control circuit 13 performs timing control for smoothly performing a read or write operation on the memory mat in accordance with an instruction from the mode control circuit 191. For example, based on an instruction from the mode control circuit 191, the timing control circuit 13 controls the word line rise timing for the refresh operation, the precharge level, the precharge timing, and the operation timing control of the sense amplifier. The operation timing of each unit for each operation mode will be described in detail later.

The mode control unit 19 is not particularly limited, but a register 193 for storing identification information of the dynamic operation mode or the nonvolatile operation mode for each of the memory mats 9-1 to 9-n, and the register 193. A mode determination circuit 192 for determining the mode of the memory mat by referring to the stored information, and this mode determination circuit 1
Based on the determination result of 92, the clock generation circuit 182
And a mode control circuit 191 for instructing the timing control circuit 13 to perform appropriate operation control for each mode.
When it is determined in the mat unit whether the operation mode is the dynamic operation mode or the non-volatile operation mode, the register 19 has a storage capacity necessary to store the identification information of the operation modes of all the mats in the memory cell array. Prepare Although not particularly limited, the operation mode identification information may be a flag. That is, depending on whether the flag bit corresponding to the memory mat has the logical value "1" or the logical value "0", the mode determination circuit 1
It is possible to determine the operation mode in 92. Further, when the operation mode determination circuit 192 determines that the memory mat is in the dynamic operation mode, the generation of the clock CLK in the clock generation circuit 182 is permitted by the control of the mode control circuit 191. As a result, the output address of the refresh counter 183 is latched by the latch circuit 184, so that the refresh address can be output. On the other hand, when it is determined that the operation mode is the non-volatile operation mode, refresh is not necessary, so that the generation of the clock CLK in the clock generation circuit 182 is stopped and the latch circuit 184 is stopped.
Address latch is not performed. In addition, the mode control circuit 191 includes the timing control circuit 13
In response to the operation mode, the operation timing is instructed.

FIG. 3 shows a configuration example of a memory cell array including the memory mats 9-1 to 9-n in relation to its peripheral circuits.

The memory mat includes a plurality of word lines WL0 to WL2 and a plurality of complementary bit lines BLT arranged so as to intersect the word lines, as shown in FIG.
0, BLB0, BLT1, BLB1, BLT2, BLB
2 and a memory cell MC arranged at the intersection of the word line and the bit line. Since all memory cells MC have the same configuration, one of them will be described in detail.
The memory cell MC is not particularly limited, but includes a capacitor 131 formed of a ferroelectric thin film such as PZT,
N-channel MOS transistor 1 coupled to it
32 and 32. The other electrode of the capacitor 131 is called a plate electrode, and the plate potential VPL is applied to this plate electrode. The plate potential VPL is not particularly limited, but is set to a voltage level which is half that of the high potential side power supply Vcc, that is, Vcc / 2 level. Further, the shared configuration is adopted, and the sense amplifier SAC and the precharge circuit P which are the memory mat peripheral circuits are adopted.
The CC and the column switch circuit CSW are shared by the memory mats arranged so as to sandwich them. That is, the bit lines BLT0, BLB0, BLT
1, n BLB1, BLT2, BLB2
Channel type MOS transistors (referred to as shared MOSs) 35 and 36 are arranged, and the shared MOSs 135 and 136 select a memory mat. For example, in the non-selected state, the shared control signals SHR and SHL are both set to the high level and the plurality of shared MOSs 135 and 136 are turned on. However, when the memory mat is selected, the non-selected mat side The shared MOS is turned off. That is, when the memory mat including the word lines WL0, WL1 and WL2 shown in FIG. 3 is selected, the shared control signal SH
L is shifted to the low level and a plurality of shared MOS1
Although not shown in FIG. 3, the memory mat arranged on the right side of the plurality of shared MOSs 136 is electrically cut off, although not shown in FIG.

FIG. 4 shows a configuration example of the sense amplifier SAC, the precharge circuit PCC, and the column switch circuit CSW.

The plurality of sense amplifiers SAC, the precharge circuit PCC, and the column switch circuit CSW have the same structure, and are formed by a plurality of unit circuits. Here, the complementary bit lines BLT0 and BLB are typically used.
Those corresponding to 0 will be described in detail.

The sense amplifier SAC is not particularly limited, but n-channel type MOS transistors Q11 and Q1 are used.
2, and p-channel type MOS transistors Q13, Q
A flip-flop is formed by connecting 14 together. MO
The sense amplifier activation signal SN is input to the series connection node of the S transistors Q11 and Q12, and the sense amplifier activation signal SP is input to the series connection node of the MOS transistors Q13 and Q14. Sense amplifier start signal SN is high level, sense amplifier start signal S
When P becomes low level, this sense amplifier SAC
Is activated, at which time the complementary bit lines BLT0,
The small signal between BLB0 is the high-potential-side power supply Vcc level,
And is amplified to the low-potential-side power supply Vss level.

The precharge circuit PCC comprises an n-channel type MOS transistor Q15 and n-channel type MOS transistors Q16, Q17 which are connected so as to short-circuit the complementary bit lines BLT0, BLB0. n
The channel type MOS transistors Q16 and Q17 are connected in series, and the precharge voltage VPC is connected to the series connection point.
Is applied. Further, the precharge control signal PC is input to the gate electrodes of the n-channel type MOS transistors Q15, Q16 and Q17. When the precharge control signal PC is asserted to the high level, the complementary bit lines BLT0, BLB
0 precharge is performed. Precharge voltage VPC
When accessing in the dynamic operation mode,
It is set to Vcc / 2 level, but in the non-volatile operation mode, it is temporarily set to the low potential side power supply Vss level immediately before word selection for its operation.

The column switch circuit CSW is composed of n-channel type MOS transistors Q18 and Q19 coupled to each other. This n-channel type MOS transistor Q18, Q
A column selection signal YS0 obtained by decoding the column address in the column decoder 11 shown in FIG. 1 is input to the gate electrode 19 of the column decoder 19. When the column selection signal YS0 is at a high level, n channels are input. Type M
The OS transistors Q18 and Q19 are turned on, and the signals on the complementary bit lines BLT0 and BLB0 change to the complementary common line CI0.
It is transmitted to T, CI0B.

Next, the auto-refresh operation sequence will be described with reference to the flowchart shown in FIG.

A trigger signal is generated at a predetermined cycle from the timer 181 shown in FIG. 1, and the trigger signal is generated.
By inputting to 82, this clock generation circuit 1
The clock CLK is generated from 82 (step S5
1), the output signal of the refresh counter 183 is latched by the latch circuit 184 (step S52). Then, the mode determination circuit 192 causes the latch circuit 18 to operate.
Whether or not the memory mat corresponding to the address latched in No. 4 is currently in the dynamic operation mode is determined by also referring to the mode identification information in the operation of the register 193 (step S53). When it is determined in this determination that the operation mode is the dynamic operation mode (YES), the mode control circuit 191 controls the clock generation circuit 182 to permit clock generation, and the timing control circuit 13 receives an instruction. The refresh operation is performed by generating various control signals in the refresh operation (step S54). When it is determined in the determination of step S53 that the dynamic operation mode is not set, it means that the memory mat corresponding to the address latched by the latch circuit 184 is currently in the nonvolatile operation state. However, since the refresh operation for that is unnecessary, the clock CL from the clock generation circuit 182 is generated.
When the generation of K is stopped, the refresh counter 1
Transmission of the refresh address from 83 is blocked, and in that case, the refresh of the memory mat is not performed. In this way, the above operation is repeated each time the trigger signal is output from the timer 181 at a predetermined cycle, whereby the memory mats are automatically refreshed. As described above, the mode determination is performed based on the operation mode identification information in the register 193, and the refresh is performed only when the dynamic operation mode is set. Therefore, regardless of the operation mode, it is uniform. As compared with the case where the refresh operation is performed, the power consumption accompanying the refresh operation can be minimized.

Next, the case where the memory access by the address input from the outside and the refresh operation conflict with each other will be described with reference to the flowchart of FIG.

When the address ADR is input from the outside (step S61) and the input address ADR is latched by the latch circuit 15 under the control of the timing control circuit 13, the refresh decision circuit 185 causes the memory corresponding to the input address ADR. It is determined whether the mat (selected mat) is currently being refreshed (step S62). In this determination, if it is determined that the selected mat is being refreshed (YES), the generation of the clock CLK in the clock generation circuit 182 is stopped, so that the refresh operation for the memory mat is immediately stopped. , And the mode determination circuit 192
Thus, the register 193 is rewritten (step S63). This register rewriting is identification information indicating that the dynamic operation mode has been changed to the nonvolatile operation mode. For example, when the flag bit of the register 193 has a logical value "1" as the dynamic operation mode and the logical value "0" as a non-volatile operation mode, the register rewriting in step S63 is , The flag bits corresponding to all the words in the memory mat in which the refresh is stopped are rewritten from the logical value "1" to the logical value "0". And
This time, it is determined whether or not the selected mat is in the non-volatile operation mode (step S66). This determination is performed by the mode determination circuit 192 with reference to the operation mode identification information in the register 193.

If it is determined in the above step S62 that the selected mat is not being refreshed (NO), the current refresh operation is not stopped and
The process moves to the determination in step S64. When it is determined that the selected mat is not in the non-volatile operation mode (NO) in the determination in step S64, the memory access corresponding to the dynamic operation mode is performed (step S66).

If it is determined that the operation mode is the non-volatile operation mode (YES) in the determination in step S64,
A memory access corresponding to the non-volatile operation mode is performed (step S65), and the register 193 is rewritten.
In the non-volatile operation mode access in step S65, all the words in the memory mat selected by external addressing are sequentially driven to the selection level and the recall operation (switching to the dynamic operation mode) is performed. That is, when the memory cell data is output to the complementary bit lines by sequentially driving all the words in the memory mat selected by external addressing to the selection level, the corresponding sense amplifier performs signal amplification. As a result, charge is stored in the capacitor of the memory cell based on the read information, and the nonvolatile operation mode is switched to the dynamic operation mode. At this time, only the data for the word corresponding to the externally input address ADR is externally output by the column selection, and the other data is not externally output. In response to the above recall operation, the operation mode identification information of the corresponding memory mat is rewritten in the register 193. As a result, the next memory access to the memory mat related to the recall operation is performed in the dynamic operation mode with reference to the operation mode identification information in the register 193 by the mode determination circuit 192.

FIG. 7 shows the operation timing when the memory mat for external memory access is being refreshed.

When the memory mat corresponding to the input address ADR is being refreshed as described above, the refresh decision circuit 185 causes the refresh stop signal ST to be generated.
Is asserted, the generation of the clock CLK from the clock generation circuit 182 is stopped, and the memory access from the outside is prioritized. That is, when the refreshing signal is asserted to the high level during the period when the row address strobe signal RAS * is asserted to the low level, the generation of the clock CLK is stopped,
The word line WL involved in the refresh operation shifts from the high-level selected state to the low-level non-selected state, so that the refresh is stopped. Then, by decoding the input address ADR, the word line WL corresponding to the input address ADR is shifted to the high-level selected state, and the corresponding memory cell data can be read. In the example shown in FIG. 7, a slight signal change occurs in the complementary bit line in the refresh operation, but it disappears due to the suspension of the refresh,
After that, by selecting the word line for the memory access, the memory cell information is read out to the corresponding complementary bit lines BLT and BLB, and the sense amplifier corresponding thereto reads the high potential side power supply Vcc level and the low potential side power supply Vss.
It is amplified to the level.

Next, the memory access in the non-volatile operation mode and the memory access in the dynamic operation mode will be described.

FIG. 8 shows the read operation timing of the memory cell data in the non-volatile operation mode.

For convenience of description, the relationship between the word line WL0 and the complementary bit lines BLT0 and BLB0 will be described.

In the non-volatile operation mode, the word line W
Immediately before L is selected, the precharge voltage VPC is Vcc
The word line WL0 is selected after the / 2 level is changed to the low-potential-side power supply Vss level and the precharge control signal PC is negated to the low level. That is, the bit line BL
After precharging T0 and BLB0 to the low-potential-side power supply Vss level, word line selection is performed and data reading is performed. As a result, the memory cell data due to the polarization characteristics of the ferroelectric memory cell is transferred to the complementary bit lines BLT0, BLT0.
It is output to LB0 and then the sense amplifier start signal S
As P and SN are asserted and the sense amplifier SAC is operated, the minute signals on the complementary bit lines BLT0 and BLB0 are at the high potential side power supply Vcc level and the low potential side power supply V
It is amplified to the ss level. By this read operation, charges are accumulated in the capacitor of the memory cell for the above data read, so that the dynamic operation can be performed next time.

FIG. 9 shows the read operation timing of the memory cell data in the dynamic operation mode.

The read operation of the memory cell data in the dynamic operation mode is basically the same as that of the normal DRAM. The operation timing shown in FIG. 9 differs from the case of the nonvolatile operation mode shown in FIG. 8 in that the precharge voltage VPC is constant at Vcc / 2 level and is not changed to the low-potential-side power supply Vss level. is there. That is, the bit lines BLT0 and BLB0 are V
With the ss / 2 level precharged, the word line is selected and the memory cell data is read.

According to the above embodiment, the following operational effects can be obtained.

When the address ADR is input from the outside and the input address ADR is latched by the latch circuit 15 under the control of the timing control circuit 13, the refresh decision circuit 185 refreshes the memory mat corresponding to the input address ADR at present. If it is determined in this determination that the selected mat is being refreshed, the clock generation circuit 182 is determined.
When the generation of the clock CLK in the memory mat is stopped, the refresh operation for the memory mat is stopped, and the mode determination circuit 192 rewrites the register 193, thereby changing the dynamic operation mode up to the nonvolatile operation. The transition to the mode is recorded. In this way, when the memory access from the outside competes with the refresh operation based on the internal clock, the refresh operation is stopped and the memory access from the outside is prioritized. For example, consider the memory access from the CPU 31. In that case, the access waiting time due to the refresh operation is eliminated. That is, the time spent for the refresh operation can be apparently reduced to zero, and the efficiency of memory access by the CPU 31 can be improved, so that the data processing time can be shortened.

Further, when the refresh operation is stopped as described above, in the memory mat which is a storage area related to the stop of the refresh, although the stored information due to the charge accumulation of the capacitor is erased over time, the memory cell is Since it is a ferroelectric substance, the stored information due to polarization remains unerased. Therefore, when the area is read-accessed next time, the memory cell data can be read by switching to the nonvolatile operation mode.

The invention made by the inventor has been specifically described based on the embodiments. However, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist of the invention. No.

For example, in the above embodiment, the management of the storage area for the determination of the non-volatile operation mode and the dynamic operation mode is performed in the memory mat unit, but the management of the storage area is performed in the word line unit. You can In the burst mode of serial access, the data may be managed in a predetermined data size unit.

In the above description, the case where the invention made by the present inventor is mainly applied to the computer system which is the field of application which is the background of the invention has been described, but the present invention is not limited thereto and various data processings are performed. It can be widely applied to devices.

The present invention can be applied under the condition that a memory cell is formed including at least a capacitor made of a ferroelectric thin film.

[0053]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, memory access from the outside,
When the contention with the refresh operation based on the internal clock conflicts, the refresh operation is stopped and the memory access from the outside is prioritized. Therefore, when the memory access from the CPU is taken into consideration, the access wait time due to the refresh operation is eliminated. . In other words, apparently the time spent for refresh operation can be reduced to zero,
As a result, the efficiency of memory access by the CPU can be improved, and the data processing time can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram of a configuration example of a shadow RAM included in a computer system that is an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an overall configuration example of the computer system.

FIG. 3 is a circuit diagram of a configuration example of a memory mat included in the shadow RAM.

FIG. 4 is a circuit diagram showing a configuration example of a peripheral circuit of a memory mat included in the shadow RAM.

FIG. 5 is a flowchart of an auto refresh operation sequence in the shadow RAM.

FIG. 6 is a flowchart of an operation sequence in the shadow RAM when a memory access from the outside and an internal refresh operation conflict with each other.

FIG. 7 is an operation timing chart when the memory mat related to an external memory access is refreshing in the shadow RAM.

FIG. 8 is a timing chart of a memory cell data read operation in a nonvolatile operation mode in the shadow RAM.

FIG. 9 is a timing diagram of a memory cell data read operation in a dynamic operation mode in the shadow RAM.

[Explanation of symbols]

 9-1 to 9-n memory mats 8-1 to 8-n sense amplifier group 10 input / output circuit 11 column decoder 12-1 to 12-n row decoder 13 timing controller 15, 16, 184 latch circuit 17, 186 predecoder 18 Auto Refresh Control Unit 31 CPU 33 Shadow RAM 34 ROM 35 Peripheral Device Control Unit 36 Display System 38 Storage Device 39 Keyboard 181 Timer 182 Clock Generation Circuit 183 Refresh Counter 185 Refresh Judgment Circuit 19 Mode Control Unit 191 Mode Control Circuit 192 Mode Judgment Circuit 193 register 131 capacitor MC memory cell

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasushi Nagashima 2326 Imai, Ome City, Tokyo, Hitachi Device Development Center (72) Inventor Masatoshi Hasegawa 2326 Imai, Ome City, Tokyo Hitachi Device Development Center, Ltd. (72) Inventor Tsuyuki Suzuki 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Hitsuritsu Cho-LS Engineering Co., Ltd. (72) Innovator Yasunobu Aoki 5 Sanmizuhoncho, Kodaira-shi, Tokyo Chome No. 20-1 Hiritsu Super L.S.I. Engineering Co., Ltd. (72) Inventor Seiji Narui 2326 Imai, Ome City, Tokyo Hitachi Device Development Center, Hitachi Ltd.

Claims (5)

[Claims] 1. A plurality of memory cells are formed including a capacitor made of a ferroelectric thin film, and a non-volatile operation mode utilizing the polarization characteristics of the ferroelectric substance and a dynamic operation utilizing the charge storage function of the capacitor. In a method of refreshing a semiconductor memory device capable of realizing a mode, a step of determining whether or not a memory area corresponding to an externally given address for memory access is in a refresh operation, If it is determined, the refresh operation of the storage area is stopped,
And a step of prioritizing a memory access based on an address from the outside, wherein the next memory access to the storage area in which the refresh operation has been stopped is performed in a non-volatile operation mode. 2. A polarization characteristic of the ferroelectric material, comprising a memory cell array divided into a plurality of memory mats, wherein the plurality of memory cells forming the memory mat are formed to include a capacitor made of a ferroelectric thin film. In a refresh method of a semiconductor memory device capable of realizing a non-volatile operation mode utilizing the above and a dynamic operation mode utilizing the charge storage function of the above capacitor, a memory mat corresponding to a refresh address internally generated is operated in the non-volatile manner. Mode or dynamic operation mode, if the dynamic operation mode is determined, the memory mat refresh operation corresponding to the refresh address is performed, and memory access is performed. Memories corresponding to externally given addresses A step of determining whether the memory is in the refresh operation, and when it is determined that the memory is in the refresh operation, the refresh operation of the memory mat is stopped and the memory access based on the address from the outside is prioritized. A refresh control method comprising the step of: performing the next memory access for the memory mat for which the refresh operation has been stopped in a non-volatile operation mode. 3. A non-volatile operation mode in which a plurality of memory cells include a capacitor made of a ferroelectric thin film, and a polarization characteristic of the ferroelectric material, and a dynamic operation in which a charge storage function of the capacitor is used. In a semiconductor memory device capable of realizing the mode, when a memory area corresponding to an address given from the outside for memory access is being refreshed, the refresh operation of the memory area is stopped and the memory access is prioritized. First to do
A semiconductor memory device comprising: means and second means for performing a next memory access to the storage area stopped by the first means in a non-volatile operation mode. 4. A non-volatile operation mode in which a plurality of memory cells are formed to include a capacitor made of a ferroelectric thin film, and a polarization characteristic of the ferroelectric material is used, and a dynamic operation in which a charge storage function of the capacitor is used. In a semiconductor memory device capable of realizing the mode and when a memory area corresponding to an externally given address for memory access is in a refresh operation,
First control means for prioritizing memory access by stopping the refresh operation of the storage area, storage means capable of storing identification information of the storage area for which the refresh operation has been stopped by the first means, and storage of the storage means 2. A semiconductor memory device comprising: second control means for performing the next memory access to the storage area for which the refresh is stopped based on information in a non-volatile operation mode. 5. A data processing device comprising the semiconductor memory device according to claim 3 and a central processing unit capable of accessing the semiconductor memory device.