JPH09251519A - Ic card - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption by using a clock frequency supplied from the outside for the data write/erasure of an EEPROM mounted on an LSI inside an IC card. SOLUTION: This IC card has a CPU 3, LOGIC 5, ROM 7, RAM 9, EEPROM 11, register 13, counter 15 and selector 17. Besides, a power supply line for supplying power (VDD), control line for supplying a reset signal (RST bar), I/O signal line for transmitting/receiving data and ground line (GND) are connected with the outside. Then, an internal oscillator for generating the clock frequency to be used for the writing/erasing operation of the EEPROM 11 is excluded and in place of it, the register 13 and selector 17 are added. With these register 13 and selector 17, the clock frequency optimum for the writing/ erasing operation of the EEPROM 11 can be generated from a rating clock frequency supplied from the outside of an IC card 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC card in which an IC (Integrated Circuit) memory and a microcomputer are embedded in a credit card or the like, and more particularly to an IC card suitable for low power consumption.

[0002]

2. Description of the Related Art Generally, an LSI (Large
An EEPROM (Electrically Erasable) capable of writing and erasing data in the Scale Integrated Circuit
Programmable Read Only Memory) is installed, but its EEPROM is the CPU from outside the IC card.
Writing and erasing are performed by using the clock frequency from an internally built-in oscillator instead of using the rated clock frequency supplied to (Central Processing Unit) and the like.
This is because when the clock frequency of the IC card reader / write in which the IC card is mounted is used, it is assumed that the IC card is mounted in a plurality of IC card reader / writers having different clock frequencies. This is because the erase time changes depending on the clock frequency, which may cause the case where writing / erasing is not surely executed.

However, in recent years, it has been strongly desired to reduce the power consumption of the IC card. Therefore, the internal oscillator, which occupies a considerable part of the power consumption inside the IC card, is removed, and the IC card is externally connected. Attempts have been made to write / erase the EEPROM by using the supplied rated clock frequency. In this case, however, the IC card reader / write in which the IC card is mounted has a constant clock frequency for the reason described above. There was a problem that it was limited to those having.

[0004]

As described above,
In the conventional IC card, an oscillator for writing / erasing data of the EEPROM is provided separately from the clock frequency supplied from the outside in order to be able to be mounted on a plurality of IC card reader / writers having different clock frequencies. It is very difficult to reduce the power consumption of the IC card because it has to be built in.

On the other hand, the oscillator is removed and the EEPRO
When the clock frequency supplied from the outside is used for the data writing / erasing of M, the IC card reader / write in which the IC card is mounted has a constant clock in order to keep the data writing / erasing time of the EEPROM constant. Since it is limited to one having a frequency, it is difficult to give the IC card versatility.

Therefore, the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a clock supplied from the outside to write / erase data of an EEPROM mounted on an LSI inside an IC card. By using the frequency, the power consumption can be reduced, and even if the clock frequency is changed, the data writing / erasing time of the EEPROM can be made constant, which is versatile.
To provide a C card.

[0007]

In order to achieve the above object, the present invention has an IC card which has a microcomputer for performing various calculations and an IC memory for storing data, and for exchanging data with the outside. In the above, it is characterized by further comprising clock generation means for generating an optimum clock for the data write / erase operation of the IC memory from a clock supplied from the outside.

Here, the clock generating means is composed of flip-flops connected in cascade in a plurality of stages, inputs a clock supplied from the outside, and outputs a division ratio signal from each of the plurality of flip-flops. ,
The selector may be configured to select a frequency division ratio signal optimal for the data write / erase operation of the IC memory from the plurality of frequency division ratio signals. From the viewpoint of reducing power consumption, it is preferable to stop the flip-flops connected after the flip-flop that outputs the selected frequency division ratio signal.

Further, in general, the IC card is E
Although it is an EPROM, a flash memory or the like can also be used.

The IC card is a microcomputer (C
PU) performs various calculations and IC memory (EEPROM)
Stores data and exchanges data with the outside. When the power is turned on, the clock frequency is supplied from the outside and the clock information is I
The IC card sets the register based on the information transmitted to the C card, and the selector extracts the optimum frequency division ratio signal from the counter, so that the optimum write / erase of the IC memory is performed from the clock frequency supplied from the outside. You can set the time.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of an IC card according to an embodiment of the present invention.

In FIG. 1, this IC card 1 is a CP
U3, LOGIC5, ROM7, RAM9, E
EPROM 11, register 13, counter 15,
A selector 17, a power supply line for supplying power (V _DD ), a clock supply line for supplying a clock (CLK), a control line for supplying a reset signal (RST bar), and data transmission / reception. I / O signal line and ground line
(GND) is connected to the outside.

FIG. 2 is a block diagram showing an example of the configuration of the counter 15 shown in FIG. 1. The counter 15 is constructed by flip-flops typified by flip-flops 19a, 19b and 19c connected in cascade. All the outputs Q of each flip-flop are connected to the selector 17.

The IC card 1 according to the present embodiment is different from the conventional one in that the internal oscillator for generating the clock frequency for the writing / erasing operation of the EEPROM 11 is removed, and the register 13 and the selector 17 are used instead. In addition, the register 13 and the selector 17 can generate the optimum clock frequency for the writing / erasing operation of the EEPROM 11 from the rated clock frequency supplied from the outside of the IC card 1.

The operation of the IC card having such a structure will be described below.

First, the IC card 1 is an IC card reader /
When the IC card 1 is inserted into a writer (hereinafter, referred to as R / W), a constant voltage of power is supplied from the R / W to the IC card 1 through the power supply line V _DD .

Next, a reset signal is transmitted from the R / W to the IC card 1 via the control line RST bar, and the IC card 1 is initialized.

Next, R / via the clock supply line CLK
The clock is supplied from W to the IC card 1 and I
Information on the clock frequency of the R / W (hereinafter referred to as clock frequency information) is transmitted via the / O signal line.

Next, the CPU 3 obtains the clock frequency information, selects the optimum clock for data writing / erasing of the EEPROM 11, and sets the clock selection information in the register 13.

Next, the CPU 3 transmits the clock selection information set in the register 13 to the selector 17, and selects E from the plurality of frequency division ratio signals transmitted from the counter 15.
Selector 1 best suited for writing / erasing EPROM
7 to select.

Now, the generation of the frequency division ratio signal of the counter 15 will be described with reference to FIG. 2. First, the clock frequency supplied from the outside is 1 that constitutes the counter 15.
It is input to the flip-flop 19a of the stage and its output Q
Is output to the selector 17 as it is, while the output Q bar is the flip-flop 1 of the second stage which constitutes the counter 15.
It is output to 9b. The output Q of the flip-flop 19b, which receives the output Q-bar of the flip-flop 19a, is directly output to the selector 17, while the output Q-bar is output to the third-stage flip-flop 19c of the counter 15. Similarly, the output Q of the flip-flop 19c, which receives the output Q-bar of the flip-flop 19b, is output to the selector 17 as it is, while the output Q-bar is output to the fourth-stage flip-flop (not shown) forming the counter 15. To be done. In this way, the output of each of the plurality of cascade-connected flip-flops, that is, the division ratio signal is output to the selector 17. Note that, for example, when the frequency division ratio signal from the flip-flop 19a is used, the subsequent flip-flops (flip-flops 19b, 19c, etc.) are unnecessary.
In this case, the CPU 3 can stop the operation of the flip-flops that have become unnecessary due to the clock selection information, thereby further reducing the power consumption and enabling stable operation.

By using the frequency division ratio signal thus obtained, the IC card according to the present embodiment can obtain the optimum write / erase time of the built-in EEPROM, so that different clock frequencies can be obtained. It is possible to mount the IC card on a plurality of IC card readers / writers having

Further, since the clock frequency supplied from the outside is used, it is not necessary to have an oscillation circuit inside unlike the conventional IC card, and the power consumption can be reduced accordingly.

[0025]

As described above, according to the IC card of the present invention, the write / erase time of the IC memory can be optimized even when different clock frequencies are supplied from the outside. Since it is not necessary to have an oscillation circuit for writing / erasing the IC memory inside the card, power consumption can be reduced accordingly.

Further, since it can be mounted on a plurality of IC card reader / writers having different clock frequencies, versatility can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of an IC card according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a counter 15 shown in FIG.

[Explanation of symbols]

 1 IC card 3 CPU 5 LOGIC 7 ROM 9 RAM 11 EEPROM 13 register 15 counter 17 selector 19a, 19b, 19c flip-flop

Claims (4)

[Claims] 1. In an IC card having a microcomputer for performing various calculations and an IC memory for storing data, and for exchanging data with the outside, writing data to the IC memory from a clock supplied from the outside. An IC card having a clock generation means for generating a clock optimum for an erase operation. 2. The clock generating means comprises flip-flops connected in cascade in a plurality of stages, inputs a clock supplied from the outside, and outputs a division ratio signal from each of the plurality of flip-flops. 2. The IC card according to claim 1, further comprising a selector that selects a frequency division ratio signal most suitable for a data write / erase operation of the IC memory from the plurality of frequency division ratio signals. 3. The IC card according to claim 2, wherein in the IC card, flip-flops connected after the flip-flop that outputs the selected frequency division ratio signal are stopped. 4. The IC card according to claim 1, 2 or 3, wherein the IC memory is an EEPROM.