JPH09251279A - Driving method of plasma display device and the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ruduce the probability of a failure in an address discharge and to improve display quality by making a display frame for a picture composed of at least one subframe and providing a dormant period for adjusting synchronization, in a maintenance discharge period. SOLUTION: A dormant process is provided to divide the maintenance discharge process of the subframe into two, in the subframe whose maintenance discharge process is longest. In the maintenance discharge period, the second half of the previous subframe has a maintenance discharge α2, at the same time when a trigger signal of Vsync comes. Then, full surface writing and delation and an address discharge are executed and further, the first half has a maintenance discharge α1. After that, a driving sequence is temporarily stopped to put it into the dormant period. When the next Vsync comes, the left second half has the maintenance discharge α2. At this time, (α1+α2) is the same length as a conventional maintenance discharge period. Therefore, the length of the dormant period is changed by the period of the Vsync, to obtain the working of adjusting the synchronization, with respect to the Vsync having a different period.

Description

Detailed Description of the Invention

[0001]

2. Description of the Related Art In recent years, in various display devices, diversification of information to be displayed and installation conditions, large screen and high definition have been remarkable. Therefore, in a display device such as a plasma display panel (hereinafter referred to as PDP), a CRT, an LCD, an EL, a fluorescent display tube, a light emitting diode, etc. used for these, the display quality is improved in order to cope with these fluorescent light. It has been demanded.

Of the above-mentioned display devices, the PDP has been actively developed recently because it has excellent characteristics such as flicker-free, easy to enlarge screen, high brightness and long life. PDPs include a two-electrode type that performs selective discharge (address discharge) and sustain discharge with two electrodes, and a three-electrode type that performs address discharge using a third electrode. In a color PDP that performs gradation display, ultraviolet rays generated by discharge excite a fluorescent substance formed in a discharge cell, but this fluorescent substance is weak against impact of ions, which are positive charges simultaneously generated by discharge. There are drawbacks. In the above-mentioned two-electrode type, since the phosphor directly hits the ions, the life of the phosphor may be shortened. In order to avoid this, a three-electrode structure utilizing surface discharge is generally used in the color PDP. Further, also in this three-electrode type, there is a case where the third electrode is formed on the substrate on which the first and second electrodes for sustaining discharge are arranged, and a case where the third electrode is arranged on the other opposite substrate. Further, even when the above-mentioned three kinds of electrodes are formed on the same substrate, there are cases where the third electrode is arranged on the two electrodes for sustaining discharge, and where the third electrode is arranged below the two electrodes. is there. Further, there are a case where visible light emitted from a phosphor is viewed through the phosphor (transmission type) and a case where reflection from the phosphor is viewed (reflection type). In addition, a cell that performs discharge has a spatial connection with an adjacent cell cut off by a barrier (rib, barrier). This barrier is provided on all four sides so as to surround the discharge cell and is completely sealed, or is provided on only one and the other is disconnected by optimizing the gap (distance) between electrodes. There is.

The present invention can be applied to any of the above-described plasma display panels (PDP).

[0004]

As described above, the present invention can be applied to any structure, but here, a panel in which a third electrode is formed on an opposing substrate different from the substrate of the electrode for sustaining discharge is provided. In the description of the reflection type, the barrier is formed only in the vertical direction (that is, orthogonal to the first electrode and the second electrode and parallel to the third electrode), and a part of the sustain electrode is formed by the transparent electrode. To do.

As the above-mentioned three-electrode / surface-discharge PDP, there is known a PDP whose schematic plan view is shown in FIG. 12 is a schematic sectional view (vertical direction) in one discharge cell of the panel of FIG. 11, and FIG. 13 is also a schematic sectional view in the horizontal direction. In the drawings shown below, the same functional parts are designated by the same reference numerals.

The panel is composed of two glass substrates 21 and 29. The first substrate 21 is provided with a first electrode (X electrode) 12 and a second electrode (Y electrode) 13 which are parallel sustain electrodes, and these electrodes are transparent electrodes 22a and 22b and a bus electrode 23a. 23b. Since the transparent electrode has a role of transmitting the reflected light from the phosphor, it is formed of ITO (transparent conductive film containing indium oxide as a main component) or the like. Further, the bus electrode needs to be formed with low resistance in order to prevent a voltage drop due to electric resistance, and is formed of Cr (chrome) or Cu (copper). In addition, they have a dielectric layer (glass)
24, and a MgO (magnesium oxide) film 25 is formed on the discharge surface as a protective film. In addition, the third electrode (address electrode) 13 is formed on the second substrate 29 facing the first glass substrate 21 in a form orthogonal to the sustain electrodes. A barrier 14 is formed between the address electrodes,
A phosphor 27 having red, green, and blue emission characteristics is formed between the barriers so as to cover the address electrodes. Two glass substrates are assembled so that the ridge of the barrier 14 and the MgO surface 25 are in close contact with each other. The space between the phosphor 27 and the MgO surface 25 is the discharge space 26.

FIG. 14 is a schematic block diagram showing a peripheral circuit for driving the PDP shown in FIGS. 12 to 14. The address electrodes 13-1, 13-2, ... Are connected to the address driver 101 one by one, and the address pulse is applied by the address driver at the time of address discharge. Further, the Y electrodes 11-1, 11-2, ... Are connected to the Y electrode driver 102. Y electrode driver 1
02 is connected to the Y common driver 103, a pulse at the time of address discharge is generated from the Y electrode driver 102, a sustain pulse or the like is generated from the Y common driver 103, and is applied to the Y electrode via the Y electrode driver 102. Is applied. The X electrodes 12 are commonly connected and taken out over all display lines of the panel. The X common driver 104 generates a write pulse, a sustain pulse, and the like. These driver circuits are controlled by the logic unit 1, and the logic unit 1
It is controlled by a synchronizing signal and a display data signal input from the outside of the device. Further, the logic unit 1 is provided with an internal power supply 40 that generates various voltages such as high voltage and negative voltage.
A high voltage controller 41 is provided for controlling application of various voltages generated by the internal power supply 40 to each driver circuit based on a control signal from the. The EPROM 39 is a memory that stores a pattern of a drive waveform and information about the number of sustain pulses, and the logic unit 1 sequentially reads out the data stored in the EPROM 39 and generates various control signals.

The logic unit 1 includes a display data control circuit unit 3
1 and a panel drive control unit 34, the display data control circuit unit 31 further includes a frame memory unit 32 and a frame memory control circuit unit 33, and the panel drive control unit 34 includes a timing generation unit 35. An address driver control unit 36, a scan driver 37, and a common driver control unit 38 are provided.

Gray scale display on the PDP is usually performed by associating each bit of display data with a subframe period and changing the length of the subframe period according to the weighting of the bits. For example, when 256-gradation display is performed, display data is represented by 8 bits, one frame is displayed in eight subframe periods, and each bit data is displayed in each subframe period. The length of the subframe period is 1: 2: 4: 8: 16: 32: 64: 12.
It is eight. The display data supplied from the outside is generally in a format in which the gradation data of each pixel is continuous and cannot be changed to the sub-frame format as it is. Therefore, the display data supplied from the outside is temporarily stored in the frame memory 32. The data is stored, read in the next cycle according to the subframe format, and supplied to the address driver 101. The frame memory control circuit unit 33 controls such an operation based on the timing signal from the timing generation unit 35. The address driver control unit 36, the scan driver 37, and the common driver control unit 38
A control signal for controlling the address driver 101, the scan driver 102, and the X and Y common drivers 103 and 104 is generated based on the data read from the ROM 39. The control signals output from the address driver control unit 36, the scan driver 37, and the common driver control unit 38 are supplied to the address unit 42, the X unit 43, and the Y unit 44 of the high voltage control unit 41, where the internal signals are generated. Various voltages from the power supply 40 are selected and applied to each driver circuit.

FIG. 15 shows the PDP shown in FIGS. 11 to 13.
15 is a waveform diagram showing a conventional method of driving by the circuit shown in FIG. 14, showing one sub-frame period in a so-called conventional "address / sustain discharge period separated type / write address system". In this example, one subframe is divided into a reset period, an address period, and a sustain discharge period. In the reset period, first, all the Y electrodes are set to 0V level, and at the same time, the voltage Vs + V is applied to the X electrodes.
A full write pulse of w (about 330 V) is applied, and discharge is performed in all cells of all display lines regardless of the display state until then. The address electrode potential at this time is
It is about 100 V (Vaw). Next, the potentials of the X electrode and the address electrode become 0 V, the voltage of the wall charge itself exceeds the discharge start voltage in all cells, and the discharge is started. Since there is no potential difference between the electrodes in this discharge, wall charges are not formed, and the space charges self-neutralize and the discharge ends.
This is so-called self-erase discharge. By this self-erasing discharge, the state of all cells in the panel becomes a uniform state without wall charges. This reset period has the effect of putting all the cells in the same state regardless of the lighting state of the previous sub-frame, and is carried out so that the next address (writing) discharge can be stably performed.

Next, in the address period, address discharge is performed line-sequentially in order to turn on / off the cells according to the display data. First, a scan pulse of −VY level (about −150 V) is applied to the Y electrode, and a voltage Va is applied to the address electrode corresponding to the cell that causes the sustain discharge, that is, the cell to be turned on among the address electrodes.
An address pulse of (about 50 V) is selectively applied to cause discharge between the address electrode and the Y electrode of the cell to be lit. Next, this is used as priming (a pilot fire) to immediately shift to the discharge between the X electrode (voltage Vx = 50V) and the Y electrode. The former discharge is called "priming address discharge" and the latter is called "main address discharge". As a result, the amount of wall charges capable of sustaining discharge is accumulated on the MgO surface on the X and Y electrodes of the selected cell on the selected line.

Thereafter, the same operation is sequentially performed on the other display lines, and new display data is written on all the display lines. Then, in the sustain discharge period, the voltage is alternately applied to the Y electrode and the X electrode by Vs (about 180
V) sustain pulse is applied to sustain discharge,
Image display of one subframe is performed. At this time, in order to avoid discharge between the address electrode and the X electrode or the Y electrode,
A voltage Vaw of about 100 V is applied to the address electrodes. In the "address / sustain discharge separate type / write address system", the brightness is determined by the length of the sustain discharge period, that is, the number of sustain discharge pulses.

Specifically, as an example of multi-gradation display, 2
FIG. 16 shows a driving method for displaying 56 gradations. In this example, one frame is divided into four subframes: SF1 to SF4. Then, in these subframes SF1 to SF4, the reset period and the address period have the same length. The length of the sustain discharge period is 1: 2: 4: 8: 16: 32: 6.
The ratio is 4: 128. Therefore, by selecting the sub-frame to be turned on, it is possible to display the difference in brightness of 16 gradations from 0 to 15.

The gradation level that can be displayed is determined by the number of sub-frames. If there are one sub-frame, 2 gradations of luminance can be displayed, and if there are 8 sub-frames, 256 gradations of luminance can be displayed. The display signal supplied to the PDP device is the same signal as that supplied to the CRT or the like, and the vertical synchronization signal Vsyn is used.
c, a horizontal synchronizing signal Hsync, and a data signal synchronized with the dot clock. The PDP device is required to be able to cope with the vertical synchronizing signal Vsync whose cycle is within a predetermined range, like the CRT. Therefore, in the PDP device, as shown in FIG. 16, the sum of the sub-frame periods is set shorter than the one-frame period to provide a pause period for each frame, and the pause period is changed in accordance with the periodic fluctuation of the vertical synchronization signal Vsync. By changing the width, the vertical synchronization signal Vs
It is designed so as to be able to cope with the periodic fluctuation of ync. In the pause period, no signal is applied to the display panel 100 of the PDP device, and the previous state is maintained as it is. Therefore, even if the rest period changes, the display is not affected. On the contrary, the pause period is a period that does not contribute to the display, and therefore, it is desirable that the pause period is as short as possible, and is set as short as possible within a range that can cope with the periodic fluctuation of the vertical synchronizing signal Vsync.

[0015]

In the PDP device, the sustain discharge is performed by using the address discharge as a priming, but there is a probability that the address discharge is not normally performed depending on whether the sustain discharge is performed before the address discharge, That is, the probability of defective address discharge changes. For example, as described above, in the PDP device, one frame forming one screen for gradation display is composed of several sub-frames (hereinafter referred to as SF) having different sustain discharge periods. However, when selecting and lighting cells that have not been lit in the previous SF, the address discharge failure probability is higher than when selecting and lighting cells that are continuously lit from the previous SF. Get higher This is because the previous sustain discharge affects priming.

Table 1 is a table showing how the time after the sustaining lighting is performed affects the probability of defective address discharge.

[0017]

[Table 1]

Table 1 shows SF having the longest sustain discharge period.
6 shows a change in the address discharge failure probability in No. 6. SF6 is arranged at the end of each frame, and in order to make the length of the previous sustain discharge period the same, only SF5 is turned on and SF1 to SF4 are turned on.
Turns off and the position where SF5 is arranged is S in the pattern a.
Immediately before F6, in pattern b, SF1 and SF3 are arranged between SF6 and in pattern c, SF1 and SF3 are arranged between SF6 and SF6.
~ SF4 is arranged. Further, in the pattern d, all SFs other than SF6 of the frame are turned off. Therefore, SF6
The period of non-lighting until it is selected / lighted in is in the order of patterns a, b, c, d. In response to this, the emission intensity of the address discharge of SF6 changes as shown in Table 1, and the probability of defective address discharge increases in the order of patterns a, b, c, d. That is, it can be said that the longer the time from the sustain discharge performed before that, the lower the emission intensity of the address discharge and the higher the probability of defective address discharge.

Therefore, when 6 SFs are provided for multi-gradation display, when SF 6 and SF 5 before it are turned on, S
As F5 moves away from SF6 in time, the priming effect of the sustain discharge of SF5 is not sufficiently given to the address discharge of SF6, and the probability of defective address discharge increases. If the address discharge fails, a problem occurs such that the lit cell blinks and the display is not normally performed.

Table 1 shows how the time after the sustain discharge for lighting affects the probability of defective address discharge, but the time after the sustain discharge for lighting is the same. However, the length of the sustain discharge period affects the probability of defective address discharge. Table 2 is a table showing how the length of the previous sustain discharge period affects the address discharge failure probability.

[0021]

[Table 2]

Table 2 also shows that SF has the longest sustain discharge period.
6 shows a change in the address discharge failure probability in No. 6. SF6 is arranged at the end of each frame, in pattern e, SF5 is arranged immediately before that and only SF5 is lit, in pattern f, SF3 is arranged immediately before that and only SF3 is lit, and in pattern g, immediately before that. SF1 is arranged and only SF1 is turned on, and in pattern h, all SFs are turned off. Therefore, the non-lighting period until selection / lighting in SF6 is the same, and the length of the sustain discharge period that is lighted before that is
The patterns are e, f, g, and h in this order. In response, S
The emission intensity of the address discharge of F6 changes as shown in Table 2,
The probability of defective address discharge increases in the order of patterns a, b, c, and d. That is, it can be said that the emission intensity of the address discharge decreases and the probability of defective address discharge increases as the period of the sustain discharge performed immediately before decreases.

Therefore, when 6 SFs are provided for multi-gradation display, when the SF 6 and the SF before it are turned on, as the sustain discharge pulse number of the immediately preceding SF becomes smaller, the sustain discharge of the immediately preceding SF becomes smaller. The priming effect due to is not sufficiently given to the address discharge of SF6, and the probability of address discharge failure increases. As shown in FIG. 16, a pause period for adjusting the synchronization is provided in one frame. Consider the influence of the pause period on the address discharge failure probability of each SF.

FIG. 17 shows the case where there is one subframe,
It is a figure which shows the time from the end of the sustain discharge period in the previous frame (frame 1) to the address discharge period of the next frame (frame 2). Frame 1 as shown
In the period from the end of the sustain discharge period to the address discharge period of frame 2 includes a pause period, the time from the end of the sustain discharge period to the address discharge period may be longer by that amount. I understand.

When one frame is composed of a plurality of sub-frames, the influence of such defective address discharge is greatest in the sub-frame having the longest sustain discharge period, and particularly in the longest sustain discharge period. It is necessary to reduce the probability of defective address discharge in the subframe. The present invention has been made in view of the above problems, and it is possible to improve the display quality by reducing the probability of defective address discharge, particularly the probability of defective address discharge in a subframe having the longest sustain discharge period. To aim.

[0026]

FIG. 1 is a diagram for explaining the principle of the present invention. As shown in FIG. 1, in the method of driving a plasma display apparatus and the plasma display apparatus of the present invention, a display frame of one screen is composed of at least one subframe, and a pause period for adjusting synchronization is maintained and a sustain period is maintained. It is characterized in that it is provided inside. FIG. 1 shows a case where a display frame of one screen is composed of one subframe, and the subframe corresponds to the display frame of one screen. In FIG. 1, frame 1 and frame 2 each represent two consecutive display frames.

That is, in the driving method of the plasma display device according to the first aspect of the present invention, the display frame of one screen is composed of at least one subframe, and each subframe displays a plurality of cells of the plasma display panel. Addressing step to set to the state corresponding to the data, sustaining and discharging step to apply sustaining discharge pulse to multiple cells to make multiple cells emit light according to the set state, full writing and full surface before addressing step A reset process for self-erasing is provided, and for each display frame of one screen, the sum of the periods of the subframes forming the display frame of one screen is subtracted from the vertical synchronization period indicated by the vertical synchronization signal applied from the outside. Hold the state that no signal is applied to the plasma display panel so as not to change the state of multiple cells for a time A method of driving a plasma display device and a stop step, pause step, characterized in that provided in the sustain discharge step of any of the sub-frame.

It is desirable that the subframe in which the pause process is provided is the subframe having the longest sustain discharge process. The pause process is provided within the longest subframe of the sustain discharge process so as to divide the sustain discharge process of the subframe into two, and the number of sustain discharge pulses of the divided two sustain discharge processes is not zero. To do.

The sum of the numbers of sustain discharge pulses of the two sustain discharge steps of the longest subframe of the sustain discharge step divided by the pause step is a predetermined value with respect to the number of sustain discharge pulses of the sustain discharge steps of other subframes. It is a ratio. The number of sustain discharge pulses of the two sustain discharge steps of the longest subframe of the sustain discharge step divided by the rest step is the number of sustain discharge pulses of the subsequent sustain discharge step, which is the number of sustain discharge pulses of the preceding sustain discharge step. Set to more.

In the address process, the pulse width of the address discharge pulse applied to set the plurality of cells in a state corresponding to the display data is set according to the address discharge defect rate. The pulse width of the address discharge pulse is 8
It is μs or more. The longest subframe of the sustain discharge process is arranged next to the longest subframe of the sustain discharge process.

The longest sub-frame of the sustain discharge process is arranged next to the next long sub-frame of the sustain discharge process. As is clear from comparison with the conventional example of FIG. 17, in the driving method of the plasma display device and the plasma display device of the present invention, as shown in FIG. 1, a pause period is provided during the sustain discharge period. The effect of priming that the sustain discharge has on the next address discharge becomes stronger as the time from the sustain discharge to the address discharge becomes shorter,
Address discharge failure can be reduced. In the case of a driving sequence having a long quiescent period, in the conventional example as shown in FIG. 17, the interval between the sustain discharge period and the address discharge period disappears due to the quiescent period, so the priming effect becomes weak. On the other hand, in the driving method and device of the present invention, since the pause period is provided during the sustain discharge period, the pause period does not affect the time from the end of the sustain discharge period to the next address period, and the sustain discharge is performed. The interval between the period and the address discharge period is shortened accordingly. Therefore, the priming effect for the next address discharge by the previous sustain discharge is increased, and the address discharge failure is prevented or reduced. The discharge is interrupted in the sustain discharge period in which the idle period is provided, but the idle period does not cause discharge failure.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION A PDP apparatus according to an embodiment of the present invention is
Since it has a configuration similar to the configuration shown in FIG. 14 and only the configuration of the panel drive control unit 34 is different, the same parts as the conventional one will be briefly described. All information regarding the drive waveforms in this embodiment is a rewritable memory (EPROM).
It is stored in 39. The stored information is information indicating the drive waveform and information indicating the number of sustain discharge pulses.
In order to reduce the storage capacity, data indicating the same drive waveform is repeatedly read in the portion where the same waveform is repeated (address pulse and sustain discharge pulse).

When the Vsync trigger signal is input to the panel drive control unit 34, the panel drive control unit 34 will read the ROM.
The reading of the data of 39 is started. The address driver control unit 36, the scan driver control unit 37, and the common driver control unit 38 of the panel drive control unit 34 generate a control signal according to the data of the ROM 39 and output it to the high voltage control unit 41. Various voltages necessary for driving are supplied from the internal power supply 40 to the high voltage control unit 41, and the output driver of the high voltage pulse provided inside is controlled according to the control signal. The high-voltage pulse output from this is supplied to each driver.

FIG. 2 is a block diagram showing the configuration of the panel drive controller 34 in the first embodiment, and FIG. 3 shows the arrangement of the idle periods in the first embodiment. As shown in FIG. 3, the number of subframes is one in the first embodiment. In FIG. 2, the Y counter 52, the comparison circuit 53, and the Y electrode number register 54 detect that the same portion of the waveform ROM 39 is repeatedly read by a predetermined number in order to generate a predetermined number of address pulses in the address period. It is a part. The up counter 55, the comparison circuit 56, and the sustain discharge wave number register 57 generate the predetermined number of sustain discharge pulses in the first half of the sustain discharge periods of the two divided parts, so that the same portion of the waveform ROM 39 is predetermined. This is a part for detecting that the data is repeatedly read. Similarly, the up-counter 58, the comparison circuit 59, and the sustain discharge wave number register 57 generate the predetermined number of sustain discharge pulses in the latter half of the two divided sustain discharge periods.
This is a part for detecting that the same part of 39 is repeatedly read by a predetermined number. The idle period control circuit 61 is a part that controls the idle period.

The Y counter 52 is cleared to zero by receiving the reset signal. The Y counter 52 counts the scan lines at that time and outputs the count result to the comparison circuit 53. The comparison circuit 53 compares the input value from the Y counter 52 with the preset number of Y electrodes stored in the Y electrode number register 54, and if they are equal, the waveform ROM control circuit 51 is sent to the address period. The end signal of is output.

Next, in the first half of the sustain discharge period,
The up counter 55 is cleared to zero by receiving the reset signal. The up counter 55 counts the number of sustain discharge waves at that time and outputs the count result to the comparison circuit 56. The comparator circuit 56 compares the input value from the up counter 55 with the preset sustain discharge wave number stored in the sustain discharge wave number register 57, and if both are equal, the waveform ROM control circuit 5
For 1, the end signal of the first half of the sustain discharge period is output.

In the pause period, a reset signal is input from the timing generator to the pause period control circuit 61, and the pause period control circuit 61 outputs a signal indicating the pause period to the waveform ROM control circuit 51. When Vsync is input to the pause period control circuit 61, the pause period control circuit 61 stops outputting the signal indicating the pause period, whereby the pause period ends.

When the second half sustain discharge period is finally entered, the same control as in the first half sustain discharge period is performed. Here, FIG.
Compare with the conventional driving method shown in. In the conventional driving method, after a Vsync trigger signal arrives, at the same time when full-scale writing and erasing, address discharge, and sustain discharge are performed, a pause period in which a drive waveform is not output until the next Vsync comes is inserted.

On the other hand, in the sustain discharge period of this embodiment shown in FIG. 3, at the same time when the Vsync trigger signal arrives, the sustain discharge α2 in the latter half of the previous SF is performed, and then the whole area write / erase and address discharge are performed. Perform the first half sustain discharge α1
After that, the drive sequence is temporarily stopped, the rest period is entered, and the second half sustain discharge α2 left when the next Vsync comes is performed. Here, α1 + α2 has the same length as the conventional sustain discharge period. Therefore, the length of the quiescent period changes depending on the cycle of Vsync, and the operation for adjusting the synchronization with respect to Vsync having a different cycle is performed as in the conventional case.

In the first embodiment, the number of subframes is 1.
However, in the second embodiment, an example in which there are a plurality of subframes will be described. In the second embodiment, the circuit of FIG. 2 is used as in the first embodiment, and further a circuit for controlling the number of subframes in one frame shown in FIG. 4 is further provided. Further, FIG. 5 is a diagram showing the arrangement of the idle periods in the second embodiment. As shown in FIG. 5, the subframe in which the idle period is inserted in the sustain discharge period is the last subframe.

The operation in each sub-frame in the second embodiment is basically the same as that in the first embodiment, and in the SF in which the idle period is inserted within the sustain discharge period, the idle period control is performed at the time of entering the idle period. The difference is that the circuit 61 is operated, but in the SF in which the idle period is not inserted in the sustain discharge period, the idle period control circuit 61 is not operated. Further, in the circuit shown in FIG. 4, when Vsync is input, the SF counter 7
1 is cleared, and the SF counter 71 starts counting subframes. The count value of the SF counter 71 is output to the comparison circuit 72, and is compared with the number of subframes forming one frame stored in the SF number register 73.
The SF counter 71 counts the number of subframes forming one frame, and when the two values match, the comparison circuit 72
Outputs a frame end signal indicating that the frame has ended.

As shown in FIG. 5, Vsy is used in the second embodiment as well.
At the same time when the trigger signal of nc comes, the sustain discharge α2 in the latter half of the previous SF is performed. Therefore, the length of the rest period is Vsync.
The function of adjusting the synchronization for Vsync having a different cycle is performed as in the conventional case. Also in this case, α1 + α2 is equal to the conventional sustain discharge period of SFn.

When one frame is composed of a plurality of subframes, the subframe in which the idle period is inserted need not be the last subframe of the frame. Therefore, an example in which a pause period is inserted in a subframe other than the last subframe is shown in the third embodiment. In the third embodiment, the circuits of FIGS. 2 and 4 are used as in the first embodiment, and further, the idle period control circuit shown in FIG. 6 is used. Moreover, FIG.
It is a figure which shows arrangement | positioning of the idle period in an Example.

As shown in FIG. 7, in the third embodiment, the entire surface write and erase, the address discharge, and the sustain discharge are sequentially performed in the SFs other than the SF (nk) of the intermediate SF. Middle S
Only in F (n−k), when the first half sustain discharge α1 is performed, the rest period is entered, and then the remaining second half sustain discharge α2 is performed. Since the operations of the circuits of FIGS. 2 and 4 are the same, the description thereof is omitted here.

In the operation of the circuit of FIG. 6, one frame is composed of four sub-frames, and the four sub-frames are SF4, SF3, in descending order of luminance (longest sustaining discharge period).
The case of SF2 and SF1 will be described. Vsyn
c is input, and the operation as described above is started from SF1. When the operations for all SFs are completed, the idle period a is entered. Then, the pause counter 81 is operated to count the pause period. When Vsync is input again, the value N of the pause counter 81 is stored in the register 82. Since no correction is made at this point, N is directly input to the comparator 83.

At the same time, the driving of SF1 of the next frame is started, and the driving of SF2 is similarly performed. Then, in SF3 in which the rest period is inserted, the sustain discharge having the predetermined first half sustain discharge wave number is performed. Then, the rest period b is entered.
Then, the pause counter 85 counts the pause period. If the value is input to the comparator A and becomes equal to the value N input from the adder / subtractor circuit 83, the comparator 84 reads the ROM.
The idle period end signal is output to the control circuit 51, and the sustain discharge in the latter half of SF3 is executed.

The next Vsync is scheduled to be input almost at the same time when the last sustain discharge of SF4 is completed. If there is no deviation in this schedule, the operation is performed as it is. However, if Vsync deviates from the time point when the last sustain discharge of SF4 ends, deviation from the cycle of Vsync occurs in the current idle period, and therefore the following operation is performed. . After the end of the last sustain discharge of SF4, the Vsync counter 86 counts the period a shown in the figure until Vsync is entered. On the other hand, if the drive waveform does not end even though Vsync is input, the drive counter 87 counts the period b in the drawing. Since the values of both a and b correspond to the deviation when Vsync fluctuates, the deviation is input to the adder / subtractor circuit 83 via the comparator 88. N ± L is input to the comparator 84 as a value corrected for the length N of the idle period counted at the beginning, and the idle period is further determined at the next Vsync based on this value. Thus, Vsy
Even when a deviation from nc occurs, it is possible to operate while maintaining the length of the idle period b.

As described above, in the first to third embodiments, since the pause period is not added to the period from the previous sustain discharge to the next address discharge, this period can be shortened and the previous period can be shortened. The priming effect of the sustain discharge of SF on the address discharge can be increased. When performing multi-gradation display, the ratio of the length of the sustain discharge period is 1:
The number of sustain discharge waveforms is determined so as to have a constant ratio of 2: 4: ..., and different gradations of luminance are expressed by the difference in the number of sustain discharge waveforms. Therefore, in order to perform accurate gradation display, Even if a rest period is inserted in the sustain discharge period, the total number of divided sustain discharge waveforms must be equal before and after the division. Therefore, the sum of the sustain discharge waveform numbers α1 and α2 in the two sustain discharge periods divided by the idle period is equal to the sustain discharge waveform number α in the sustain discharge period before the division.

Since the number of sustain discharge waveforms α2 in the latter half of the divided sustain discharge period gives a priming effect to the next address discharge, in order to increase the priming effect, α2 should be as large as possible. Good. That is, it is desirable to set α1 <α2. However, if the number of sustain discharge waveforms α1 in the first half is set to zero, the pause period after the address discharge is entered, and the time from the address discharge to the sustain discharge becomes long. Since the sustain discharge may not be performed, it is not desirable to set the sustain discharge waveform number α1 in the first half to zero.

As described above, when the pause period for synchronization adjustment is set within the sustain discharge period, the pause period does not impair the priming effect and the address discharge failure probability can be reduced, but the address discharge failure probability is different. It is also affected by the factors of. One of the factors is the address discharge pulse width. FIG. 8 is a diagram showing the relationship between the address discharge pulse width and the address discharge failure probability. As is clear from the figure,
It can be seen that the probability of defective address discharge decreases as the width of the address discharge pulse increases. And
It can be seen that when the address discharge pulse width exceeds a constant value, Ts in FIG. 8, the address discharge failure probability becomes a substantially constant value and is saturated. Therefore, even when the driving method of the plasma display device in which the pause period is provided during the sustain discharge period is performed, the address discharge failure probability is reduced by setting the address discharge pulse width to a sufficient value Ts considering the address discharge failure probability. can do.

When a plurality of SFs are provided in one frame, the visual display quality is most deteriorated due to defective address discharge in the SF having the maximum brightness. Therefore, in order to cause sufficient discharge to select and light the address discharge of the SF having the maximum brightness (longest sustain discharge period), the sustain discharge of the preceding SF should be as strong as possible,
That is, it is desirable that the SF has a large number of sustain discharge pulses. Therefore, as is clear from the example in Table 2, immediately before the SF having the maximum brightness, the S having the next largest brightness is displayed.
By providing F, that is, SF having a large priming effect, the intensity of the address discharge light emission of the SF having the maximum brightness becomes strong, and the deterioration of the visual display quality due to the defective address discharge can be reduced.

The above arrangement is also effective when the rest period is arranged during the sustain discharge period. FIG. 9 is a diagram showing an arrangement of idle periods in the fourth embodiment. As shown in FIG. 9, in the fourth embodiment, the SF having the longest sustain discharge period is
SF5 having a long sustain discharge period is arranged before 6
A rest period is provided in the sustain discharge period of 6. As a result, the priming effect of the sustain discharge period of the relatively large SF5 reduces the address discharge failure of the SF6, which greatly contributes to the display quality, so that the display quality can be improved.

FIG. 10 is a diagram showing the arrangement of idle periods in the fifth embodiment. In the fifth embodiment, SF5 having the longest sustain discharge period is arranged after SF6 having the longest sustain discharge period, and the idle period is provided in the sustain discharge period of SF6. In order to improve the display quality, it is necessary to reduce the address discharge failure not only in the SF having the maximum brightness but also in the SF having a relatively large brightness. In the fifth embodiment, the priming effect of the SF having the maximum brightness is effectively utilized. Then, the deterioration of the visual display quality due to the defective address discharge of SF having the next highest brightness is reduced.

[0054]

In the prior art, since the pause period provided for synchronization adjustment lengthens the time from the sustain discharge of the previous subframe to the address discharge of the next subframe, the address discharge failure can be sufficiently reduced. However, according to the present invention, since the idle period does not affect the time from the sustain discharge of the previous subframe to the address discharge of the next subframe, it is possible to prevent or mitigate the address discharge failure. The display quality of can be improved.
Further, the present invention is particularly effective for a PDP device having a small number of subframes and a long idle period. Moreover, the present invention is
Since it can be performed by only changing the contents of the ROM storing the drive waveform and a slight change in the panel drive control unit, it can be said that there is almost no increase in cost over the conventional example.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block configuration diagram showing a part (control within a subframe) of a panel drive control unit of the first embodiment.

FIG. 3 is a diagram showing an arrangement of idle periods according to the first embodiment.

FIG. 4 is a diagram showing a part (control of the number of subframes) of a panel drive control unit of a second embodiment.

FIG. 5 is a diagram showing an arrangement of idle periods according to a second embodiment.

FIG. 6 is a diagram showing a configuration of a pause period control circuit according to a third embodiment.

FIG. 7 is a diagram showing an arrangement of idle periods according to a third embodiment.

FIG. 8 is a diagram showing a relationship between an address discharge pulse width and an address discharge defect rate.

FIG. 9 is a diagram showing an arrangement of longest subframes in the fourth embodiment.

FIG. 10 is a diagram showing an arrangement of longest subframes in the fifth embodiment.

FIG. 11 is a schematic plan view of a three-electrode / surface-discharge type color plasma display.

FIG. 12 is a schematic cross-sectional view of a three-electrode / surface-discharge type color plasma display.

FIG. 13 is another schematic cross-sectional view of a three-electrode / surface-discharge type color plasma display.

FIG. 14 is a block configuration diagram of a peripheral circuit for driving a three-electrode AC type plasma display.

FIG. 15 is a time chart showing a conventional drive waveform of the plasma display device.

FIG. 16 is a diagram showing a subframe structure.

FIG. 17 is a diagram showing a conventional example of an idle period arrangement.

[Explanation of symbols]

 30 ... Logic part 31 ... Display data control circuit part 32 ... Frame memory part 33 ... Frame memory control circuit part 34 ... Panel drive control part 35 ... Timing generation part 36 ... Address driver control part 37 ... Scan driver control part 38 ... Common driver Control unit 39 ... EPROM 40 ... Power supply circuit 41 ... High voltage control unit 61 ... Rest period control circuit 100 ... Plasma display panel 101 ... Address driver 102 ... Y scan driver 103 ... Y driver 104 ... X driver

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Naoki Matsui, 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor, Yoshikazu Kanazawa 1015, Kamikodanaka, Nakahara-ku, Kawasaki, Kanagawa, Fujitsu Limited ( 72) Inventor Keishin Nagaoka 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited

Claims (18)

[Claims] 1. A display frame of one screen is composed of at least one sub-frame, and each sub-frame includes an address step of setting a plurality of cells of a plasma display panel (100) in a state corresponding to display data, A sustain discharge step of applying a sustain discharge pulse to a plurality of cells to cause the plurality of cells to emit light according to a set state; a reset step of performing a full write and a full self erase before the address step; For each display frame of the screen, the states of the plurality of cells are changed by the time obtained by subtracting the sum of the periods of the sub-frames constituting the display frame of one screen from the vertical synchronization period indicated by the vertical synchronization signal applied from the outside. So that the plasma display panel (100) is not applied with a signal. In the driving method for the Zuma display device, the pause step is provided within a sustain discharge step of any subframe so as to divide the sustain discharge step of the subframe into two. Driving method of display device. 2. The driving method of the plasma display device according to claim 1, wherein the pause process is provided in a subframe that is the longest in the sustain discharge process. 3. The pause process is provided within the longest subframe of the sustain discharge process so as to divide the sustain discharge process of the subframe into two, and the two sustain discharge processes are divided. The method of claim 1, wherein the number of sustain discharge pulses is not zero. 4. The sum of the numbers of sustain discharge pulses of the two sustain discharge steps of the subframe that is the longest in the sustain discharge step divided by the pause step is the number of sustain discharge pulses of the sustain discharge steps of other subframes. The driving method of the plasma display device according to claim 3, wherein the ratio is a predetermined ratio with respect to. 5. The sustain discharge pulse number of the two sustain discharge steps of the longest sub-frame of the sustain discharge step divided by the pause step is earlier than the sustain discharge pulse number of the subsequent sustain discharge step. The driving method of the plasma display device according to claim 3, wherein the number of sustain discharge pulses is greater than the number of sustain discharge pulses in the sustain discharge process. 6. The pulse width of an address discharge pulse applied to set the plurality of cells in a state corresponding to display data in the addressing step is set according to an address discharge defect rate. Driving method for plasma display device of the above. 7. The pulse width of the address discharge pulse is
The method for driving the plasma display device according to claim 6, wherein the period is 8 μs or more. 8. The driving method of the plasma display apparatus according to claim 1, wherein the longest sub-frame of the sustain discharge step is arranged next to the next long sub-frame of the sustain discharge step. 9. The driving method of the plasma display apparatus according to claim 1, wherein the longest sub-frame of the sustain discharge step is arranged before the next long sub-frame of the sustain discharge step. 10. A plasma display panel (100) having a plurality of cells for selectively performing discharge light emission, address means (101, 102) for setting the plurality of cells to a state corresponding to display data, and a plurality of the plurality of cells. Sustaining discharge means (103, 104) for applying a sustaining discharge pulse to the cells to cause the plurality of cells to emit light in accordance with a set state, resetting means for performing full writing and full self erasing, and the addressing means ( 101, 102), the sustain discharge means (103, 104), and a drive control means (3) for controlling the reset means, and a display frame of one screen is configured by at least one subframe, and the drive control is performed. The means (3) corresponds to the display data of the plurality of cells by the address means (101, 102) for each subframe. Control to perform writing to set the state, application of the sustain discharge pulse by the sustain discharge means (103, 104), and full write and full self erase by the reset means before the write, For each display frame of one screen,
The plasma display panel is configured so as not to change the states of the plurality of cells for a time period obtained by subtracting the sum of the periods of the subframes forming the display frame of the one screen from the vertical synchronization period indicated by the vertical synchronization signal applied from the outside. In a plasma display device controlled to hold a resting state in which a signal is not applied to (100), the resting state is divided into two sustaining discharge steps in one of the subframes. A plasma display device, which is provided so as to be divided. 11. The plasma display device according to claim 10, wherein the idle state is provided in a subframe having the largest number of sustain discharge pulses applied by the sustain discharge means. 12. The pause state is provided so as to divide the sustain discharge pulse application period into two in the subframe in which the number of applied sustain discharge pulses is the largest, and two divided sustain discharges are provided. The plasma display device of claim 10, wherein the number of sustain discharge pulses in the pulse application period is not zero. 13. The sum of the numbers of sustain discharge pulses in the two sustain discharge pulse application periods of the subframe in which the number of applied sustain discharge pulses divided by the rest state is the largest, and the sum of sustain discharge pulse numbers of other subframes is the sum of the sustain discharge pulses. 13. A predetermined ratio to the number of sustain discharge pulses in the application period.
3. The plasma display device according to 1. 14. The number of sustain discharge pulses in the two sustain discharge pulse application periods of the sub-frame having the largest number of applied sustain discharge pulses divided by the rest state is the number of sustain discharges in the subsequent sustain discharge pulse application period. The plasma display device according to claim 12, wherein the number of pulses is larger than the number of sustain discharge pulses in the previous sustain discharge pulse application period. 15. The pulse width of an address discharge pulse applied to set the plurality of cells to a state corresponding to display data by the address means is set according to an address discharge defect rate. Plasma display device. 16. The plasma display device of claim 15, wherein the pulse width of the address discharge pulse is 8 μs or more. 17. The subframe having the most applied sustain discharge pulses is arranged next to the subframe having the next most applied sustain discharge pulses.
3. The plasma display device according to 1. 18. The subframe having the highest number of applied sustain discharge pulses is arranged before the subframe having the next highest number of applied sustain discharge pulses.
3. The plasma display device according to 1.