JPH09247220A - Automatic frequency control circuit - Google Patents

Automatic frequency control circuit

Info

Publication number
JPH09247220A
JPH09247220A JP6899396A JP6899396A JPH09247220A JP H09247220 A JPH09247220 A JP H09247220A JP 6899396 A JP6899396 A JP 6899396A JP 6899396 A JP6899396 A JP 6899396A JP H09247220 A JPH09247220 A JP H09247220A
Authority
JP
Japan
Prior art keywords
signal
value
circuit
frequency
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6899396A
Other languages
Japanese (ja)
Inventor
Kouki Enomoto
衡貴 榎本
Hisatsugu Kawai
久嗣 川井
Takaya Hoshina
孝也 星名
Kenzo Urabe
健三 占部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kokusai Electric Corp
Original Assignee
Kokusai Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kokusai Electric Corp filed Critical Kokusai Electric Corp
Priority to JP6899396A priority Critical patent/JPH09247220A/en
Publication of JPH09247220A publication Critical patent/JPH09247220A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To make the bit error rate of a reproduced signal small by further reducing the frequency shift between a carrier frequency and a local oscillation frequency when a frequency-modulated received wave is demodulated and detected. SOLUTION: A comparing circuit 3 compares the demodulation output of a demodulating circuit 1 with the output of a decision circuit 2 and outputs its positive/negative sign. When the same positive/negative sign is outputted more than once successively, a digital filter 4 outputs an up signal or down signal to vary the value in a counter 5, and the value is converted by a D/A converter 6 into an analog value, which is used as the control voltage of a VCO 7. A frequency synthesizer 8 supplies a local oscillation signal based upon the output of the VCO 7 to the demodulating circuit.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、周波数変調方式の
無線受信機の復調回路に用いられ、周波数オフセットの
補正機能を有する自動周波数制御(AFC:automatic
frequency control )回路に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a demodulation circuit of a frequency modulation type radio receiver and has an automatic frequency control (AFC: automatic) having a frequency offset correcting function.
frequency control) circuit.

【0002】[0002]

【従来の技術】従来用いられているAFCの構成例を図
2に示す。図において11は局部発振周波数信号を発振
出力する局部発振回路、12は受信信号と局部発振回路
11の発振出力とを入力し、位相検波出力信号を得る検
波回路、13は位相検波出力信号のタイミングに位相同
期した受信シンボルタイミングを出力するデジタルPL
L(DPLL:Degital Phase Locked Loop )、14は
位相検波出力信号を用いて信号の判定を行い、検波出力
信号を得る判定回路、15は判定回路の入力と判定出力
との誤差を計算する加算器、16は誤差の平均値を得る
平均化回路、17は誤差の平均値を積分し位相差誤差を
求める積分回路、18は検波回路12からの位相検波出
力から位相差分誤差を差引き、その値を判定回路14に
入力する加算器である。上記回路では、判定出力が概ね
正しい結果を示す限りにおいて、最終的には判定回路1
4の入出力の差が零になる方向へと自動的に制御が進行
し、周波数オフセットの補正機能AFCを実現してい
る。
2. Description of the Related Art FIG. 2 shows a configuration example of a conventional AFC. In the figure, 11 is a local oscillation circuit that oscillates and outputs a local oscillation frequency signal, 12 is a detection circuit that receives the received signal and the oscillation output of the local oscillation circuit 11, and obtains a phase detection output signal, and 13 is the timing of the phase detection output signal. Digital PL that outputs received symbol timing that is phase-synchronized with
L (DPLL: Digital Phase Locked Loop), 14 is a determination circuit that determines a signal using a phase detection output signal and obtains a detection output signal, and 15 is an adder that calculates an error between the input of the determination circuit and the determination output , 16 is an averaging circuit for obtaining the average value of the errors, 17 is an integrating circuit for obtaining the phase difference error by integrating the average value of the errors, 18 is the phase difference error subtracted from the phase detection output from the detection circuit 12, and its value Is an adder for inputting to the determination circuit 14. In the above circuit, as long as the judgment output shows a substantially correct result, the judgment circuit 1 is finally
The control automatically advances toward the direction where the input / output difference of 4 becomes zero, and the frequency offset correction function AFC is realized.

【0003】[0003]

【発明が解決しようとする課題】しかし、このAFCの
構成では、検波後の出力信号の位相誤差成分を補正する
という方法をとっているため、搬送波周波数と局部発振
周波数との間では、依然として周波数のずれが存在し続
け、大幅な周波数ドリフトが生じた場合、AFCとして
の機能を果たせないという欠点がある。
However, in this AFC configuration, since the phase error component of the output signal after detection is corrected, the frequency is still between the carrier frequency and the local oscillation frequency. However, if the frequency shift continues to occur and a large frequency drift occurs, the AFC function cannot be achieved.

【0004】本発明の目的は、周波数変調された信号を
受信して検波後の出力信号の位相誤差成分から周波数ド
リフトの方向を検出し、自局のVCO(電圧制御発振
器)を直接制御することによって、搬送波周波数と局部
発振周波数とのずれを逐次補正するAFC回路を提供す
ることにある。
An object of the present invention is to receive a frequency-modulated signal, detect the direction of frequency drift from the phase error component of the output signal after detection, and directly control the VCO (voltage controlled oscillator) of the local station. Accordingly, it is an object of the present invention to provide an AFC circuit that sequentially corrects the deviation between the carrier frequency and the local oscillation frequency.

【0005】[0005]

【課題を解決するための手段】本発明の自動周波数制御
回路は、周波数変調された受信信号を局部発振信号によ
り復調,検波してベースバンド信号を再生する復調回路
と、該再生されたベースバンド信号をしきい値によって
判定し復調データを得る判定回路と、前記復調回路から
のベースバンド信号と、前記判定された復調データを理
想データに変換したものとを比較し、その正負符号を出
力する比較回路と、該比較回路から入力される正負符号
が複数回連続して同じときアップ信号又はダウン信号を
出力するデジタルフィルタと、該デジタルフィルタから
入力されるアップ信号又はダウン信号に基づきカウンタ
内の値を変化させ、かつそのカウンタ値をデジタル値と
して出力するアップ/ダウンカウンタと、該デジタル値
をアナログ値に変換するD/A変換器と、該アナログ値
を電圧値に変換する電圧制御発振器と、該電圧制御発振
器からの電圧値に基づいた局部発振周波数の発振出力を
前記復調回路に与える周波数シンセサイザとを備えたこ
とを特徴とするものである。
SUMMARY OF THE INVENTION An automatic frequency control circuit of the present invention comprises a demodulation circuit for demodulating and detecting a frequency-modulated received signal by a local oscillation signal to reproduce a baseband signal, and the reproduced baseband signal. A determination circuit that determines a signal by a threshold value to obtain demodulation data, a baseband signal from the demodulation circuit, and a signal obtained by converting the determined demodulation data to ideal data are compared, and the positive / negative sign is output. A comparator circuit, a digital filter that outputs an up signal or a down signal when the positive and negative signs input from the comparator circuit are the same for a plurality of times in succession, and a counter in the counter based on the up signal or the down signal input from the digital filter. An up / down counter that changes the value and outputs the counter value as a digital value, and the digital value to an analog value. A D / A converter, a voltage controlled oscillator that converts the analog value into a voltage value, and a frequency synthesizer that gives an oscillation output of a local oscillation frequency based on the voltage value from the voltage controlled oscillator to the demodulation circuit. It is characterized by that.

【0006】[0006]

【発明の実施の形態】本発明によるAFC回路の構成例
を図1に示す。図において、1は受信信号を復調検波
し、送信データ(ベースバンド信号)を再生する復調回
路、2は再生されたデータをしきい値によって判定する
判定回路、3は復調回路から送出された再生データと、
判定されたデータを理想データに変換したものとを比較
し、その正負符号を出力する比較回路、4は比較回路3
から入力された正負符号が複数回連続して同じだった場
合アップ信号又はダウン信号を送出するデジタルフィル
タ、5はデジタルフィルタ4から入力されたアップ信号
又はダウン信号に基づきカウンタ内の値を変化させ、か
つそのカウンタ値をデジタル値として送出するアップ/
ダウンカウンタ(up/down カウンタ)、6はデジタル値
をアナログ値に変換するD/A変換器、7はアナログ値
を電圧値に変換するVCO、8はVCOからの電圧値に
基づいて局部発振周波数を発振する周波数シンセサイザ
である。
FIG. 1 shows an example of the configuration of an AFC circuit according to the present invention. In the figure, 1 is a demodulation circuit that demodulates and detects a received signal and reproduces transmission data (baseband signal), 2 is a determination circuit that determines the reproduced data by a threshold value, and 3 is a reproduction that is transmitted from the demodulation circuit Data and
The comparison circuit 4 compares the determined data with the ideal data and outputs the positive / negative sign of the comparison data.
When the positive and negative signs input from are consecutively the same, the digital filter 5 sends out the up signal or the down signal, and 5 changes the value in the counter based on the up signal or the down signal input from the digital filter 4. , And the counter value is sent as a digital value
Down counter (up / down counter), 6 is a D / A converter that converts a digital value into an analog value, 7 is a VCO that converts an analog value into a voltage value, 8 is a local oscillation frequency based on the voltage value from the VCO Is a frequency synthesizer that oscillates.

【0007】[0007]

【作用】復調回路1は、受信信号と周波数シンセサイザ
8より入力された局部発振周波数信号とで、ベースバン
ドデータを再生する。判定回路2は、復調回路1で再生
されたデータを予め決められたしきい値を基に判定し、
復調データを得る。比較回路3は、復調データを、周波
数オフットがまったく無い場合の復調データ、即ち、理
想データに変換し、復調回路1から出力されるベースバ
ンドデータと理想データとの大小を比較し、その結果を
正負符号として出力する。
The demodulation circuit 1 reproduces baseband data from the received signal and the local oscillation frequency signal input from the frequency synthesizer 8. The determination circuit 2 determines the data reproduced by the demodulation circuit 1 based on a predetermined threshold value,
Obtain demodulated data. The comparison circuit 3 converts the demodulation data into demodulation data when there is no frequency offset, that is, ideal data, compares the magnitude of the baseband data output from the demodulation circuit 1 with the ideal data, and compares the result. Output as a plus / minus sign.

【0008】デジタルフィルタ4はビット毎に正負符号
を取り込み、同じ正負符号が複数回連続した場合、アッ
プ信号又はダウン信号を出力する。この場合、連続回数
を少なく設定した場合は、オフセットの発生に敏感に対
応し、連続回数を多く設定した場合は、オフセットの発
生に鈍感になるが、突発的な雑音には影響され難くな
る。
The digital filter 4 takes in a positive / negative code for each bit, and outputs an up signal or a down signal when the same positive / negative code continues a plurality of times. In this case, when the number of consecutive times is set small, it responds to the occurrence of offset sensitively, and when the number of consecutive times is set to be large, it becomes insensitive to the occurrence of offset, but is less susceptible to sudden noise.

【0009】アップ/ダウンカウンタ5内のカウンタ値
には、予め初期値が設定されている。この初期値は周波
数オフセットが全くない場合のアップ/ダウンカウンタ
5の理想出力値である。アップ/ダウンカウンタ5は、
デジタルフィルタ4から入力されたアップ信号又はダウ
ン信号に基づきカウンタ値をその都度更新し、かつその
カウンタ値をデジタル値として送出する。D/A変換器
6はアップ/ダウンカウンタ5から入力されたデジタル
値をアナログ値に変換する。VCO7はアナログ値を電
圧値に変換する。周波数シンセサイザ8は、VCO7か
らの電圧値に基づいて局部発振周波数を発振して出力す
る。本発明による回路では、段階的に検波後の出力信号
の位相誤差成分が零となる方向へと局部発振周波数の制
御が自動的に進行し、周波数オフセットの補正機能AF
Cを実現することができる。
An initial value is set in advance as a counter value in the up / down counter 5. This initial value is an ideal output value of the up / down counter 5 when there is no frequency offset. The up / down counter 5 is
The counter value is updated each time based on the up signal or the down signal input from the digital filter 4, and the counter value is sent out as a digital value. The D / A converter 6 converts the digital value input from the up / down counter 5 into an analog value. The VCO 7 converts an analog value into a voltage value. The frequency synthesizer 8 oscillates and outputs a local oscillation frequency based on the voltage value from the VCO 7. In the circuit according to the present invention, the control of the local oscillation frequency automatically progresses in the direction in which the phase error component of the output signal after the detection becomes stepwise, and the frequency offset correction function AF is performed.
C can be realized.

【0010】検波後の出力信号の位相誤差成分から、周
波数ドリフトの方向を検出して自局のVCOを直接制御
することにより、搬送波周波数の変動に対し、局部発振
周波数が逐次、搬送波周波数に追従し、周波数オフセッ
トが補正されるAFC方式が実現できた。
By detecting the direction of frequency drift from the phase error component of the output signal after detection and directly controlling the VCO of the local station, the local oscillation frequency sequentially follows the carrier frequency with respect to variations in the carrier frequency. However, the AFC method in which the frequency offset is corrected has been realized.

【0011】図3はBER(Bit Errer Rate:誤り率)
静特性であり、本発明の構成に基づいて実機で回路を製
作し、AFC効果を測定したものである。図中の凡例、
「NON AFC」はAFC回路のないもの、「方式
1」は従来技術のAFC回路によるもの、「方式2」は
本発明のAFC回路によるものである。図の縦軸は、送
信データと受信後の復調データとを比較し、その誤り度
合いを百分率で表したもの。横軸は、周波数オフセット
幅(搬送波周波数と局部発振周波数との周波数のずれ)
である。
FIG. 3 shows BER (Bit Errer Rate).
This is a static characteristic, and a circuit was manufactured by an actual machine based on the configuration of the present invention, and the AFC effect was measured. Legend in the figure,
"NON AFC" means that there is no AFC circuit, "method 1" means that the conventional AFC circuit is used, and "method 2" means that the AFC circuit of the present invention is used. The vertical axis of the figure compares the transmission data with the demodulation data after reception, and shows the error degree as a percentage. The horizontal axis shows the frequency offset width (frequency shift between carrier frequency and local oscillation frequency)
It is.

【0012】[0012]

【発明の効果】本発明を実施すれば、従来技術による方
式よりも、格段に安定したAFC効果が得られることが
確認された。
It has been confirmed that, by carrying out the present invention, a remarkably stable AFC effect can be obtained as compared with the method according to the prior art.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例を示すブロック図である。FIG. 1 is a block diagram showing an embodiment of the present invention.

【図2】従来のAFC回路の構成例図である。FIG. 2 is a diagram illustrating a configuration example of a conventional AFC circuit.

【図3】従来方式と本発明による方式とのAFC効果を
比較したBER静特性例である。
FIG. 3 is a BER static characteristic example comparing the AFC effect between the conventional method and the method according to the present invention.

【符号の説明】[Explanation of symbols]

1 復調回路 2 判定回路 3 比較回路 4 デジタルフィルタ 5 アップ/ダウンカウンタ 6 D/A変換器 7 VCO 8 周波数シンセサイザ 11 局部発振回路 12 検波回路 13 DPLL 14 判定回路 15 加算器 16 平均化回路 17 積分回路 18 加算器 DESCRIPTION OF SYMBOLS 1 Demodulation circuit 2 Judgment circuit 3 Comparison circuit 4 Digital filter 5 Up / down counter 6 D / A converter 7 VCO 8 Frequency synthesizer 11 Local oscillation circuit 12 Detection circuit 13 DPLL 14 Judgment circuit 15 Adder 16 Averaging circuit 17 Integration circuit 18 adder

───────────────────────────────────────────────────── フロントページの続き (72)発明者 占部 健三 東京都中野区東中野三丁目14番20号 国際 電気株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kenzo Urabe 3-14-20 Higashi-Nakano, Nakano-ku, Tokyo Kokusai Electric Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 周波数変調された受信信号を局部発振信
号により復調,検波してベースバンド信号を再生する復
調回路と、 該再生されたベースバンド信号をしきい値によって判定
し復調データを得る判定回路と、 前記復調回路からのベースバンド信号と、前記判定され
た復調データを理想データに変換したものとを比較し、
その正負符号を出力する比較回路と、 該比較回路から入力される正負符号が複数回連続して同
じときアップ信号又はダウン信号を出力するデジタルフ
ィルタと、 該デジタルフィルタから入力されるアップ信号又はダウ
ン信号に基づきカウンタ内の値を変化させ、かつそのカ
ウンタ値をデジタル値として出力するアップ/ダウンカ
ウンタと、 該デジタル値をアナログ値に変換するD/A変換器と、 該アナログ値を電圧値に変換する電圧制御発振器と、 該電圧制御発振器からの電圧値に基づいた局部発振周波
数の発振出力を前記復調回路に与える周波数シンセサイ
ザとを備えた自動周波数制御回路。
1. A demodulation circuit for demodulating and detecting a frequency-modulated received signal by a local oscillation signal to reproduce a baseband signal, and a judgment for judging the reproduced baseband signal by a threshold value to obtain demodulated data. A circuit, comparing the baseband signal from the demodulation circuit with the determined demodulated data converted to ideal data,
A comparison circuit that outputs the positive / negative sign, a digital filter that outputs an up signal or a down signal when the positive / negative signs input from the comparison circuit are the same for a plurality of times consecutively, and an up signal or a down signal input from the digital filter. An up / down counter that changes a value in the counter based on a signal and outputs the counter value as a digital value, a D / A converter that converts the digital value into an analog value, and the analog value into a voltage value. An automatic frequency control circuit comprising: a voltage controlled oscillator for converting; and a frequency synthesizer for giving an oscillation output of a local oscillation frequency based on a voltage value from the voltage controlled oscillator to the demodulation circuit.
JP6899396A 1996-03-01 1996-03-01 Automatic frequency control circuit Pending JPH09247220A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6899396A JPH09247220A (en) 1996-03-01 1996-03-01 Automatic frequency control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6899396A JPH09247220A (en) 1996-03-01 1996-03-01 Automatic frequency control circuit

Publications (1)

Publication Number Publication Date
JPH09247220A true JPH09247220A (en) 1997-09-19

Family

ID=13389702

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6899396A Pending JPH09247220A (en) 1996-03-01 1996-03-01 Automatic frequency control circuit

Country Status (1)

Country Link
JP (1) JPH09247220A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7057422B2 (en) 2003-10-30 2006-06-06 Infineon Technologies Ag Comparator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7057422B2 (en) 2003-10-30 2006-06-06 Infineon Technologies Ag Comparator

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