JPH09246487A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To extend the refresh period by making the absolute value of voltage that is given previously to a data line before reading stored information lower than a half of the absolute value of the voltage for the writing information. SOLUTION: A gate oxide film 2 and a gate electrode 3 are formed on a p type well 1 after forming an element separating oxide film 9 on it. A first layer insulating film 4 is formed and a capacitor is completed by forming an accumulating electrode 6, a capacitor insulating film 7 and a plate electrode 8. A data line 14 is formed after forming a second layer insulating film 13. A depletion layer 10 is formed directly under and around the gate oxide film 10 and diffusion layers 11 and 5. With this, the hold time of data is extended and the power consumption of a DRAM can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to an occasional write / read type semiconductor memory device (DRAM) which requires a memory holding operation.

[0002]

2. Description of the Related Art With the spread of portable information devices, market needs for DRAMs with low power consumption are increasing.
Conventional techniques for meeting such market needs will be described below.

In DRAM, 1-bit information is stored in a component called a memory cell. The memory cell consists of one MOS transistor and one capacitor,
The capacitor is composed of a pair of electrodes (a plate electrode and a storage electrode) facing each other with a capacitor insulating film interposed therebetween.
A voltage Vcc or 0 V is applied to the storage electrode according to the information to be stored, and the charge corresponding to each is stored in the capacitor. Also, the plate electrode serves as a reference electrode,
It is always held at a voltage half the write voltage Vcc.

The MOS transistor plays a role of both applying a voltage (Vcc or 0V) to the storage electrode and controlling reading of the stored charge.

The storage electrode is a capacitor insulating film from the plate electrode and is insulated from the Si substrate (well) by a pn junction. However, since a leak current is unavoidable at the pn junction, the accumulated charge is accumulated. It will disappear soon. In order to prevent this, the stored charge is read before it completely disappears, the stored information corresponding to the stored charge is determined, and the voltage corresponding to the stored information is applied again to the storage electrode. It is periodically performed to restore the original amount. This operation is usually called refresh, and the power required for this operation occupies most of the power consumption of the DRAM in the standby state.

Therefore, how to lengthen the refresh cycle is a problem in reducing the power consumption of the DRAM. Further, in order to prevent an increase in power consumption that accompanies the generation change of DRAMs and the improvement in the degree of integration, it is necessary to double the refresh cycle for each generation.

[0007]

One way to lengthen the refresh cycle of a DRAM is to reduce the junction leakage current. Therefore, technological development has been actively conducted to reduce crystal defects that are the source of leakage current,
At present, it has been improved to a level where defects cannot be detected even by using an electron microscope or the like. Therefore, it is expected that it will be difficult to lengthen the refresh cycle by reducing the leak current of the junction in the future, and it is necessary to take measures by device / circuit technology.

[0008]

Taking a memory cell formed in a well having p-type conductivity as an example, first, DR
The principle of reading information from AM will be described. The data line is held at a predetermined positive voltage (precharge voltage) Vi immediately before reading the data, and when the accumulated charge is read to the data line, the potential changes according to the amount. At this time, the potential Vr of the data line after reading is given by Equation 1.

[0009]

## EQU00001 ## Vr = Vi + (Qr-Cs.times.Vi) / (Cs + Cd) (Equation 1) where Qr is the residual accumulated charge amount at the time of reading (the accumulated charge immediately after writing when writing is performed at a voltage of 0V). Cs is a capacitor capacitance, and Cd is a parasitic capacitance associated with the data line. The variation amount ΔV of the data line potential due to the reading is expressed by Equation 2, and whether the stored information is “1” or “0” is detected by detecting whether the variation amount is positive or negative. It is determined whether there is any.

[0010]

[Formula 2] ΔV = Vr−Vi = (Qr−Cs × Vi) / (Cs + Cd) (Formula 2) Since many sense amplifiers are created in one DRAM and there is a difference in detection characteristics between them. , ΔV is “1”
It is necessary not only to correctly take positive and negative values in accordance with the information of "0" and "0" but also to have an absolute value larger than a predetermined value Vt in order to prevent erroneous detection. That is, the residual accumulated charge amounts corresponding to the “1” and “0” states are set to Qr, respectively.
It is necessary for 0 and Qr1 to satisfy the conditions of Equations 3 and 4.

[0011]

(Qr1-Cs × Vi) / (Cs + Cd) ≧ Vt (Equation 3)

[0012]

## EQU00004 ## (Qr0-Cs.times.Vi) / (Cs + Cd) .ltoreq.-Vt (Expression 4) These conditional expressions can also be expressed as in the following Expressions 5 and 6.

[0013]

Qr1 ≧ Cs × Vi + (Cs + Cd) × Vt (Equation 5)

[0014]

[Equation 6] Qr0 ≦ Cs × Vi− (Cs + Cd) × Vt (Equation 6) Immediately after data writing, the accumulated charge amount is Cs ×
Since Vcc (“1” state) and 0 (“0” state), Vi is conventionally set to Vcc / 2 in order to equalize the margins of Qr1 and Qr0 with respect to Vt variation between chips, between wafers or between lots. .

On the other hand, in the present invention, it is more efficient to set Vi so that both margins become equal when the desired time data is held, and how the accumulated charge amount changes with time. We considered whether it would change.

As described above, the value of the accumulated charge fluctuates mainly due to the leak current through the pn junction. by the way,
Since the potential of the Si substrate is always held at the negative potential Vbb, a positive voltage with respect to the Si substrate is applied to the storage electrode regardless of whether Cs × Vcc (> 0) or 0 is stored in the storage electrode. Since it is added, the leak current always flows from the storage electrode to the Si substrate. This means that the accumulated charge amount decreases not only for the “1” state but also for the “0” state as time passes. Therefore, when the time from writing to reading (data holding time) becomes long, Qr1 decreases, and the condition of the equation 5 is not satisfied, and data disappears. On the other hand, Qr0 also decreases, but on the contrary, this makes the establishment of the condition of Expression 6 more reliable.

Therefore, if a larger margin is secured for the residual accumulated charge amount Qr1 in the "1" state, "0" is obtained.
I realized that the data retention time could be extended without causing erroneous state detection. For that purpose, the potential of Vi may be set smaller than the conventional Vcc / 2.

Next, a method of designing the value of Vi will be described. As is clear from Expression 5, the smaller Vi is, the longer the data holding time is. However, when Vi is too small, the condition of Expression 6 is not satisfied, and a problem of erroneous detection of the “0” state occurs. Since Qr0 decreases with time, this can be prevented by satisfying the condition of Expression 6 immediately after writing. From this condition, the conditional expression that should be satisfied by Vi is obtained as shown in Expression 7.

[0019]

[Expression 7] Vi ≧ (1 + Cd / Cs) × Vt (Expression 7) Therefore, if Vi is designed to be as small as possible within the range where Expression 7 holds in all the memory cells of the DRAM,
The data holding time in the "1" state can be made longer than before without causing the false detection of the "0" state.

In order to improve the usability, the voltage V
It is desirable that i is generated internally instead of being supplied from the outside. Further, as described above, it is desirable that Vi is as small as possible in order to make the data retention time longer. However, when the voltage is fixed, variations in shape or the like between chips, between wafers, or between lots in the manufacturing process. Therefore, a memory cell that does not satisfy the condition of Expression 6 may be created.

In order to deal with this, Vi is made variable,
When the erroneous detection of the "0" state occurs, it can be changed to a good product by increasing Vi. On the other hand, when the data retention time does not reach the predetermined standard and the false detection of the “0” state does not occur, the data retention time can be lengthened by decreasing Vi and the data satisfying the standard must be satisfied. You can increase.

The erroneous detection caused by the inappropriate value of Vi is often caused by the fluctuation of the detection sensitivity of the sense amplifier or the parasitic capacitance of the data line. In this case, since the malfunction occurs not for each memory cell but for each data line, it can often be distinguished from the false detection caused by a foreign substance or a crystal defect.

As described above, the DRAM formed in the p-type well
Although the means of the present invention has been described in accordance with the above, it goes without saying that the present invention is also effective for a DRAM formed in an n-type well. In the latter case, Vi is 0V and Vcc.
/ 2, but Vi is decreased (increases the absolute value) for erroneous detection in the "0" state, and Vi is increased (absolute value for erroneous detection in the "1" state. Decrease the value).

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) FIG. 1 shows a DR which is a first embodiment of the present invention.
A sectional view of AM is shown. This example was created as follows.

LOCOS (local oxid
After forming the element isolation oxide film 9 by the ation of silicon) method, the gate oxide film 2 and the gate electrode 3 are formed. Next, after forming the first interlayer insulating film 4 having a connection hole, the storage electrode 6, the capacitor insulating film 7, and the plate electrode 8 are formed to complete the capacitor. Next, after forming the second interlayer insulating film 13 having a connection hole, the data line 14 is formed. The pad electrode 12 in the opening of the second interlayer insulating film 13 was formed at the same time as the storage electrode 6. The diffusion layers 5 and 11 were formed by solid phase diffusion from the storage electrode 6 and the pad electrode 12, respectively. After that, an interlayer insulating film, wiring and a surface protective film (not shown) are formed to complete the DRAM of this embodiment.

The gate oxide film 10 and the diffusion layer 11
A depletion layer 10 is formed immediately under and around 5 and 5. 64M memory cells were formed inside one DRAM. The capacitance of the capacitor is 25 fF on average, and the parasitic capacitance of the data line is 200 fF (Cd / Cs = 8) on average.
The data write voltage Vcc is designed to be 3.6V, and the data line precharge voltage Vi is designed to be 1V. Vi
Is generated by a circuit (not shown) built in the DRAM.

First, the data retention characteristics of all 64M bits were measured according to the usual procedure, and the defective memory cell was replaced with the memory cell previously formed in advance. Then, when the data retention time was measured again, the minimum value was 720 milliseconds. In order to confirm the effect of this embodiment, the precharge voltage is half the Vcc (1.8
When the data retention characteristic was measured as V), the minimum value of the data retention time was 450 milliseconds. The same voltage
(1.8 V) was supplied externally through an electrode specially formed for characteristic evaluation. From this result, it can be seen that the present embodiment has the effect of increasing the data retention time by about 1.6 times that of the conventional technique.

(Embodiment 2) This embodiment is formed in the same manner as in FIG. 1, but differs from Embodiment 1 in that a circuit capable of changing the precharge voltage is incorporated.

First, after replacing the defective memory cell with the precharge voltage of 1 V in the same manner as in Example 1, the data retention time was measured. The minimum value was 440 milliseconds, which was 500 milliseconds of the standard. Was below.

When the distribution of the data retention time among the memory cells was examined, it was found that many of the memory cells connected to the same data line as the memory cell having the minimum data retention time had a short data retention time. Therefore, when the precharge voltage was set to 0.6 V and the measurement was performed again, the minimum value of the data retention time was improved to 520 milliseconds and the standard could be satisfied. The precharge voltage is 0.4V
When the voltage was lowered to 0, some memory cells appeared which caused an erroneous detection in reading the "0" state.

(Embodiment 3) The structure of the DRAM of this embodiment is the same as that of the second embodiment.

First, after replacing the defective memory cell with the precharge voltage of 0.8 V in the same manner as in the first embodiment, the data retention time was measured. As for the detection of the "1" state, the data retention was carried out. False detections did not occur until the time reached 680 ms, which exceeded the standard of 500 ms. However, there was a memory cell that caused an erroneous detection when reading the "0" state. Then, when the precharge voltage was set to 1 V and the measurement was performed again, the erroneous detection of the reading in the “0” state was resolved. At this time, the minimum value of the data retention time is 610.
Although it decreased to milliseconds, it satisfied the standard of 500 milliseconds.

[0033]

According to the present invention, since the data holding time can be lengthened, the power consumption of the DRAM can be reduced. In particular, since it is possible to provide a means for lengthening the data holding time depending on the occurrence status of the data holding failure, there is an effect of relieving the failure which cannot be dealt with by the conventional technique.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

[Explanation of symbols]

1 ... P-type well, 2 ... Gate oxide film, 3 ... Gate electrode,
4 ... First interlayer insulating film, 5, 11 ... Diffusion layer, 6 ... Storage electrode, 7 ... Capacitor insulating film, 8 ... Plate electrode, 9 ... Element isolation oxide film, 10 ... Depletion layer, 12 ... Pad electrode, 13
... second interlayer insulating film, 14 ... data line.

Claims (7)

[Claims] 1. A semiconductor memory device, wherein an absolute value of a voltage applied to a data line in advance when reading stored information is smaller than half an absolute value of a voltage when writing information. 2. An occasional write / read type semiconductor memory device having a built-in circuit for generating a voltage between half the voltage used for writing information and 0V. 3. The semiconductor memory device according to claim 1, wherein the voltage applied to the data line can be changed. 4. The semiconductor memory device according to claim 3, wherein the voltage applied to the data line is changed in accordance with a retention characteristic of stored information. 5. When the information to be stored is converted into the magnitude of the voltage and written in the storage electrode and then read again, an error occurs in the information read again for the voltage having the smaller absolute value. The semiconductor memory device according to claim 4, wherein the absolute value of the voltage applied to the data line is increased. 6. When the information to be stored is converted into the magnitude of the voltage and written in the storage electrode and then read again, an error occurs in the information read again for the voltage having the larger absolute value. The semiconductor memory device according to claim 4, wherein the absolute value of the voltage applied to the data line is reduced in some cases. 7. The semiconductor according to claim 5, wherein the absolute value of the voltage applied to the data line is increased or decreased when an error occurs in the information read again in a plurality of memory cells connected to the same data line. Storage device.