JPH09238059A - Switch circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain a low voltage operation and high output transmission and to make a device small in size by employing specific multi-gate field effect transistors(FET) for the circuit. SOLUTION: This circuit is provided with multi-gate FETs having n-sets of gate electrodes. Let an internal resistance of a signal source connected thereto and a load resistance be R respectively and a maximum voltage amplitude of transmitted power be Vmax , a pinch-off voltage Vp, a withstanding voltage Vr and a drain saturation current IDSS, of the multi-gate FET satisfy relations of equation |Vp-Vr|>Vmax /(2n) and IDSS>Vmax /(2R). For example, the circuit includes the dual gate FETs 10, 20 and gate resistors R1-R4 formed on a GaAs substrate 100, and the FET10 is connected between terminals A, B and the FET20 is connected between terminals A, C. Then the FET10 sends a signal with a power P1 and has a pinch-off voltage Vp1 and the FET20 sends a signal with a power P2 smaller than the power P1 and has a pinch-off voltage Vp2 shallower than the pinch-off voltage Vp2 .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switch circuit device composed of a field effect transistor (FET) formed on a semiconductor substrate.

[0002]

2. Description of the Related Art For example, a transmission / reception apparatus of a microwave communication system includes GaAs capable of high-speed switching operation.
A system switch circuit device is used. FIG. 27 shows MESF
ET (metal-semiconductor field effect transistor; hereinafter FE
FIG. 10 is a circuit diagram illustrating an example of a conventional switch circuit device using a switch circuit (abbreviated as T).

In the switch circuit device of FIG. 27, a FET 30 is connected between terminals A and B, and F is connected between terminals A and C.
ET40 is connected, and FET is connected between terminal B and ground terminal.
70 is connected, and the FET 80 is connected between the terminal C and the ground terminal.
Is connected. The control voltage V _CTL is applied to the gates of the FETs 30 and 80 through gate resistances, respectively, and F
The control voltage / V _CTL is applied to the gates of the ETs 40 and 70 via gate resistances. Control voltage V _CTL , /
V _CTL is a voltage complementary to each other.

For example, when the control voltage V _CTL becomes 0 V and the control voltage / V _CTL becomes -10 V, the FETs 30 and 80 are
Turns on and the FETs 40 and 70 turn off. Thereby,
A signal is transmitted between the terminals A and B. On the other hand, when the control voltage V _CTL becomes −10 V and the control voltage / V _CTL becomes 0 V, the FETs 30 and 80 are turned off and the FETs 40 and 70 are turned on. Thus, a signal is transmitted between the terminals A and C.

[0005]

In order to reduce the size and improve the performance of communication equipment in microwave communication, a switch circuit device capable of low voltage operation and high output transmission is required. In the above switch circuit device,
By connecting a plurality of FETs in series between terminals A and B and between terminals A and C, large power can be turned on / off with low control voltages V _CTL and / V _CTL . That is, it is possible to perform low voltage operation and high output transmission. The inventors of the present invention have derived and reported the conditions for realizing high output transmission without distortion in such a switch circuit device (Shingaku Giho MW95-11 (1995-0).
5)). However, since it is necessary to connect a plurality of FETs in series, there is a problem that the chip size of the switch circuit device becomes large.

When the above switch circuit device is used as an antenna switch, the antenna is connected to the terminal A, the transmitting circuit is connected to the terminal B, and the receiving circuit is connected to the terminal C. In this case, a large amount of power needs to be transmitted between the terminals A and B during transmission, and a minute signal needs to be transmitted between the terminals A and C during reception. Therefore, the present inventors have proposed a switch circuit device using FETs having two types of pinch-off voltages (1993 IEICE Spring Conference Proceedings C-89 and IEEE JOURN.
AL OF SOLID-STATE CIRCUITS, VOL.29, NO.10, OCTOBER 19
94, pp.1262-1269).

On the other hand, the present inventors have reported that a high isolation (insulation degree) can be obtained by adding a chip inductor between the terminals B and C of the switch circuit device (Communication Technical Report ED95). -165, MW95-15
0, ICD95-221 (1996-01)).

However, even if a switch circuit device capable of low-voltage operation and high-output transmission is constructed based on the above technique, it is not possible to reduce the chip size. An object of the present invention is to provide a small-sized switch circuit device capable of low voltage operation and high output transmission.

Another object of the present invention is to provide a small switch circuit device capable of low voltage operation and high output transmission and having excellent input / output power transmission characteristics.

[0010]

Means for Solving the Problems and Effects of the Invention The present inventor has focused on voltage distribution in a multi-gate field effect transistor in order to reduce the size of a switch circuit device,
As a result of various simulations and evaluations, it was found that the voltage distribution in the multi-gate field effect transistor having n gate electrodes can be made equal to the voltage distribution in the series connection of n field effect transistors. Invented the following inventions.

The switch circuit device according to the first invention is n
A multi-gate field effect transistor having a number of gate electrodes is provided. When the values of the internal resistance and the load resistance of the signal source connected to the multi-gate field effect transistor are R, and the maximum voltage amplitude of the power transmitted by the multi-gate field effect transistor is V _max , the multi-gate field effect is obtained. The pinch-off voltage V _P , breakdown voltage V _r, and drain saturation current I _DSS of the transistor satisfy the following expressions (A) and (B).

| V _P −V _r |> V _{max /(2n)...(A} ) I _DSS > V _{max /(2R)...(B} ) In the switch circuit device according to the first invention, When the gate field effect transistor is off, a maximum voltage V _max / (4n) is applied between the gate and the source at one end and between the gate and the drain at the other end. Therefore, by satisfying the expression (A), the gate-source and gate-source of the multi-gate field effect transistor can be satisfied.
The voltage applied between the drains is within the range of the breakdown voltage V _r and the pinch-off voltage V _P, and the multi-gate field effect transistor maintains the complete off state.

When the multi-gate field effect transistor is turned on, the maximum current flowing between the source and drain is V _max / (2R). Therefore, by satisfying the expression (B), the linearity of the output power with respect to the input power is obtained, and the signal transmission without distortion becomes possible.

In this case, as the number n of gate electrodes increases, the maximum voltage V _max / applied between the gate and the source at one end and between the gate and the drain at the other end of the multi-gate field effect transistor. Since (4n) becomes small, the multi-gate field effect transistor can be surely turned on / off even if the control voltage applied to the gate electrode is lowered. Further, since the maximum voltage V _max / (4n) applied between the gate and the source at one end and between the gate and the drain at the other end becomes small, the multi-gate field effect transistor with respect to a large electric power is obtained. Can be maintained in the off state.

Therefore, high power can be turned on and off at a low operating voltage as in the case of using a series connection of n single gate field effect transistors. Moreover, since the multi-gate field effect transistor having n gate electrodes can be formed in a smaller area as compared with the series connection of n single gate field effect transistors, and a low insertion loss can be maintained. The switch circuit device can be downsized while realizing good high frequency characteristics.

Therefore, it is possible to obtain a small and inexpensive switch circuit device capable of low voltage operation and high output transmission. A switch circuit device according to a second aspect of the present invention includes a first multi-gate field effect transistor connected between a common terminal and a first terminal and transmitting a signal of a _first power P ₁ , a common terminal and a first multi-gate field effect transistor. A second multi-gate field effect transistor connected to the second terminal and transmitting a signal of a _second power P ₂ smaller than the first power P _1; Has a first pinch-off voltage V _P1 and the second multi-gate field effect transistor has a second pinch-off voltage V _P2 which is shallower than the first pinch-off voltage V _P1 .

The shallow pinch-off voltage means that the absolute value of the pinch-off voltage is small, and the deep pinch-off voltage means that the absolute value of the pinch-off voltage is large.

In the switch circuit device according to the second aspect of the invention, the first multi-gate field effect transistor transmits a large power signal and the second multi-gate field effect transistor transmits a small power signal.

Since the first multi-gate field effect transistor has a deep pinch-off voltage V, it has a low on-resistance and a large drain saturation current. Therefore, a signal of high power can be transmitted without distortion. on the other hand,
Since the second multi-gate field effect transistor has a shallow pinch-off voltage, it is possible to maintain a complete off state during transmission of a large amount of power by the first multi-gate field effect transistor.

Further, since the signal transmitted by the second multi-gate field effect transistor is small, it is possible to perform signal transmission without distortion even if the pinch-off voltage of the second multi-gate field effect transistor is shallow. At this time, since the power transmitted by the second multi-gate field effect transistor is small, even if the pinch-off voltage of the first multi-gate field effect transistor is deep, the first multi-gate field effect transistor is in a completely off state. Can be maintained.

In particular, the first and second multi-gate field effect transistors achieve a function equivalent to that of a plurality of single-gate field effect transistors connected in series. Therefore, it is possible to reduce the size while maintaining good high frequency characteristics. You can

Therefore, it is possible to obtain a small and inexpensive switch circuit device capable of selectively transmitting high power and low power signals at a low operating voltage without distortion. A switch circuit device according to a third aspect of the present invention is the switch circuit device according to the second aspect, wherein the internal terminal and the load resistance of the signal source connected to the common terminal and the first and second terminals are respectively set. R, the number of gates of the first multi-gate field effect transistor is n ₁ , the number of gates of the second multi-gate field effect transistor is n _2, and the maximum voltage amplitude at the first power P ₁ is V _1max , Second
_Of the first multi-gate field effect transistor, the first pinch-off voltage V _P1 , the withstand voltage V _{r1, the} drain saturation current I _DSS1 and the second multi-gate field effect, where V _2max is the maximum voltage amplitude of the power P ₂ of The second pinch-off voltage V _P2 , breakdown voltage V _r2, and drain saturation current I _DSS2 of the transistor satisfy the following expressions (C), (D), (E), and (F).

_{│V P1} -V _r1 │> V _2max / (2n ₁ ) ... (C) I _DSS1 > V _1max / (2R) ・ ・ ・ (D) _{│V P2-} V _r2 │> V _1max / (2n ₂₎ in the switch circuit device according to _{··· (E) I DSS2> V} 2max / (2R) ··· (F) the third invention, by satisfying the formula (D), first When the multi-gate field effect transistor is turned on, the first multi-gate field effect transistor can transmit the signal of the first power P ₁ without distortion. At this time, by satisfying the expression (E), the second multi-gate field effect transistor can maintain a complete off state with respect to the first power P ₁ . On the other hand, by satisfying the formula (F), the second
When the multi-gate field effect transistor of is turned on, the second
The multi-gate field effect transistor of the second power P ₂
Can be transmitted without distortion. At this time, by satisfying the expression (C), the first multi-gate field effect transistor can maintain a complete off state with respect to the second power P ₂ .

Therefore, it is possible to obtain a small and inexpensive switch circuit device capable of selectively transmitting a signal of high power and a signal of low power at a low operating voltage without distortion and without causing signal leakage.

A switch circuit device according to a fourth invention is the switch circuit device according to the second or third invention, further comprising an inductor connected between the first terminal and the second terminal. It is a thing.

In the switch circuit device according to the fourth aspect of the invention, the inductor connected between the first terminal and the second terminal and the source-drain capacitance of the off-state multi-gate field effect transistor resonate. Causes high isolation in a specific frequency range. Therefore, it is possible to obtain a small and inexpensive switch circuit device capable of selectively transmitting a signal of high power and a signal of low power at a low operating voltage and having high isolation.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION Before describing the embodiments of the present invention, the basic principle of the switch circuit device of the present invention will be described first with reference to FIGS.

FIG. 1 is a circuit diagram of a switch circuit device composed of two single gate FETs. The switch circuit device of FIG. 1 has three terminals A, B and C, a single gate FET 30 is connected between the terminals A and B, and a single gate FET 40 is connected between the terminals A and C. FET
Control voltages V _{CTL and} / V _CTL which are complementary to each other are applied to the gates of 30 and 40 via gate resistors. A signal source SG is connected to the terminal A, and loads are connected to the terminals B and C, respectively. In the figure, Ri represents the internal resistance of the signal source SG, and RL represents the load resistance.

At this point, the FET 30 turns on and the FET 40
Is off. In this case, within the signal source SG
Current flows through the partial resistance Ri, the FET 30, and the load resistance RL.
It is. Electric power input from the signal source SG to the switch circuit device
The force is P and the resistance values of the internal resistance Ri and the load resistance RL
And R respectively, the maximum voltage amplitude V of the signal source SG
_maxIs given by the following equation.

V _max = √ (4R · P) · √2 (1) Usually, the resistance value R is 50Ω. Since the resistance value of the internal resistance Ri and the resistance value of the load resistance RL are equal, the maximum voltage applied to the terminal A is V _max / 2. At this time, FE
T40 so turned off, it becomes the terminal A, the maximum voltage V _{ma x} / 2 that is applied between the C.

FIG. 2 is a schematic sectional view of the FET 40 in the off state. In FIG. 2, P on the GaAs substrate 100
^- layer 107 is formed. An n ⁺⁺ layer 101 serving as a source (or a drain) and an n ⁺⁺ layer 102 serving as a drain (or a source) are formed on the P ⁻ layer 107 at a predetermined interval, and n between the n ⁺⁺ layers 101 and 102 is n. The layer 103 is formed. A gate electrode 104 is formed on the n layer 103. A gate-source capacitance C _gs exists between the gate electrode 104 and the n ⁺⁺ layer 101, and the gate electrode 1
A gate-drain capacitance C _gd exists between 04 and the n ⁺⁺ layer 102, and a source-drain capacitance C _ds exists between the n ⁺⁺ layers 101 and 102.

FIG. 3 shows an equivalent circuit diagram of the FET 40 of FIG. In the FET 40, when the source and the drain have a symmetrical structure with respect to the gate, C _gs = C _gd , and the voltage is equally distributed between the gate and the source and between the gate and the drain. Therefore, the maximum voltage applied between the gate and the source and between the gate and the drain is V _max /
It becomes 4.

Next, FIG. 4 shows four single gate FETs.
It is a circuit diagram of a switch circuit device consisting of. In the switch circuit device of FIG. 4, two single gate FETs 11 and 12 are connected in series between terminals A and B,
Two single gate FETs 21 and 22 are connected between C in series.

At this time, the FETs 11 and 12 are turned on, and the FE
It is assumed that T21 and 22 are off. In this case, since the maximum voltage applied to the terminal A is V _max / 2, the maximum voltage applied between the terminals A and C is also V _max / 2.
Therefore, when the FETs 21 and 22 have the same characteristics, the maximum voltage applied between the source and drain of the FETs 21 and 22 is V _max / 4, respectively.

FIG. 5 is a schematic sectional view of the FETs 21 and 22 in the off state. In FIG. 5, FETs 21 and 22
The structure of each is similar to that of the FET 40 shown in FIG. FET 21 n ^{+ +} layer 102 and FET 22 n ^{+ +}
It is connected to the layer 101 by the metal layer 105. These n ⁺⁺ layers 102 and n ⁺⁺ layers 101 are common n ⁺⁺ layers 1
If replaced with 06, the structure shown in FIG. 6 is obtained. In this structure, the n ⁺⁺ layer 106 serves as the drain (or source) of the FET 21 and the source (or drain) of the FET 22.

FIG. 7 shows an equivalent circuit diagram of the FETs 21 and 22 shown in FIG. In these FETs 21 and 22, when the source and drain have a symmetrical structure with respect to the gate, C _gs = C _gd , and the maximum voltage applied between the gate and the source and between the gate and the drain is V, respectively.
It becomes _max / 8.

When the n ⁺⁺ layer 106 is removed in the structure of FIG. 6, the structure of the dual gate FET 20 shown in FIG. 8 is obtained. In the dual gate FET 20 of FIG.
P on As substrate 100 ^- on the layer 107, n ⁺⁺ layer 102 serving as a source (or drain) and a n ⁺⁺ layer 101 and the drain (or source) is formed at a predetermined distance, n ⁺⁺ layer An n layer 103 is formed between 101 and 102. Two gate electrodes 104 are formed on the n layer 103.

FIG. 9 shows an equivalent circuit diagram of the FET 20 shown in FIG. In this FET 20, the capacitance between the two gates is the gate-drain capacitance C of the FET 21 shown in FIG.
The combined capacitance of _gd and the gate-source capacitance C _gs of the FET 22 is C _gs / 2.

Since the maximum voltage applied between the source and the drain is V _max / 2, the maximum voltage applied between one gate and the source and between the other gate and the drain is V _max /, respectively. 8 and the maximum voltage applied between the two gates is V _max / 4.

As described above, it is understood that similar voltage distribution occurs even when two single gate FETs connected in series are replaced by one dual gate FET. FIG. 10 is a circuit diagram of a switch circuit device including two dual gate FETs. In the switch circuit device of FIG. 10, a dual gate FET1 is provided between terminals A and B.
0 is connected, and dual gate FET2 is connected between terminals A and C.
0 is connected. The control voltage V _{CTL is} applied to the two gates of the FET 10 via the gate resistance,
Control voltage / V to the two gates of
_CTL is given.

At this time, the FET 10 is turned on and the FET 20
Is off. In this case, since the maximum voltage applied to the terminal A is V _max / 2, as described with reference to FIG. 9, between the one gate and the source of the FET 20 and the other gate and the drain of the FET 20. The maximum voltage applied is V _max / 8, respectively.

Therefore, the two single gate FETs 11 and 12 in the switch circuit device of FIG. 4 are replaced with one dual gate FET 10, and the two single gate FETs 21 and 22 are replaced with one dual gate FE.
By replacing with T20, it becomes possible to reduce the size of the switch circuit device while maintaining the same voltage distribution.

Next, the characteristics of the dual gate FETs 10 and 20 in the switch circuit device of FIG. 10 will be described in comparison with the characteristics of the single gate FETs 30 and 40 of the switch circuit device of FIG. Figure 11 is the drain current I _D in the FET - a diagram showing the gate voltage V _G characteristics. To turn off the FET, the gate voltage V _G
Must be set lower than the pinch-off voltage V _P.

In the switch circuit device of FIG. 1, the maximum voltage applied between the gate and the source of the FET 40 in the off state is V _max / 4. Therefore, when the predetermined off-time control voltage / V _CTL is applied, the FE
In order to maintain T40 in the OFF state, as shown in FIG. 11A, the pinch-off voltage V _P is shallower (close to 0 V) than the value obtained by adding V _max / 4 to the control voltage / V _CTL during OFF. )It is necessary.

On the other hand, in the switch circuit device of FIG. 10, the maximum voltage applied between the one gate and the source of the FET 20 in the off state is V _max / 8. Therefore, in order to maintain the OFF state of the FET 20 when the predetermined off-time control voltage / V _CTL is applied, as shown in FIG. 11B, the off-time control voltage / V _CTL is set.
_The pinch-off voltage V _P is higher than the value obtained by adding V _max / 8 to _CTL.
Is required to be shallow (close to 0V).

Here, the relationship between the pinch-off voltage and the DC characteristic of the FET will be described. FIG. 12 shows the pinch-off voltage V
_P = -2.4V of the FET and the pinch-off voltage V _P = -
Drain current I _D −source of 0.8 V FET
It is a diagram showing the drain voltage V _DS characteristics. Gate width W _G
Is 1000 μm and the gate voltage V _G is 0V.

The source in the linear region of this characteristic curve
The ratio of the drain voltage V _DS and drain current I _D corresponds to the on-resistance, the drain current I _D in the saturation region corresponds to the drain saturation current I _DSS. As can be seen from FIG. 12, the deeper the pinch-off voltage V _P , the smaller the on-resistance.
The drain saturation current I _DSS is large. Therefore, it can be seen that the deeper the pinch-off voltage V _{P, the} better the direct current characteristic can be obtained.

Here, consider the case where the operating voltage is low. For example, the control voltage / V _CTL when off is set to -2.4V. The input power from the signal source SG is 22 dBm (= 158
mW), the maximum voltage amplitude V of the signal source SG
_max becomes 7.9V (= about 8V).

In this case, in the switch circuit device of FIG. 1, the gate-source voltage of the FET 40 is V _max / 4.
= 2V. In order to maintain the FET 40 in the off state, the pinch-off voltage V _P needs to be shallower than −0.4V. That is, as the FET 40, -0.4V
It is necessary to use an FET having a shallower pinch-off voltage V _P. In this way, the FE having a shallow pinch-off voltage V _P
T is difficult to make. Even if it can be manufactured, the on-resistance is high, the drain saturation current is small, and the direct current characteristics are poor.

On the other hand, in the switch circuit device of FIG. 10, the maximum voltage applied between the one gate and the source of the FET 20 is V _max / 8 = 1V. In order to maintain the FET 20 in the off state, the pinch-off voltage V _P is −
It needs to be shallower than 1.4V. That is, FE
T20 is shallower than -1.4V pinch-off voltage V
An FET having _P may be used.

As described above, in the switch circuit device of FIG. 10, an FET having a deeper pinch-off voltage V _P can be used as compared with the switch circuit device of FIG. Therefore, good DC characteristics can be obtained even if the operating voltage is lowered.
Further, when the switch circuit device of FIG. 10 is compared with the switch circuit device of FIG. 4, the number of FETs is reduced, so that the size can be reduced.

From the above results, by constructing the switch circuit device with the multi-gate FET, it is possible to realize a low voltage operation and a high output transmission and also to reduce the size. FIG.
FIG. 3 is a circuit diagram of a switch circuit device including two multi-gate FETs. In the switch circuit device of FIG. 13, the multi-gate FET 10n is connected between the terminals A and B, and the multi-gate FET 20n is connected between the terminals A and C. The number of gates of the multi-gate FETs 10n and 20n is n. n is an integer of 2 or more. FET10
The control voltage V is applied to the n gates of n through the gate resistance.
_CTL is applied, and the control voltage / V _{CT L} is applied to the n gates of the FET 20n via the gate resistance. Here, it is assumed that the FET 10n is turned on and the FET 20n is turned off.

FIG. 14 shows a circuit diagram of a switch circuit device having a voltage distribution equivalent to that of the switch circuit device of FIG.
In the switch circuit device of FIG. 14, n single gate FETs 11, 12, ..., 1n are connected between terminals A and B, and n single gate FETs 2 are connected between terminals A and C.
1, 2, 2, ..., 2n are connected.

The control electrodes V _CTL are applied to the gates of the FETs 11 to 1n via gate resistances, and the FETs 21 to 2n are
The control voltage / V _CTL is applied to the gate of the gate via the gate resistance. Here, the FETs 11 to 1n are turned on,
It is assumed that 21 to 2n are off.

In this case, since the maximum voltage applied to the terminal A is V _max / 2, the source / source of each FET 21 to 2n is
The maximum voltage applied between the drains is V _max / (2n), and the maximum voltage applied between the gate and the source and between the gate and the drain is V _max / (4n).

The switch circuit device of FIG. 13 has a voltage distribution equivalent to that of the switch circuit device of FIG.
The maximum voltage applied between the gate and the source at the one end of 0n and between the gate and the drain at the other end is V _max / (4n).

FIG. 15 shows the relationship between the drain current _ID -gate voltage V _G characteristic of the FET and the input voltage. In the switch circuit device of FIG. 13, the FET 20n in the off state
The maximum voltage applied between the gate and source at one end and between the gate and drain at the other end is V
It becomes _max / (4n). Therefore, when the off-time control voltage / V _CTL is given as the gate voltage V _G , the FE
In order for T20n to maintain the off state, as shown in FIG. 15, the voltage amplitude swinging around the control voltage / V _CTL must be between the pinch-off voltage V _P and the breakdown voltage V _r . That is, the following formula needs to hold.

| V _P −V _r |> V _max / (2n) (2) Further, FIG. 16 shows the drain current I _D −source-drain voltage V _DS characteristic in the FET of the switch circuit device of FIG. Shows the relationship with the load line. When the voltage applied to the FET 10n in the ON state is V _AB , when the voltage of the signal source SG has the maximum amplitude, the drain current I _D represented by the following equation flows through the FET 10n.

I _D = −V _AB / (2R) + V _max / (2R) (3) Assuming that the resistance of the FET 10n in the ON state is very small, V _AB = 0, and the above equation (3) Is as follows.

[0060] _{I D = V max / (2R} ) ··· (4) Therefore, when V _DS = 0, that is, the drain current I _D in the ON state becomes V _{ma x} / (2R). Also, I _D
In the state where = 0, that is, in the off state, the maximum voltage applied between the source and drain of the FET is V _max / (2n) from the above discussion. Therefore, the load line at the maximum voltage amplitude in the FET 10n in the ON state is as shown in FIG.
As shown in FIG.

As can be seen from FIG. 16, the maximum V _max /
In order to maintain the linearity even when the drain current V _DS of (2R) flows, the saturated drain current I _DSS of the FET needs to be _equal to or _larger than the maximum current. Therefore, FET1 in the ON state
The saturated drain current I _DSS of 0n needs to satisfy the following equation.

I _DSS > V _max / (2R) (5) From the above consideration, F in the switch circuit device of FIG.
The ETs 10n and 20n need to satisfy the formula (2) from the off condition and the formula (5) from the on condition.

As a result of the above, the multi-gate FE having the pinch-off voltage V _P that satisfies the expressions (2) and (5).
By using T, it is possible to realize a small switch circuit device capable of high output transmission without signal leakage at a low operating voltage and without signal distortion.

FIG. 17 is a circuit diagram of a shunt switch circuit device including four multi-gate FETs. In the switch circuit device of FIG. 17, the multi-gate FET 10n is connected between the terminals A and B, and the multi-gate FET 20n is connected between the terminals A and C. Also, a multi-gate FET 50n is connected between the terminal B and the ground terminal,
The multi-gate FET 60n is connected between the terminal C and the ground terminal. Multi-gate FETs 10n, 20n,
The number of gates of 50n and 60n is n.

N gates of FET 10n and FET
The control voltage V _CTL is applied to each of n gates of 60n via a gate resistance. In addition, n of the FET 20n
A control voltage / V _CTL is applied to the gates of the FET and the n gates of the FET 50n through gate resistors. At this time, the FETs 10n and 60n are turned on, and the FET2
It is assumed that 0n and 50n are off.

FIG. 18 shows a circuit diagram of a switch circuit device having a voltage distribution equivalent to that of the switch circuit device of FIG.
In the switch circuit device of FIG. 18, n single gate FETs 11, 12, ..., 1n are connected between terminals A and B, and n single gate FETs 2 are connected between terminals A and C.
1, 2, 2, ..., 2n are connected. In addition, n single gate FETs 51 and 5 are provided between the terminal B and the ground terminal.
2, ..., 5n are connected, and n is provided between the terminal C and the ground terminal.
The single gate FETs 61, 62, ..., 6n are connected.

FET 11 to 1n and FET 61 to 6n
The control voltage V is applied to each gate via the gate resistance.
_CTL is given, and FET21-2n and FET51-
A control voltage / V _CTL is applied to the gate of 5n via a gate resistor. FET11 ~ 1n is FET10
FETs 21 to 2n correspond to FET 20n, FETs 51 to 5n correspond to FET 50n, and FETs correspond to n.
61 to 6n correspond to the FET 60n.

FET 11 to 1n and FET 61 to 6n
Is on and the FETs 21 to 2n and the FETs 51 to 5n are off, the maximum voltage applied to the terminal A is V
It becomes _max / 2. Therefore, the maximum voltage applied between the source and drain of each FET 21 to 2n is V _max / (2
n), and the maximum voltage applied between the gate and the source and between the gate and the drain is V _max / (4n), respectively. Similarly, the maximum voltage applied between the source and drain of each FET 51-5n is V _max / (2n), and the maximum voltage applied between the gate and source and between the gate and drain is V _max / (4n), respectively. Becomes

The switch circuit device of FIG. 17 has a voltage distribution equivalent to that of the switch circuit device of FIG.
The maximum voltage applied between the gate and the source at the one end of 0n and between the gate and the drain at the other end is V _max / (4n). Similarly, the maximum voltage applied between the gate and the source at one end and the gate and the drain at the other end of the FET 50n is V _max /
(4n).

Also in the switch circuit device of FIG. 17, F
In order to keep the ETs 10n and 20n completely in the off state, it is necessary to satisfy the relationship of the above formula (2). Also,
In order to maintain the linearity with respect to the input power P when the FETs 10n and 20n are turned on, it is necessary to satisfy the relationship of the above expression (5).

An embodiment of the present invention utilizing the above basic principle will be described below. FIG. 19 is a circuit diagram of the switch circuit device according to the first embodiment of the present invention. The switch circuit device of FIG. 19 has dual gate FETs 10 and 20 and gate resistors R1 and R formed on a GaAs substrate 100.
2, R3 and R4 are included. The FET 10 is connected between the terminals A and B, and the FET 20 is connected between the terminals A and C.
The two gates of the FET 10 have gate resistances R1 and R1, respectively.
The FET 20 is connected to the terminal D via R2, and the two gates of the FET 20 are connected to the terminal E via gate resistors R3 and R4, respectively.

The terminal A is connected to, for example, an antenna, the terminal B is connected to, for example, the transmitting circuit 81, and the terminal C is connected to, for example, the receiving circuit 82. The high frequency signal RF1 is input to the terminal B from the transmission circuit 81, and the terminal A is passed through the FET 10.
Is output to the antenna as a high frequency signal RF0. Further, the high frequency signal RF0 from the antenna is input to the terminal A, and is given to the receiving circuit 80 from the terminal C via the FET 20 as the high frequency signal RF2. Control voltages V _CTL and / V _{CT L} , which are complementary to each other, are applied to the terminals D and E, respectively. The control signals V _CTL and / V _CTL are, for example, + 5V and 0V, + 3V and -3V, or 0V and -5.
V is set.

In general, the power P ₁ of the signal transmitted from the transmission circuit 81 to the antenna via the FET 10 is larger than the power P ₂ of the signal transmitted from the antenna to the reception circuit 82 via the FET ₂₀ . That is, when the power P ₁ is transmitted by the FET 10, the FET 10 must transmit a large amount of power without signal distortion, and the FET 20 must be completely off for the large amount of power P ₁ . In this case, by using a FET with a deep pinch-off voltage as the FET 10 and using a FET with a shallow pinch-off voltage as the FET 20, the FET 10 can perform high-output transmission without signal distortion, and the FET 20 can perform complete transmission for large power. It is possible to maintain the off state.

On the other hand, when the signal of the power P ₂ is transmitted by the FET 20, the FET 20 may transmit a small power without distortion, and the FET 10 may be kept completely off for the small power P ₂ . In this case, since the signal transmitted by the FET 20 is minute, signal distortion does not occur even if the pinch-off voltage of the FET 20 is shallow. Further, since the power P ₂ is small, the FET 10 can easily maintain the off state even if the pinch-off voltage is deep.

[0075] Thus, in the switch circuit device shown in FIG. 19, the pinch-off voltage V _P of the FET10 is set deep, the pinch-off voltage V _P of the FET20 is set shallow.

Here, the pinch-off voltage of the FET 10 is V
_P1And withstand voltage is V_r1And the drain saturation current is I_DSS1When
I do. Moreover, the pinch-off voltage of the FET 20 is set to V_P2age,
Withstand voltage is V_r2And the drain saturation current is I_DSS2And Ma
Power P₁The maximum voltage amplitude during transmission of V_1maxAnd then
Power P_TwoThe maximum voltage amplitude during transmission of V_2maxAnd Further
The internal resistance of the signal source and the load resistance.
Let R. Where P ₁> P_TwoIt is.

The maximum voltage amplitude V _1max during transmission of the power P ₁ is given by the following equation. V _1max = √ (4R · P ₁ ) · √2 (6) The maximum voltage amplitude V _2max during transmission of the power P ₂ is given by the following equation.

V _2max = √ (4R · P ₂ ) · √2 (7) The pinch-off voltage V _P1 and the drain saturation current I _DSS1 of the FET 10 satisfy the following equation.

| V _P1 −V _r1 |> V _2max / (2n) (8) I _DSS1 > V _1max / (2R) (9) Pinch off voltage V _P2 of FET 20 and drain saturation current I _DSS2 Satisfies the following equation.

Shows an example of _{a> V 1max / (2n) ···} (10) I DSS2> V 2max / (2R) ··· (11) FET10,20 properties in Table 1 | [0080] | V _P2 -V _r2 . Table 1
The characteristics are shown for a gate width W _G = 1000 μm.

[0081]

[Table 1]

In this embodiment, the gate widths of the FETs 10 and 20 are set to 1800 μm and the gate resistances R1, R2, R3 are set.
The resistance value of R4 was set to be larger than 5 kΩ.
FIG. 20 shows a circuit pattern of the switch circuit device of FIG. As shown in FIG. 20, the dual gate FETs 10 and 20 and the gate resistor R1 are formed on the GaAs substrate 100.
0 and R20 are formed. The gate resistor R10 is shown in FIG.
Corresponding to the gate resistances R1 and R2 shown in FIG.
20 corresponds to the gate resistors R3 and R4. Further, Ga
On the As substrate 1, a pad PA corresponding to the terminal A, a pad PB corresponding to the terminal B, and a pad P corresponding to the terminal C.
C, a pad PD corresponding to the terminal D, a pad PE corresponding to the terminal E, a pad PG10 connected to the gate electrode of the FET 10, and a pad PG20 connected to the gate electrode of the FET 20 are formed.

FIG. 21 shows the dual gate FET1 of FIG.
0 shows the electrode pattern. As shown in FIG.
In FIG. 10, the comb-shaped source electrode S and the comb-shaped drain electrode D are arranged so as to be fitted to each other, and two gate electrodes G are arranged between the source electrode S and the drain electrode. The source electrode S is connected to the pad PA of FIG. 20, the drain electrode B is connected to the pad PB, and the gate electrode G is connected to the pad electrode PG10.

For comparison, the single gate FE is shown in FIG.
5 shows a circuit pattern of the switch circuit device of FIG. 4 using T. As shown in FIG. 22, single gate FETs 11, 12, 13, 14 and gate resistors R11, R12, R13, R14 are formed on a GaAs substrate 100. Furthermore, the pads PA and P are formed on the GaAs substrate 100.
B, PC, PD, PE, and pads PG11, PG1 connected to the gate electrodes of FETs 11-14, respectively
2, PG13, PG14 are formed.

FIG. 23 shows the single gate FET1 of FIG.
The electrode pattern of No. 1 is shown. As shown in FIG.
In 11, the comb-shaped source electrode S and the comb-shaped drain electrode D are arranged so as to fit each other, and one gate electrode G is arranged between the source electrode S and the drain electrode D. The source electrode S is connected to the pad PA of FIG. 22, the drain electrode D is connected to the pad PB, and the gate electrode G is connected to the pad PG11.

The short side length L of the switch circuit device of FIG.
1 is 360 μm, and the long side length L2 is 840 μm. On the other hand, the short side length L3 of the switch circuit device of FIG. 22 is 425 μm, and the long side length L4 is 10 μm.
It becomes 00 μm.

Thus, the two dual gate FETs are
In the switch circuit device of FIG.
The chip size is reduced by about 30% as compared with the switch circuit device of FIG. 4, which is composed of two single gate FETs 11 to 14.

FIG. 24 shows a simulation result of frequency dependence of insertion loss and isolation in the switch circuit device of FIG. As shown in FIG. 24, the insertion loss is smaller than 1.0 dB and the isolation is larger than 16 dB at 1.9 GHz. Thus, it can be seen that low insertion loss and high isolation can be obtained even if the chip size is reduced.

FIG. 25 is a circuit diagram of a switch circuit device according to a second embodiment of the present invention. The switch circuit device of FIG. 25 differs from the switch circuit device of FIG.
The point is that the chip inductor L is connected between C.
The configuration of the other parts is similar to that shown in FIG.

In the switch circuit device of this embodiment,
Chip inductor L and off-state dual gate FET
Resonance with the source-drain capacitances of 10 and 20 increases the isolation in a specific frequency region.

FIG. 26 shows a simulation result of frequency dependence of insertion loss and isolation in the switch circuit device of FIG. The simulation result shows that the inductance value of the chip inductor L is 23n
It is obtained when H is set. As shown in FIG. 26, the insertion loss is low and the isolation is 1.9 GHz.
It is as large as 26 dB. Thus, it can be seen that by connecting the chip inductor L, it is possible to increase the isolation in a specific frequency region while keeping the insertion loss low. By adjusting the inductance of the chip inductor L, it is possible to adjust the frequency region where high isolation is obtained.

In the first and second embodiments, the switch circuit device using the dual gate FET has been described, but a triple gate FET having three gate electrodes may be used instead of the dual gate FET.
Multi-gate FE having any number of gate electrodes described above
You may use T. Further, the conditions in the first and second embodiments can be similarly applied to the shunt switch circuit device shown in FIG.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a switch circuit device including two single gate FETs.

FIG. 2 is a schematic cross-sectional view of a single gate FET in an off state.

FIG. 3 is an equivalent circuit diagram of the single gate FET of FIG.

FIG. 4 is a circuit diagram of a switch circuit device including four single gate FETs.

FIG. 5 is a schematic cross-sectional view of two single gate FETs in an off state.

6 is a schematic sectional view showing a replacement structure the n ⁺⁺ layer of the two single-gate FET with common n ⁺⁺ layer shown in FIG.

7 is an equivalent circuit diagram of an FET having the structure of FIG.

FIG. 8 is a schematic cross-sectional view of a dual gate FET.

9 is an equivalent circuit diagram of the dual gate FET of FIG.

FIG. 10 is a circuit diagram of a switch circuit device including two dual gate FETs.

FIG. 11 is a diagram showing drain current-gate voltage characteristics in FETs having different pinch-off voltages.

FIG. 12 is a diagram showing drain current-source-drain voltage characteristics in FETs having different pinch-off voltages.

FIG. 13 is a circuit diagram of a switch circuit device including two multi-gate FETs.

14 is a circuit diagram of a switch circuit device having a voltage distribution equivalent to that of the switch circuit device of FIG.

FIG. 15 is a diagram showing a relationship between a drain current-gate voltage characteristic of an FET and an input voltage.

16 is a diagram showing a relationship between drain current-source / drain voltage characteristics and a load line in the FET of the switch circuit device of FIG.

FIG. 17 is a circuit diagram of a switch circuit device including four dual gate FETs.

18 is a circuit diagram of a switch circuit device having a voltage distribution equivalent to that of the switch circuit device of FIG.

FIG. 19 is a circuit diagram of a switch circuit device according to a first embodiment of the present invention.

20 is a plan view showing a circuit pattern of the switch circuit device of FIG.

21 is a diagram showing an electrode pattern of a dual gate FET in the switch circuit device of FIG.

22 is a plan view showing a circuit pattern of the switch circuit device of FIG. 4. FIG.

23 is a diagram showing an electrode pattern of a single-gate FET in the switch circuit device of FIG.

24 is a diagram showing simulation results of frequency dependence of insertion loss and isolation in the switch circuit device of FIG.

FIG. 25 is a circuit diagram of a switch circuit device according to a second embodiment of the present invention.

26 is a diagram showing a simulation result of frequency dependence of insertion loss and isolation in the switch circuit device of FIG. 25.

FIG. 27 is a circuit diagram showing an example of a conventional switch circuit device.

[Explanation of symbols]

 10, 20 Dual gate FET 10n, 20n, 50n, 60n Multi gate FET 100 GaAs substrate A, B, C, D, E terminal L Chip inductor

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Keiichi Honda, 2-5-5 Keihan Hondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. 2-5-5 Sanyo Electric Co., Ltd.

Claims (4)

[Claims] 1. A multi-gate field effect transistor, comprising: a multi-gate field effect transistor having n gate electrodes, wherein the internal resistance and the load resistance of a signal source connected to the multi-gate field effect transistor are each R. When the maximum voltage amplitude of the power transmitted by the transistor is V _max , the pinch-off voltage V _P , breakdown voltage V _r, and drain saturation current I _DSS of the multi-gate field effect transistor are | V _P −V _r |> V _{max / (2n) ··· (a} ) I DSS> V max / (2R) ··· (B) the above expression (a) and (B) switching circuit device which satisfies the. 2. A first multi-gate field effect transistor, which is connected between a common terminal and a first terminal and which transmits a signal of a _first power P ₁ , and a common terminal and a second terminal. with connected and a second multi-gate field effect transistor for transmitting the first second of the signal power P ₂ less than the power P ₁ during the first multi-gate field effect transistor has a first has a pinch-off voltage V _P1 of the second multi-gate field effect transistor switch circuit device, characterized in that it comprises a second pinch-off voltage V _P2 shallower than the first pinch-off voltage V _P1. 3. The value of the internal resistance and the load resistance of the signal source connected to the common terminal and the first and second terminals is R, and the number of gates of the first multi-gate field effect transistor is n. ₁ , the number of gates of the second multi-gate field effect transistor is n ₂ ,
The maximum voltage amplitude at the first power P ₁ is V _1max, and the maximum voltage amplitude at the second power P ₂ is V _2max.
In this case, the first pinch-off voltage V _P1 , the breakdown voltage V _r1 and the drain saturation current I _{DSS1 of} the first multi-gate field effect transistor, and the second pinch-off voltage of the second multi-gate field effect transistor. V _P2 , breakdown voltage V _r2 and drain saturation current I _DSS2 are: | V _P1 −V _r1 |> V _2max / (2n ₁ ) ... (C) I _DSS1 > V _{1max /(2R)...(D} ) _{| V P2 -V r2 |> V} 1max / (2n 2) ··· (E) I DSS2> V 2max / (2R) ··· (F) above formula (C), (D), (E) and The switch circuit device according to claim 2, wherein the condition (F) is satisfied. 4. The switch circuit device according to claim 2, further comprising an inductor connected between the first terminal and the second terminal.