JPH09232453A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device such as an EEPROM high in element isolating capability and junction breakdown strength and small in area of the element isolating region. SOLUTION: A wide opening 13a, at a memory cell array part 14, and a narrow opening 13b, at a peripheral circuit part 15, are made a silicon nitride film 13. After that, a photoresist 15 which has an opening 16a on the same level as the opening 13b is made within the opening 13a. Then, by the ion implantation using the photoresist 16 and the silicon nitride film 13 as masks, a channel stopper layer 19 is made, and silicon oxide films 21 a and 21 b are made as the silicon nitride film 13 as an oxidation preventive film. Therefore, at the memory cell array part 14, the source/drain diffused layer 33 and the channel stopper layer 19 are spaced, and at the peripheral circuit part 15, the area of the silicon oxide film 21b can be made small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a region where a relatively high operating voltage is used and a region where a relatively low operating voltage is used, and its manufacturing. Regarding the method.

[0002]

2. Description of the Related Art LOCOS is used as an element isolation region of a semiconductor device.
In the case of forming by the method, a resist which is a mask for forming an opening of a pattern of an element isolation region in a silicon nitride film which is an antioxidant film when performing a selective oxidation method, or a pattern of an element isolation region By using the silicon nitride film itself with the opening as a mask and implanting impurities of the same conductivity type as the semiconductor substrate into the semiconductor substrate, the channel is self-aligned with the oxide film (field oxide film) for element isolation. It is common to form a stopper layer. By forming the channel stopper layer in this way, a parasitic channel is not formed under the field oxide film, and a leak current or the like can be prevented.

However, according to this method, since the channel stopper layer is formed almost all over the element isolation region, the impurity diffusion layers such as the source / drain formed in the element active region and the channel stopper layer are in contact with each other. become.
Therefore, the EEP using a high operating voltage and a low operating voltage
In a non-volatile semiconductor memory device such as a ROM, when the impurity concentration of the channel stopper layer is increased to increase the element isolation capability, the element is formed in the element active region on the side of the memory cell transistor to which a high operating voltage is applied. The junction breakdown voltage between the impurity diffusion layer and the channel stopper layer will decrease. Therefore, with this method, it is difficult to manufacture a highly reliable semiconductor device.

Therefore, a resist having an opening having a width narrower than the pattern of the element isolation region is formed on the silicon nitride film having the pattern of the element isolation region, and the channel stopper layer is formed by ion implantation using the resist as a mask. A method of forming a gap to separate the impurity diffusion layer and the channel stopper layer formed in the element active region from each other (see, for example, JP-A-2-222174 and JP-A-4-22174).
-98850).

[0005]

However, in the method of the above publication, since the width of the element isolation region needs to be wider than the width of the channel stopper layer, the area of the element isolation region becomes unnecessarily large. It was difficult to manufacture a highly integrated semiconductor device.

Therefore, an object of the present invention is to provide a semiconductor device manufacturing method capable of manufacturing a semiconductor device using a high operating voltage and a low operating voltage with high reliability and a high degree of integration, and It is an object of the present invention to provide a semiconductor device having reliability and integration.

[0007]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention uses a first region where a relatively high operating voltage is used and a relatively low operating voltage. And a second region having a relatively wide width at a portion of the antioxidant film corresponding to the first region. No. 1 opening, a step of forming a second opening having a relatively narrow width in a portion of the antioxidant film corresponding to the second region, and a resist in the first opening. A step of forming a film and opening a part of the resist film to form a third opening; and introducing impurities into the substrate through the second opening and the third opening, A channel stopper layer in the first region and the second region of An oxide film for element isolation is formed in the first region and the second region by selectively thermally oxidizing the semiconductor substrate in the step of forming and the portion not covered with the antioxidant film. And the process.

It is preferable that a non-volatile memory cell transistor having a stacked gate structure is formed in the first region and a transistor forming a peripheral circuit section is formed in the second region.

It is preferable that the width of the third opening is substantially equal to the width of the second opening.

The oxide film may be a silicon oxide film having a film thickness of 300 nm or more.

The relatively high operating voltage is 10V.
As described above, the relatively low operating voltage may be 5 V or less.

A semiconductor device according to the present invention is a semiconductor device having a first region in which a relatively high operating voltage is used and a second region in which a relatively low operating voltage is used. The first region has a relatively wide oxide film for element isolation, and the second region has a relatively narrow oxide film for element isolation. The channel stopper layer in the region is formed only under the relatively wide oxide film for element isolation, and the channel stopper layer in the second region is substantially formed in the relatively wide region. Is formed over the entire area below the narrow oxide film for element isolation.

Further, it is preferable that the channel stopper layer in the first region is formed only in a central portion below the relatively wide oxide film for element isolation.

According to the present invention, in the first region in which a relatively high operating voltage is used, the width of the element isolation oxide film (field oxide film) is relatively wide so that the element isolation oxide film is formed. Since the outer edge of the element is wider than the channel stopper layer, the impurity diffusion layer formed in the element active region and the channel stopper layer can be separated from each other.

Therefore, by increasing the impurity concentration of the channel stopper layer, it is possible to enhance the element isolation capability and also to reduce the junction breakdown voltage due to the contact between the impurity diffusion layer formed in the element active region and the channel stopper layer. Can be prevented.

On the other hand, in the second region where a relatively low operating voltage is used, since the width of the oxide film for element isolation is relatively narrowed, the area of the element isolation region can be narrowed. .

By the way, in the nonvolatile memory cell transistor having the stacked gate structure, if the ratio of the area of the insulating film between the floating gate and the control gate to the area of the insulating film between the semiconductor substrate and the floating gate is increased, The capacitive coupling ratio between the floating gate and the control gate can be increased. Therefore, in the present invention, the nonvolatile memory cell transistor having the stacked gate structure is formed in the first region where a relatively high operating voltage is used, and the floating gate is formed in the relatively wide first region. Of the first isolation region, which is relatively wide, can be effectively used in order to increase the capacitive coupling ratio between the floating gate and the control gate. .

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIGS. 1A to 1C are cross-sectional views showing the semiconductor device of this embodiment in the order of steps.
3A is a plan view and a cross-sectional view showing the memory cell structure of the nonvolatile semiconductor memory device manufactured according to the present embodiment. FIG. In these figures, the memory cell array portion on the right side of FIG. 1 is a cross-sectional view taken along the line II of FIG.
2B is a sectional view taken along the line BB of FIG.
2C is a cross-sectional view taken along the line CC of FIG.

A nonvolatile semiconductor memory device such as an EEPROM manufactured in this embodiment has a memory cell having a stacked gate structure of a floating gate and a control gate, and this memory cell transistor has a relatively high operating voltage. Is used. Further, a selection transistor having a selection gate for address selection is formed adjacent to each memory cell transistor. A relatively low operating voltage is used for the selection transistor and the transistor formed in the peripheral circuit section.

In this embodiment, first, as shown in FIG. 1A, a P-type silicon substrate 11 having a specific resistance of about 10 Ω · cm is thermally oxidized to form a silicon film having a thickness of about 4 to 5 nm. The oxide film 12 is formed on the surface of the silicon substrate 11. A polycrystalline silicon film (not shown) as a buffer layer is further formed on the silicon oxide film 12,
So-called poly-silicon buffed
element may be isolated by the red) LOCOS method, and in this case, the bird's beak length can be reduced.

After that, a silicon nitride film 13 having a film thickness of about 150 to 200 nm is formed on the entire surface of the silicon oxide film 12 by CV.
Deposit by method D. Then, the silicon nitride film 13 is photolithographically and etched to form openings 13a having a width of about 1.2 to 1.4 μm in the memory cell array portion 14 and openings 13b having a width of about 0.5 μm in the peripheral circuit portion 15. Form.

Next, as shown in FIG. 1B, after the photoresist 16 is applied to the entire surface, the photoresist 16 in the peripheral circuit portion 15 is removed and the photoresist 16 in the memory cell array portion 14 is processed. The opening 16a is formed substantially in the center of the opening 13a. The opening 16a may be formed in the opening 13a, and the width of the opening 16a is about the same as the opening 13b of the silicon nitride film 13 (for example, the minimum processing size).

Then, using the photoresist 16 and the silicon nitride film 13 as a mask, 2.0 × 10 ^{13 to} 3.0 ×
Boron ions 17 with a dose of about 10 ¹³ cm ^-2 are added to 30
Silicon substrate 11 with acceleration energy of about 40 keV
Are ion-implanted into the silicon substrate 11 to form a boron implantation region 18 in the silicon substrate 11.

Next, as shown in FIG. 1 (c), the photoresist 16 is removed by ashing or the like, and then the silicon substrate 11 is removed by using the silicon nitride film 13 as an oxidation resistant mask.
Thermally oxidize at a temperature of about 00 ° C. Then, a silicon oxide film (field oxide film) 21 for element isolation having a film thickness of 300 nm or more is formed on a portion of the memory cell array portion 14 and the peripheral circuit portion 15 which is not covered with the silicon nitride film 13.
a and 21b are respectively formed, the boron in the boron implantation region 18 is activated and the silicon oxide film 21 is formed.
A channel stopper layer 19 is formed below a and 21b. Therefore, the width of the silicon oxide film 21 a is relatively wide corresponding to the width of the opening 13 a of the silicon nitride film 13, and the width of the silicon oxide film 21 b is the width of the opening 13 of the silicon nitride film 13.
It becomes relatively narrow corresponding to the width of b. As in this embodiment, by performing the ion implantation for forming the channel stopper layer in the step before the heat treatment for forming the field oxide film, the photoresist as the mask for ion implantation is charged and the film is formed. The thin insulating film is not destroyed. Further, since it is not necessary to perform ion implantation with a range larger than the film thickness of the field oxide film, it is possible to simplify the apparatus for performing ion implantation.

After that, the silicon nitride film 13 and the silicon oxide film 12 are removed, and then the silicon substrate 11 is thermally oxidized to form a memory as shown in FIGS. 1 (c) and 2 (b) (c). In the peripheral circuit portion 15 and the portion of the cell array portion 14 where the select gate is to be formed and in the vicinity thereof, the silicon oxide film 22 as a gate oxide film is formed on the surface of the element active region surrounded by the silicon oxide film 21a.
Then, a silicon oxide film 23 for tunneling is formed on the surface of the element active region surrounded by the silicon oxide film 21a in the portion where the floating gate of the memory cell array portion 14 is to be formed and in the vicinity thereof.

After that, as shown in FIGS. 2A to 2C, the floating gate 25 is formed of the first-layer polycrystalline silicon film 24 on the silicon substrate 11, and the ONO film 26 is used for the capacitive coupling insulation. A film is formed, and a control gate 28 is formed of the second-layer polycrystalline silicon film 27 on the silicon substrate 11. Further, the select gate 31 is formed by the polycrystalline silicon films 24 and 27. However, the select gate 31 is formed of the polycrystalline silicon film 2
It may be formed by only one of 4, 27.

Then, as shown in FIG. 1C, the silicon oxide films 21a and 21b and the polycrystalline silicon films 24 and 2 are formed.
7 as a mask, arsenic ions 32 with a dose of about 3.0 × 10 ¹⁵ cm ⁻² are ion-implanted into the silicon substrate 11 at an acceleration energy of about 80 keV, and the arsenic-implanted region 40 is formed.
To form

Thereafter, as shown in FIGS. 1 (d) and 2 (c), annealing is performed in a nitrogen atmosphere.
The source / drain diffusion layer 33 is formed by activating and diffusing arsenic in the arsenic implantation region 40. Of these source / drain diffusion layers 33, the side opposite to the selection gate 31 of the floating gate 25 and the control gate 28 is the source diffusion layer 3.
3a, and the side of the select gate 31 opposite to the floating gate 25 and the control gate 28 becomes the drain diffusion layer 33b.

As described above, the silicon oxide film 21
While the width of a is relatively wide in the memory cell array portion 14 and the width of the silicon oxide film 21b is relatively narrow in the peripheral circuit portion 15, the width of the opening 13a of the silicon nitride film 13 in the peripheral circuit portion 15 is large. Since the width of the opening 16a of the photoresist 16 and the width of the opening 16a of the photoresist 16 are set to be substantially the same,
In the memory cell array portion 14, the source / drain diffusion layer 33 and the channel stopper layer 19 are separated from each other, while the source / drain diffusion layer 33 and the channel stopper layer 19 are close to each other in contact with each other. Exists.

Next, as shown in FIGS. 1E and 2C, after forming an interlayer insulating film 34 such as a BPSG film on the entire surface, a contact hole 35 reaching the drain diffusion layer 33b.
Are formed on the interlayer insulating film 34. After that, contact hole 3
Al wiring 3 connected to the drain diffusion layer 33b through 5
6 is formed, and a surface protective film (not shown) or the like is further formed to form the memory cell 39 including the memory cell transistor 37 and the selection transistor 38.
A non-volatile semiconductor memory device arranged in an array is completed.

In the nonvolatile semiconductor memory device manufactured as described above, the memory cell transistor 37 is determined depending on whether or not a predetermined amount of charge is accumulated in the floating gate 25 of the memory cell transistor 37 in each memory cell 39.
The data is stored by changing the threshold voltage of and making these states correspond to "0" or "1".

Therefore, in order to rewrite the storage state of each memory cell 39, the silicon oxide film 23 for tunneling is used.
Charges are injected from the silicon substrate 11 to the floating gate 25 or extracted from the floating gate 25 to the silicon substrate 11 via.

For example, a potential of 5V is applied to the selection gate 31, a potential of 15V is applied to the control gate 28, and a potential of 0V is applied to the drain diffusion layer 33b and the silicon substrate 11, respectively, and the source diffusion layer 33a.
Are floated, so that electrons are injected from the drain diffusion layer 33b into the floating gate 25 through the silicon oxide film 23.

The select gate 31 has 5V, the control gate 28 and the silicon substrate 11 have 0V, and the drain diffusion layer 33.
A potential of 15 V is applied to each of b to bring the source diffusion layer 33a into a floating state, so that electrons are extracted from the floating gate 25 to the drain diffusion layer 33b through the silicon oxide film 23.

Therefore, the stronger the electric field is applied to the silicon oxide film 23, the more efficiently the memory state of each memory cell 39 can be rewritten. On the other hand, the voltage V _tox applied to the silicon oxide film 23, using the voltage V _cg applied to the control gate 28, the capacitance C _ONO capacitance C _tox and ONO film 26 of the silicon oxide film 23, V _tox = C Since it is represented by _ONO · V _cg / (C _ONO + C _tox ), the storage state of each memory cell 39 can be efficiently rewritten by increasing the capacity C _ONO of the ONO film 26.

Increasing the capacitance C _ONO of the ONO film 26 in this way generally makes the ONO between the floating gate 25 and the control gate 28 larger than the area of the silicon oxide film 23 below the floating gate 25. This is addressed by increasing the area of the membrane 26. Then, as one method for that purpose, as shown in FIGS. 2A and 2B, the floating gate 25 is mounted on the silicon oxide film 21a for element isolation.

Therefore, in the nonvolatile semiconductor memory device having such a structure, the size of the silicon oxide film 21a is controlled by the size of the floating gate 25 overlapping the silicon oxide film 21a, and is larger than the minimum processing size. . Therefore, as described above, the width of the silicon oxide film 21a in the memory cell array portion 14 is relatively widened to separate the source / drain diffusion layer 33 and the channel stopper layer 19 from each other. Widened silicon oxide film 21a
Are effectively used to overlap the floating gate 25.

In the above-described embodiments, since the channel stopper layer 19 having a high impurity concentration is formed, it has a high element isolation capability even for a high voltage of 10 V or more used in the memory cell array section 14. In addition to the above, the memory cell array section 14 can be used as a source / source as described above.
Since the drain diffusion layer 33 and the channel stopper layer 19 are separated from each other, these source / drain diffusion layers 33 are formed.
The junction breakdown voltage does not decrease due to the contact between the channel stopper layer 19 and the channel stopper layer 19.

On the other hand, the source / drain diffusion layer 33 and the channel stopper layer 19 are in contact with each other in the peripheral circuit section 15, but since the peripheral circuit section 15 uses only a voltage of about 3 to 5 V, these source / drain diffusion layers are diffused. Even if the layer 33 and the channel stopper layer 19 are in contact with each other, the junction breakdown voltage does not decrease.

In the present embodiment, the present invention is applied to a nonvolatile semiconductor memory device such as an EEPROM in which memory cell transistors have a laminated gate structure.
The present invention can be applied to semiconductor devices other than the nonvolatile semiconductor memory device as long as the semiconductor device includes a region in which a relatively high operating voltage is used and a region in which a relatively low operating voltage is used.

[0041]

According to the present invention, in the first region in which a relatively high operating voltage is used, it is possible to enhance the element isolation capability by increasing the impurity concentration of the channel stopper layer, and at the same time, the element active region. It is possible to prevent the junction breakdown voltage from decreasing due to the contact between the impurity diffusion layer and the channel stopper layer formed in the second region, and reduce the area of the element isolation region in the second region where a relatively low operating voltage is used. be able to. Therefore, a semiconductor device with high reliability and high integration can be obtained.

Further, the memory cell array portion of the nonvolatile semiconductor memory device having the stacked gate structure is formed in the first region where a relatively high operating voltage is used, and the floating gate is formed on the element isolation region having a relatively large area. Is extended, the capacitive coupling ratio between the floating gate and the control gate can be increased, so that the element isolation region can be effectively used and a nonvolatile semiconductor memory device having excellent characteristics can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention in the order of manufacturing steps.

FIG. 2 is a plan view and a cross-sectional view of a memory cell array portion of a nonvolatile semiconductor memory device manufactured according to an embodiment of the present invention.

[Explanation of symbols]

11 Silicon Substrate 13 Silicon Nitride Film (Oxidation Prevention Film) 13a Opening (First Opening) 13b Opening (Second Opening) 14 Memory Cell Array Part (First Area) 15 Peripheral Circuit Part (Second Area) 16 Photo Resist (resist film) 16a Opening (third opening) 19 Channel stopper layers 21a, 21b Silicon oxide film (oxide film for element isolation) 24 Polycrystalline silicon film 25 Floating gate 27 Polycrystalline silicon film 28 Control gate

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 27/10 481

Claims (7)

[Claims] 1. A first in which a relatively high operating voltage is used
And a second region in which a relatively low operating voltage is used, a method of forming an antioxidant film on a substrate, and the first region of the antioxidant film. And forming a relatively wide first opening at a location corresponding to the step, and forming a relatively narrow second opening at a location corresponding to the second region of the antioxidant film. And a step of forming a resist film in the first opening and forming a third opening by opening a part of the resist film, the second opening and the third opening A step of introducing an impurity into the substrate to form a channel stopper layer in the first region and the second region in the substrate, and selecting a portion of the semiconductor substrate not covered with the antioxidant film. By thermally oxidizing the first region and The method of manufacturing a semiconductor device, characterized by having a step of forming an oxide film for element isolation in the second region. 2. A non-volatile memory cell transistor having a stacked gate structure is formed in the first region, and a transistor forming a peripheral circuit portion is formed in the second region. The method for manufacturing a semiconductor device according to claim 1. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the width of the third opening is made substantially equal to the width of the second opening. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the oxide film is a silicon oxide film having a film thickness of 300 nm or more. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the relatively high operating voltage is 10 V or more and the relatively low operating voltage is 5 V or less. 6. A first in which a relatively high operating voltage is used
And a second region in which a relatively low operating voltage is used, the first region having a relatively wide oxide film for element isolation. The second region has a relatively narrow oxide film for element isolation, and the channel stopper layer in the first region is under the relatively wide oxide film for element isolation. The channel stopper layer in the second region is formed substantially over the entire region below the oxide film for element isolation, which is relatively narrow in width. Semiconductor device. 7. The channel stopper layer in the first region is formed only in the central portion below the relatively wide element isolation oxide film. Semiconductor device.