JPH09231749A - Voltage supply circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a voltage supply circuit which can reduce the power consumption and limit the increase of IC chip area. SOLUTION: A voltage supply circuit is divided into a VPP voltage supply circuit 50 for internal memory and a VPPO voltage supply circuit 51 for output section, and a pump circuit 30 by variation of data is provided in the VPPO voltage supply circuit 51, and only when the data variation is detected, the data change signals YDTD, CDTD indicating such data change are output to the VPPO control circuit 20. The oscillation signals VPROSC1, VPROSC2 for controlling the pumping are generated and are then output to the VPPO high power pumps 23, 24. These pumping circuit generate a high voltage VPPO and supplies it to the data output driver. Therefore, the VPPO voltage is supplied to the data output section only when the data change is detected, to suppress useless power.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage supply circuit applied to, for example, a semiconductor memory device.

[0002]

2. Description of the Related Art In recent years, DRAMs have been increased in capacity, speed and power consumption, and have been increasingly used in image processing. FIG. 6 is a diagram showing the concept of the field memory 80 composed of DRAM. The field memory stores image signals such as television signals in 1 field / 1
An image signal processing memory for accumulating and delaying in frame units.

As shown in FIG. 6, the Nth field /
The image signal of the frame is stored in the field memory 80 and output after a certain delay time. Such a field memory 80 is required to have a cycle and access time corresponding to a high sampling frequency, needs asynchronous read / write capable of real-time processing of image data, and further stores a plurality of image data. A large capacity is required for this.

FIG. 7 is a diagram showing the structure of the field memory 80. In FIG. 7, reference numeral 60 is a memory array, 61 is a write (write) address pointer, 62 is a write data register, 63 is a read (read) address pointer, 64 is a read data register, and 65 is a write / read / refresh. The control circuit and 66 are refresh timers, respectively.

Generally, the memory array 60 is composed of a highly integrated DRAM in order to store a huge amount of image data. Further, the data input / output unit is separated from the input unit and the output unit so as to follow a high-speed sampling frequency and enable an asynchronous read / write operation, and a data register is provided for each. Further, a write / read / refresh control circuit 65 for controlling a refresh operation and a write / read operation for automatically generating and refreshing a row address is provided. A refresh timer is also provided to control the refresh timing.

As the basic operation of the field memory 80 shown in FIG. 7, the write system and the read system are controlled by independent clock signals and enable signals, respectively, and the write data register 62, the read data register 63, and the memory array. The transfer of data to and from 60 is automatically controlled internally.

The field memory 80 is provided with a VPP voltage supply circuit for generating the high voltage VPP for boosting the gate voltage of the word line of the memory array 60, the output driver (output system drive circuit) of the peripheral circuits, and the like. ing. FIG. 8 is a block diagram showing the configuration of the VPP voltage supply circuit 50a. In FIG. 8, 10 is a VPP level sensor, 11 is a VPP control circuit, 12 is a VPP standby pump, 13 is a VPP high power pump, and 14 is an ATD.
(Address Transition Detection) Pump, 15 is DF
T (Design For Test) pump, 16 is VPP clamper /
A limiter (Clamper / Limiter) 100 is a VPP voltage output terminal, respectively.

As shown in FIG. 8, the VPP level sensor 1
0 receives the VPP voltage fed back from the VPP voltage output terminal 100, and outputs VP according to the level of the VPP voltage.
The control signal VPC is output to the P control circuit 11. The VPP control circuit 11 controls the control signal V from the VPP level sensor 10.
It receives VPP control signals from the PC and external circuits, and responds to these signals by VPP standby pump 12 and VPP.
The high power pump 13, the ATD pump 14, the DFT pump 15, and the VPP clamper / limiter 16 each output an on / off control signal.

For example, during standby, VPP control circuit 11 outputs an active ON / OFF control signal to standby pump 12 to cause standby pump 12 to generate a VPP voltage. Then, the VPP voltage generated by the standby pump 12 is output to the VPP voltage output terminal 100.

When the memory array is active, the VPP control circuit 11 outputs an active on / off control signal to the high power pump 13, and the VPP high power pump 13
To generate a VPP voltage and output it to the VPP voltage output terminal 100.

Further, in the page mode of the memory, VPP
The control circuit 11 turns on / off the ATD pump 14.
Output an off control signal to operate the ATD pump 14,
Generate the VPP voltage.

In the test mode, the VPP control circuit 11 outputs an active ON / OFF control signal to the DFT pump 15 to operate the DFT pump 15 and generate the VPP voltage.

Further, when the VPP voltage output to the VPP voltage output terminal 100 exceeds a predetermined voltage value, VPP
The control circuit 11 outputs an active control signal to the VPP clamper / limiter 16, and the VPP clamper / limiter 1
6 is operated and V is output to the VPP voltage output terminal 100.
The PP voltage is controlled within a predetermined range. Further, in the test mode or the like, the VPP clamper / limiter 16 clamps the VPP voltage to the power supply voltage.

Thus, the VPP voltage outputted to the VPP voltage output terminal 100 is constantly detected by the VPP level sensor 10, and when the VPP voltage becomes low, the VPP voltage becomes VPP.
A control signal VPC for enhancing the pumping operation of the voltage supply circuit 50a is output to the VPP control circuit 11.

[0015]

By the way, in the above-mentioned conventional VPP voltage supply circuit 50a, the ATD pump 14 is provided as a pump circuit for the output driver. ATD pump 14 is in page mode, S
It operates by receiving the address change detection signal in the CD (Static Column Decoder) mode. In this case, it is premised that the data changes as the address changes.
In the actual case, when the address changes, it is unknown whether or not the data changes. The same data may continue for a long time. If the same data continues, the output driver does not operate and the VPP voltage supply circuit does not need to pump. Therefore, the ATD pump 14
The control method in (1) has a problem that power is wasted.

To prevent this, there is a method of relying only on the detection of the VPP level without using the ATD pump 14. However, since the level detection circuit has potentially poor transient characteristics, the fluctuation of the VPP voltage is reduced. Therefore, the capacity of the smoothing capacitor must be increased to increase the IC chip area.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a voltage supply circuit which can reduce power consumption and limit an increase in IC chip area.

[0018]

In order to achieve the above object, a voltage supply circuit of the present invention is a voltage supply circuit for supplying a data output drive voltage to a data output system, and an input to the data output system. Data change detection means for detecting the presence or absence of data change and outputting a data change detection signal when there is data change; and a drive voltage for data output to the data output system upon receiving the data change detection signal. And a voltage generating means for supplying the data to the data output system.

Further, in the present invention, the data change detection means detects the presence or absence of a change for each bit forming each data and outputs the data change detection signal.

Further, according to the present invention, the data change detecting means outputs the data change detecting signal having contents corresponding to the number of changed data bits in the bits forming the data, and the voltage generating means outputs the data change detecting signal. A voltage having a level corresponding to the content of the data change detection signal is generated.

According to the present invention, the voltage supply circuit is provided with the data change detecting means for detecting the presence or absence of a change in the data, and the data input to the data output system by the data change detecting means has changed. At this time, a data change detection signal corresponding thereto is generated and output.

In the voltage generating means, a voltage is generated according to the data change detection signal and supplied to the drive circuit of the data output system. As a result, the data output section
The voltage is supplied to the data output drive circuit only when there is a change in the output data, and the voltage is not supplied at other times, so that the power consumption of the data output unit can be reduced. Furthermore, since the level fluctuation of the generated voltage is small, the capacity of the smoothing capacitor can be small, and the increase in the size of the IC chip can be suppressed.

Further, according to the present invention, a data change detection signal having a content corresponding to the number of bits of the output data changing is generated, and a voltage having a level corresponding to the level of the data change detection signal is generated by the voltage generating means. Therefore, the charge amount of the charges is adjusted according to the number of bits in which the data has changed, and the power consumption can be further reduced.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment FIG. 1 is a conceptual diagram showing a first embodiment of a voltage supply circuit according to the present invention. In FIG. 1, 10a is a VPP level sensor (VPS), 11a is a VPP control circuit (VPP).
CTL), 12a is a VPP standby pump (VPSP)
MP), 13a is a VPP high power pump (VPPHPM)
P) and 15a are VPP emergency pumps (VPEMPM)
P) and 16a are VPP clampers / limiters (VPPCL
AMP), 10b is a VPPO level sensor (VPO
S), 12b are VPPO standby pumps (VPOSP)
MP), 16b is a VPPO clamper / limiter (VPO
CLAMP), 17 is a VPPO enable control circuit, 1
8 is a Y data change detection circuit (VPYDTD), 19 is C
Data change detection circuit (VPCDTD), 20 is VPPO
Control circuits (VPROSC), 21 and 22 are VPPO emergency pumps (VPOEYPMP, VPOECPMP), 2
3 and 24 are VPPO high power pumps (VPOHPMP
-1, VPOHMPMP-2), 30 is a pump circuit by data change, 50 is a VPP voltage supply circuit, 51 is VPP
O voltage supply circuit, 100 is a VPP voltage output terminal, 101
Indicate the VPPO voltage output terminals, respectively.

As shown, the VPP in this embodiment is
The circuit is composed of two circuits, a VPP voltage supply circuit 50 and a VPPO voltage supply circuit 51. In the case of a field memory, the internal memory section and the data output section controlled by the read clock signal operate asynchronously, so to prevent mutual interference of noise, the VPP voltage dedicated to the memory section and the output driver (output drive circuit) dedicated The VPPO voltage is generated by the VPP voltage supply circuit 50 and the VPPO voltage supply circuit 51, respectively. The VPPO voltage supply circuit 51 is provided with a charge pump circuit 30 that obtains a boosted voltage according to a change in data. The charge pump circuit 30 detects a change in data and generates a VPPO voltage only when the data changes. To operate the pumping circuit to generate the VPPO voltage and
Output to the voltage output terminal 101.

As shown in FIG. 1, the pump circuit 30 according to data change is composed of a Y data change detection circuit 18, a C data change detection circuit 19, a VPPO control circuit 20, and VPPO high power pumps 23 and 24. Y
The data change detection circuit 18 detects a change in Y data in the image data, and when a change in Y data is detected, VP
The Y data change signal YDTD is output to the PO control circuit 20. The C data change detection circuit 19 detects a change in the C data in the image data. When the change in the C data is detected, the C data change signal CDTD is sent to the VPPO control circuit 20.
Is output. The VPPO control circuit 20 receives the control signal VPOC from the VPPO level sensor 10b, the Y data change signal YDTD from the Y data change detection circuit 18 and the C data change signal CDTD from the C data change detection circuit 19, and outputs these control signals. According to the oscillation signal VPR for controlling pumping to the VPPO high power pumps 23 and 24,
Output OSC1 and VPROSC2 respectively.

The VPPO high power pumps 23 and 24 are V
The oscillation signals VPROSC1 and VPROSC2 for controlling pumping from the PPO control circuit 20 and the on / off control signal VPPHEN from the VPP control circuit 11a are received, and pumping operation is performed according to these control signals.
A VPPO voltage is generated and output to the VPPO voltage output terminal 101.

The VPP voltage supply circuit 50 includes a VPP level sensor 10a, a VPP control circuit 11a, a VPP standby pump 12a, a VPP clamper / limiter 16a and a VP.
P high power pump 13a and VPP emergency pump 1
5a.

The VPP level sensor 10a receives the fed back VPP voltage of the VPP voltage output terminal 100, and outputs a control signal VPC to the VPP control circuit 11a according to the VPP voltage level. VPP control circuit 11a is V
Receives the control signal VPC from the PP level sensor 10a,
Accordingly, the VPP standby pump 12a, the VPP clamper / limiter 16a, the VPP high power pump 13
a and VPP emergency pump 15a output on / off control signals VPSEN, VPCLMP, VPPHEN and VPMEN, respectively.

For example, during standby, the VPP control circuit 11a activates the active on / off control signal VPSEN.
To the VPP standby pump 12a, and when the memory is active, the VPP control circuit 11a outputs an active on / off control signal VPHPEN to the VPP high power pump 13a. In an emergency, the VPP control circuit 11a outputs the active on / off control signal. Output VPMEN to the VPP emergency pump 15a. Further, when the level of the VPP voltage output to the VPP voltage output terminal 100 exceeds a predetermined voltage value, the VPP control circuit 11a causes the VPP clamper / limiter 16a to activate the on / off control signal V.
Outputs PCLMP and VPP clamper / limiter 16a
The VPP output by the pumping circuit
Limit the voltage level to within a predetermined range.

The VPP standby pump 12a receives an active on / off control signal VP from the VPP control circuit 11a.
When SEN is received, the pumping operation is performed to generate the VPP voltage, which is output to the VPP voltage output terminal 100. VP
When the P high power pump 13a receives an active on / off control signal VPHPEN from the VPP control circuit 11a, it performs a pumping operation to generate a VPP voltage,
Output to the P voltage output terminal 100. The VPP emergency pump 15a is turned on / off from the VPP control circuit 11a.
When receiving the off control signal VPMEN, the pumping operation is performed to generate the VPP voltage, and the VPP voltage output terminal 10
Output to 0. VPP clamper / limiter 16a is VP
The active on / off control signal V from the P control circuit 11a
When receiving PCLMP, it operates as a voltage clamper / limiter and limits the level of the VPP voltage within a predetermined range.

The VPPO voltage supply circuit 51 includes a VPPO level sensor 10b, a VPPO enable control circuit 17, V
It comprises a PPO standby pump 12b, a VPPO clamper / limiter 16b, VPPO emergency pumps 21 and 22 and a pump circuit 30 according to data changes.

The VPPO level sensor 10b receives the fed back VPPO voltage of the VPPO voltage output terminal 101, and outputs a control signal VPOC according to the VPPO voltage level.
And the VPPO enable control circuit 17 and the VPPO control circuit 20 in the pump circuit 30 according to the data change.
Respectively.

The VPPO enable control circuit 17 uses the VPP
Receives the control signal VPOC from the O level sensor 10b,
Oscillation signal VPOEY that controls pumping accordingly
OSC and VPOECOSC are generated and output to the VPPO emergency pumps 21 and 22, respectively.

VPPO emergency pumps 21 and 22 are VPP
Oscillation signals VPOEYOSC, VPOECOSC and VP for controlling pumping from the O enable control circuit 17
ON / OFF control signal VPOEE from the P control circuit 11a
Upon receiving N, the pumping operation is performed according to these signals to generate the VPPO voltage, and the VPPO voltage output terminal 10
Output to 1.

Hereinafter, the above VPP voltage supply circuit and V
The operation of these circuits in this embodiment will be described based on the configuration of the PPO voltage supply circuit. In the VPP voltage supply circuit 50, the level of the VPP voltage output to the VPP voltage output terminal 100 is detected by the VPP level sensor 10a, a control signal VPC is generated according to the level of the VPP voltage, and the control signal VPC is input to the VPP control circuit 11a. It

The VPP control circuit 11a receives the control signal VPC from the VPP level sensor 10a and outputs the control signal VPC.
On / off control signals are output to the VPP standby pump 12a, the VPP high power pump 13a, the VPP emergency pump 15a and the VPP clamper / limiter 16a according to the PC.

The VPP level sensor 10a, VPP
The control circuit 11a receives control signals RAS1, I from the external circuit.
In response to SYS2, etc., these control signals are controlled. For example, the system initialization enable signal ISYS
When E2 is set to the active state, VPP level sensor 10a and VPP control circuit 11a are initialized.

A pumping circuit constituted by the VPP standby pump 12a, the VPP high power pump 13a, and the VPP emergency pump 15a is a VPP control circuit 11a.
Is controlled by an on / off control signal from, and a predetermined pumping circuit operates according to each control signal,
The VPP voltage is generated and output to the VPP voltage output terminal 100. Also, the V generated by the pumping circuit
When the level of the PP voltage exceeds a predetermined value, the control signal VPCLMP from the VPP control circuit 11a operates the VPP clamper / limiter 16a to limit the level of the VPP voltage within a predetermined range. It should be noted that these pumping circuit and clamper / limiter receive control signals VBHLOSCE2, RAS1 and the like from an external circuit, and their operations are controlled by these control signals.

On the other hand, in the VPPO voltage supply circuit,
The level of the VPPO voltage output to the VPPO voltage output terminal 101 is detected by the VPPO level sensor 10b, and the VPPO control signal V is detected according to the level of the VPPO voltage.
The POC is generated and input to the VPPO enable control circuit 17 and the VPPO control circuit 20, respectively.

Oscillation signals VPOEYOSC and VP for controlling pumping by the VPPO enable control circuit 17.
OECOSC is generated and output to the VPPO emergency pumps 21 and 22, respectively. Then, the VPPO emergency pumps 21 and 22 receive the on / off control signal VPOEEN from the VPP control circuit 11a, and further receive the oscillation signals VPOEYOSC and VPOECOSC that control pumping from the VPPO enable control circuit 17, and operate in an emergency. A VPPO voltage is generated and output to the VPPO voltage output terminal 101. The VPPO enable control circuit 17 receives a clock signal RCP, a control signal ISYSE3, etc. from an external circuit, and its operation is controlled by these control signals. For example, the timing of the operation is controlled by the clock signal RCP, which is initialized when the system initialization enable signal ISYSE3 is set to the active state.

In the pump circuit 30 due to the data change, the Y data change detection circuit 18 and the C data change detection circuit 19 detect two types of signals constituting the data, that is, the changes in the Y data and the C data. When a change in the data is detected, a Y data change signal YDTD and a C data change signal CDTD indicating the respective changes in the data are generated and input to the VPPO control circuit 20.

The VPPO control circuit 20 controls the VPPO.
A level sensor 10b and a Y data change detection circuit 18,
Oscillation signals VPROSC1 and VPROS for controlling pumping according to a control signal from the C data change detection circuit 19
C2 is generated and the VPPO high power pump 23, 24
Respectively. The VPPO control circuit 20 uses the clock signal RCP and the control signal ISYS from the circuit.
The operation is controlled by E3. For example, the clock signal RCP controls the timing of the operation and is initialized when the system initialization enable signal ISYSE3 is set to the active state.

Oscillation signals VPROSC1, VPROSC2 and VP for controlling pumping from the VPPO control circuit 20 by the VPPO high power pumps 23 and 24.
ON / OFF control signal VPHPE from the P control circuit 11a
A VPPO voltage is generated according to N and is output to the VPPO voltage output terminal 101.

As described above, the VPP voltage supply circuit 50
And the VPPO voltage supply circuit 51 generate the VPP voltage and the VPPO voltage, respectively, and output them to the VPP voltage output terminal 100 and the VPPO voltage output terminal 101. Further, the pump circuit 30 for changing data is provided in the VPPO voltage supply circuit 51, and the pumping circuits 23 and 24 for generating the VPPO voltage operate only when the change of the data is detected to generate the VPPO voltage. , Is output. As a result, depending on the change of data, VP
Since PO is generated and the VPPO voltage is supplied to the data output section, useless power consumption is suppressed in the output section such as the data output driver.

FIG. 2 shows a Y data change detection circuit (VPYDTD) 18, a C data change detection circuit (VPCDTD) 19 and a VPPO control circuit (VPR) in this embodiment.
3 is a circuit diagram showing a configuration of OSC) 20. FIG. In FIG. 2, YCMP0 to YCMP7, CCMP0 to CCMP7
Is a comparison circuit composed of an exclusive OR (Ex.OR) circuit, YDLY0 to YDLY7, CDL
Y0 to CDLY7 are delay circuits formed by D flip-flops, ORG is an OR circuit, and TFF is a T flip-flop.

As shown in FIG. 2, in this embodiment, the data has two different attributes, Y data and C data.
Each type of signal has 8 bits. Furthermore, the 8-bit Y data is input to the input terminals YDO_0 to YDO_7 of the Y data change detection circuit 18, and the 8-bit C data is the C data change detection circuit 19
Input terminals CDO_0 to CDO_7.

The comparison circuits YCMP0 to YCMP7 and CCMP0 to CCMP in which the input Y data and C data are formed by exclusive OR circuits
The delay circuits YDLY0 to YDLY, which are input to one of the input terminals of
7, a comparison circuit YCMP via CDLY0 to CDLY7
It is input to the other input terminals of 0 to YCMP7 and CCMP0 to CCMP7. In addition, these delay circuits YDL
Delay timings of Y0 to YDLY7 and CDLY0 to CDLY7 are controlled by a read system clock signal RCP.

Comparison circuits YCM50 to YCMP7, CCM
The output signals YDTD0 to YDTD7 and CDTD0 to CDTD7 of P0 to CCMP7 are input to the input terminals of the OR circuit ORG, and the output terminals of the OR circuit ORG are connected to the T input terminals of the T flip-flops TFF. Oscillation signals VPROSC1 and VPROSC2 that control pumping are output to the output terminals of the T flip-flop TFF. The operation timing of the T flip-flop TFF is also controlled by the clock signal RCP.

As shown in FIG. 2, in the Y data change detection circuit 18, each bit of Y data and the delay circuit YDLY.
0 to YDLY7, each bit of the previous Y data delayed by one cycle of the clock signal RCP is input to each of the comparison circuits YCMP0 to YCMP7, and the comparison circuit YCMP0 configured by the exclusive OR circuit.
~ Compared by YCMP7. When there is a change in Y data, a predetermined comparison circuit YCMPx (x = 0, 1, ...,
The high level signal YDTDx is output to the output terminal 7). On the other hand, when there is no change in Y data, the comparison circuit YC
MP0 to YCMP7 are low-level signals YDTD0 to YD
DTD7 is output.

In the C data change detection circuit 19, each bit of the C data and each bit of the previous C data delayed by one cycle of the clock signal RCP by the delay circuits CDLY0 to CDLY7 are compared circuits CCMP0 to CCMP, respectively.
It is input to MP7 and compared by the comparison circuits YCMP0 to YCMP7 configured by the exclusive OR circuit. When there is a change in the C data, the high-level signal CDTDx is output to the output terminal of a predetermined comparison circuit CCMPx (x = 0, 1, ..., 7). On the other hand, when the C data does not change, the comparison circuits CCMP0 to CCMP7 output the low-level signals CDTD0 to CDTD7.

In the VPPO control circuit 20, when the signals output by the comparison circuits YCMP0 to YCMP7 and CCMP0 to CCMP7 are input to the input terminals of the OR circuit ORG and the Y data or C data changes, the output of the OR circuit ORG is output. A high level signal is output to the terminal,
Since the input signal is input to the T input terminal of the T flip-flop TFF, the oscillation signals VPROSC1 and VPROSC2 for controlling the pumping that takes a high level and a low level are output to the output terminal of the T flip-flop TFF.
The VPPO high power pumps 23 and 24 operate, and VPP
An O voltage is generated and the output driver is supplied with the VPPO voltage. .

On the other hand, when there is no change in the Y data and the C data, a low level signal is output to the output terminal of the OR circuit ORG and is input to the T input terminal of the T flip-flop TFF. Since the output signal level is held, the VPPO high power pump 23,
Since 24 does not operate and the VPPO voltage is not supplied to the output driver, useless power consumption is suppressed.

FIG. 3 is a timing chart showing the operation timing in the pump circuit 30 due to data change. As shown in the figure, the clock signal RCP is a signal that takes a high level and a low level mutually. Then, for example, 8-bit Y input to the Y signal change detection circuit 18
When, for example, the data YDO_x or CDO_x having 8-bit C data input to the data or the C signal change detection circuit 19 changes, the output signal YDTD of the Y signal change detection circuit 18 or the C signal change detection circuit 19
x or CDTDx becomes high level.

In the VPPO control circuit 20, a high level signal is output by the OR circuit ORG and input to the T terminal of the T flip-flop TFF. As a result, as shown in FIG. 3, at the next rising edge of the clock signal RCP. , The output signal of the T flip-flop TFF is inverted.

On the other hand, when the Y data and the C data do not change, the Y signal change detection circuit 18 and the C signal change detection circuit 19 output a low level signal. Then, in the VPPO control circuit 20, a low level signal is output by the OR circuit ORG and input to the T terminal of the T flip-flop TFF. As a result, the output signal level of the T flip-flop TFF is kept constant.

Oscillation signal VPR whose output signal and inverted output signal of T flip-flop TFF control pumping
Since OSC1 and VPROSC2 are input to the VPPO high power pumps 23 and 24, VPP is generated at the rising edge of the oscillation signal VPROSC1 that controls pumping.
The O high power pump (VPOHPMP-1) 23 performs a pumping operation to generate the VPPO voltage. At the rising edge of the oscillation signal VPROSC2 that controls pumping, the VPPO high power pump (VPOH
PMP-2) 24 is pumped and the VPPO
Voltage is generated.

FIG. 4 is a circuit diagram showing the structure of the VPPO high power pumps 23 and 24 composed of the charge pump circuit. Since the VPPO high power pump 23 and the VPPO high power pump 24 have the same configuration, FIG. 4 shows only one of them, for example, a circuit diagram of the VPPO high power pump (VPOHMPM-1) 23.

In FIG. 4, 1 is a power supply voltage V _CC supply line,
2 is a ground wire, 200 is an oscillation signal V for controlling pumping
Input terminal of PROSC1, 201 is an input terminal of ON / OFF control signal VPHPEN, and 202 is a NAND.
Circuits, 203 and 204 are inverters, 205 and 206 are delay circuits, for example, a delay circuit that provides a delay time of 1 nanosecond (1 ns), 207 is an inverter, 208 is a NOR circuit, 209 is a NAND circuit, 210, 2
11, ..., 215 are inverters, D ₁ , D ₂ , D ₃ are diodes, C ₁ , C ₂ , C ₃ , C ₄ are capacitors, SW
₁ , SW ₂ , SW ₃ , and SW ₄ are switch circuits, NT ₁ ,
NT _2, ..., NT ₈ is nMOS transistor, 220 denotes an output terminal, respectively.

Oscillation signal VPROS for controlling pumping
Input terminal 200 of C1 and ON / OFF control signal VPH
The input terminals 201 of the PENs are NAND circuits 202, respectively.
, And the output terminal of the NAND circuit 202 and the input terminal of the inverter 203 are connected.

The node ND ₁ which is the output terminal of the inverter 203 is connected to the input terminal of the inverter 204, the output terminal of the inverter 204 is connected to the input terminal of the delay circuit 205, and the output terminal of the delay circuit 205 is connected to the delay circuit 206.
Is connected to the input terminal of the node ND ₂ and these connection points form a node ND ₂ . The output terminal of the delay circuit 206 is connected to the node ND ₃ via the inverter 207.

The input terminals of the NOR circuit 208 are connected to the nodes ND ₁ and ND ₃ , respectively.
8 output terminals are connected to the node ND ₄ . The cathode of the diode D ₁ is connected to the node ND ₄ , and the anode is grounded. Also, one terminal of the capacitor C ₁ is connected to the node ND ₄ , and the other terminal is connected to the node ND _4.
Connected to ₅ .

[0063] The gate electrode and the drain electrode of the nMOS transistor NT ₁ is connected to the supply line 1 of the power supply voltage V _CC,
The source electrode is connected to the node ND ₅ . nMOS
The gate electrodes and source electrodes of the transistors NT ₂ , NT ₃ , and NT ₄ are connected, and these nMOS transistors are connected in series between the supply line 1 of the power supply voltage V _CC and the node ND ₅ .

The input terminals of the NAND circuit 209 are respectively
Node ND₁And node ND_ThreeConnected to the NAND circuit
The output terminal of 209 is connected to the node via the inverter 210.
ND ₆It is connected to the. Diode D_TwoThe cathode of
Node ND₆And the anode is grounded.
Also, the capacitor C_TwoOne terminal is node ND₆Contact
And the other terminal is the node ND₇It is connected to the.

The gate electrode of the nMOS transistor NT ₆ is connected to the node ND ₅ , and the drain electrode thereof is the power supply voltage V
_It is connected to the supply line 1 of _CC and the source electrode is connected to the node ND ₇ .

Inverters 211, 212, ..., 215 are connected in series between the nodes ND ₂ and ND ₈ . The cathode of the diode D ₃ is connected to the node ND ₈ , and the anode is grounded. One terminal of the capacitor C ₃ is connected to the node ND ₈ and the other terminal is connected to the node ND ₉ . One terminal of the capacitor C ₄ is connected to the node ND ₈ and the other terminal is connected to the node ND _8.
Connected to ₁₀ . Also, the nodes ND ₈ and ND
_The switch circuit SW ₁ is connected between the node ₉ and
The switch circuit SW ₂ is connected between D ₈ and the node ND ₁₀ .

Further, the node ND ₉ is connected to the switch circuit SW ₃
Through, is connected to the node ND _11, the node ND ₁₀ via the switch circuit SW _4, is connected to the node ND _11.

The gate electrode of the nMOS transistor NT ₅ is connected to the node ND ₅ , and the drain electrode thereof is the power supply voltage V
_It is connected to the supply line 1 of _CC and the source electrode is connected to the node ND ₁₁ . The gate electrode of the nMOS transistor NT ₇ is connected to the output terminal 220, the drain electrode is connected to the node ND ₇ , and the source electrode is connected to the node ND ₁₁ . The gate electrode of the nMOS transistor NT ₈ is connected to the node ND ₇ , and the drain electrode of the nMOS transistor NT ₈ is connected to the node ND.
₁₁ and the source electrode is connected to the output terminal 220.

Further, in this circuit, the switch circuit S
Since W ₁ is in the non-conducting state and the switch circuit SW ₂ is in the conducting state, the capacitor C ₄ is bypassed,
It does not work, but the capacitor C ₃ works. Further, since the switch circuit SW ₃ is in the conductive state and the switch circuit SW ₄ is in the non-conductive state, the node ND ₁₀ and the node ND ₁₁ are insulated, and the node ND ₉ and the node ND ₁₁ are conductive. Note that here, the switch circuit SW ₂ is set to a non-conducting state and the switch circuit SW ₄ is set to a conducting state, so that the capacitor C ₃ and the capacitor C ₄ are provided between the node ND ₈ and the node ND _11. Connected in parallel, the pumping ability of the charge pump circuit can be further enhanced.

The operation of the high power pump 23 will be described below based on the above circuit configuration. Oscillation signal VPR for controlling pumping when a high level signal is input to the input terminal of the on / off control signal VPHPEN
The signal input to the input terminal 200 of OSC1 is NAND
It is transferred to the internal circuit via the circuit 202. On the other hand, when a low level signal is input to the input terminal of the on / off control signal VPPHEN, the signal input to the input terminal 200 of the oscillation signal VPROSC1 for controlling pumping is not transferred to the internal circuit, and the high power pump The operation of 23 is stopped 1. That is, the on / off control signal VPH
When PEN is at high level, it becomes active.

When no data change is detected,
Oscillation for controlling pumping input to the input terminal 200
With the signal VPROSC1 held at a constant level
Keeps the on / off control signal VPHPEN at low level.
Node ND when held _FourIs high level, ND₆
And ND₈Is held low.

When the ON / OFF control signal VPPHEN is at the high level and a data change is detected, the oscillation signal VPROSC1 for controlling the pumping input to the input terminal 200 is switched between the high level and the low level. It becomes a oscillating signal. This input signal is the NAND circuit 20.
2. Input to the node ND ₁ via the inverter 203.

The signal on node ND ₁ is inverted by inverter 204, and after a predetermined delay time has passed by delay circuit 205, it is input to node ND ₂ . The signal of the node ND ₂ is further delayed by the delay circuit 206, then inverted by the inverter 207,
Entered in ₃ . Thus, the signal of the input signal and the phase to the input terminal 200 is input to the node ND _1, the node ND ₂ delayed signal of the inverted signal of node ND ₁ is input. The delayed signal of the inverted signal of the node ND ₂ is input to the node ND ₃ .

Also, the node ND_TwoSignal is inverter 2
Nodes ND via 11 to 215 ₈To be entered in
And node ND₈Signal is node ND_TwoThe reverse signal of
The signal has a constant delay time. Ie no
Do ND₈Signal is node ND₁Signal with constant delay time
Is the signal given.

The node ND is connected to the input terminal of the NOR circuit 208.
₁And node ND_ThreeSignals are input respectively,
Also, the node ND is connected to the input terminal of the NAND circuit 209.₁And
And node ND_ThreeSignals are input respectively. This result
Result, node ND₁And node ND_ThreeAre both low level
When the NOR circuit 208, that is, the node ND_FourTo high
When the level signal is input and at other times, the node N
D_FourA low level signal is input to. Also, the node N
D₁And node ND_ThreeWhen both signals are high level,
Node ND₆High level signal is input to
, Node ND ₆Low level signal is input to
You.

When the node ND ₄ is held at the low level and the voltage of the node ND ₅ is V _CC or more, the capacitor C ₁ is controlled by the nMOS transistor NT ₁ .
(V _CC -V _th) is charged up, the node ND ₅ is at V _CC voltage above when the node ND ₆ is held at a low level, the power supply voltage V _CC capacitor C ₂ is the nMOS transistor NT ₆ Will be charged to the level. Here, V _th is the nMOS transistor NT ₁
Shows the threshold voltage of. Further, when the node ND ₈ is held at the low level and the node ND ₅ has a voltage higher than V _CC , the capacitor C ₃ causes the nMOS transistor N
It is charged to the level of the power supply voltage V _CC by T ₅ .

As described above, the node ND ₄ and the node N
D ₆ has a high level and a low level, and the capacitors C ₁ and C ₂ connected to the respective nodes are charged with each other. The capacitor C ₃ is also charged via the nMOS transistor NT ₅ according to the level of the node ND ₈ .

For example, when the node ND ₈ is at the low level, the capacitor C ₃ is charged up to the power supply voltage V _CC level, and thereafter, when the node ND ₈ rises to the high level, for example, the power supply voltage V _CC level, The node ND ₁₁ is boosted to a level twice the power supply voltage V _CC by the capacitor C ₃ . Then, when the node ND ₇ is boosted by the capacitor C ₂ and reaches the level twice the power supply voltage V _CC , the nMOS transistor NT ₈ becomes conductive and the high voltage of the node ND ₁₁ is output to the output terminal 220. Then, when the level of the node ND ₆ drops to the low level, the level of the node ND ₇ also drops, the capacitor C ₂ is charged to the power supply voltage V _CC level via the nMOS transistor NT ₆ , and the node ND ₇ goes to the power supply voltage V _CC. Since it returns to the _CC level, the nMOS transistor NT ₈ becomes non-conductive, and the node ND ₁₁ and the output terminal 220 become insulated. Also, when the node ND ₆ goes down, it is synchronized,
Since the level of the node ND ₈ also drops, the capacitor C ₃ is charged to the power supply voltage V _CC level via the nMOS transistor NT ₅ , and the node ND ₁₁ returns to the power supply voltage V _CC level.

In this way, the VPPO high power pump 2
3, an oscillation signal VPROS for controlling pumping
When an oscillation signal is input to the C1 signal input terminal 200,
The pumping operation is performed in synchronization with the rising edge of the input signal, the high voltage is output to the output terminal 220, and the output of the high voltage to the output terminal 220 is stopped in synchronization with the falling edge of the input signal. To be done.

Output terminal 220 is connected to VPPO voltage output terminal 101 shown in FIG. 1 to provide a high voltage VPPO voltage to the output section of the memory.

As described above, according to this embodiment, the voltage supply circuit is divided into the VPP voltage supply circuit for the internal memory and the VPPO voltage supply circuit for the output section, and V
The PPO voltage supply circuit 51 is provided with the pump circuit 30 according to the data change, and only when the data change is detected, the data change signals YDTD and CDTD indicating the data change are output to the VPPO control circuit 20, and the oscillation signal V for controlling the pumping is output.
PROSC1 and VPROSC2 are generated and output to the VPPO high power pumps 23 and 24, and a high voltage VPPO voltage is generated by these pumping circuits and output to the VPPO voltage output terminal 101, so only when a change in data is detected. Further, the VPPO voltage is supplied to the data output section, and useless power consumption is suppressed.

Second Embodiment FIG. 5 is a circuit diagram showing a second embodiment of the voltage supply circuit according to the present invention, which is a circuit diagram of the data change detection circuit. In FIG. 5, DT _{0 to} DT _X are data input terminals,
DLY _{0 to} DLY _X are delay circuits, and DCMP _{0 to} DCMP
_X is a comparison circuit composed of exclusive OR circuits, NTR _{0 to} NTR _X are nMOS transistors,
R is a load resistance, BAMP is an output amplifier, and T _OUT is an output terminal.

In the second embodiment, the detection of data change is controlled by dividing the bits without taking the logical sum of the bits of all the data. X as shown
Bit data is input to the data input terminals DT _{0 to} DT _X, and the input data is input to the delay circuits DLY ₀ to DLY, respectively.
Compare circuit DCM with original data via DLY _X
It is input to P0 to DCMP _X.

[0084] The output terminal of the delay circuit DLY ₀ ~DLY _X is connected to the gate electrode of the nMOS transistor NTR ₀ ~NTR _X, nMOS transistors NTR ₀ ~
The drain electrodes of NTR _X are commonly connected, and the node ND ₁ is configured by these connection points, and the node ND _1
1 is connected to the supply line 1 of the power supply voltage V _CC via the resistor R ₁ . The source electrodes of the nMOS transistors NTR _{0 to} NTR _X are grounded, and the node ND ₁ is connected to the amplifier BAMP.
_Is connected to the output terminal T _OUT via.

The input data is delayed by one cycle of the clock signal and output by the delay circuits DLY _{0 to} DLY _X , so that the current input data is compared with the input data one cycle before the clock signal to obtain the data. When there is no change, a high level signal is output to the output terminal of the comparison circuit, and when there is no change in data, a low level signal is output to the output terminal of the comparison circuit.

In the circuit shown in FIG. 5, when the bit of data changes, the nMOS transistor N is correspondingly changed.
Since a predetermined transistor of TR _{0 to} NTR _X becomes conductive and a conductive current flows through the nMOS transistor in the conductive state, a current flowing through the resistor R according to the number of changed data bits in the input data. The value is determined,
The voltage of the node ND ₁ is also determined.

The voltage of the node ND ₁ is output to the output terminal T _OUT via the amplifier BAMP and input to the pump circuit as a control signal for the pump circuit. Then, the pump circuit performs a pumping operation according to the control signal,
An O voltage is generated and supplied to the data output section.

As described above, the level of the control signal input to the pump circuit changes in accordance with the number of bits in which the data has changed, so that VPP is changed in accordance with the required charge amount.
The O voltage is supplied to the data output section, and the power consumption of the output section is further suppressed.

[0089]

As described above, according to the voltage supply circuit of the present invention, it is possible to reduce the power consumption of the data output section in a large-capacity memory device and to suppress the increase of the IC chip size. is there.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a voltage supply circuit according to the present invention.

FIG. 2 is a circuit diagram of a data change detection circuit.

FIG. 3 is a flowchart of a pump circuit according to data change.

FIG. 4 is a circuit diagram of a high power pump circuit.

FIG. 5 is a circuit diagram showing a second embodiment of a voltage supply circuit according to the present invention.

FIG. 6 is a conceptual diagram of a field memory.

FIG. 7 is a block diagram showing a configuration of a field memory.

FIG. 8 is a block diagram showing a configuration of a conventional voltage supply circuit.

[Explanation of symbols]

1 ... Power supply voltage V _CC supply line 2 ... Ground line 10, 10a ... VPP level sensor 10b ... VPPO level sensor 11, 11a ... VPP control circuit 11b ... VPPO control circuit 12, 12a ... VPP standby pump 12b ... VPPO standby pump 13, 13a ... VPP high power pump 13b ... VPPO high power pump 14 ... ATD pump 15 ... DFT pump 16, 16a ... VPP clamper / limiter 16b ... VPPO clamper / limiter 17 ... VPPO enable control circuit 18 ... Y data change detection circuit 19 ... C Data change detection circuit 20 ... VPPO control circuit 21, 22 ... VPPO emergency pump 23, 24 ... VPPO high power pump 30 ... Data change pump circuit 50, 50a ... VPP voltage supply circuit 51 ... VPPO voltage supply circuit 60 ... Memory array 61 ... Write address pointer 62 ... Write data register 63 ... Read address pointer 64 ... Read data register 65 ... Write / read / refresh control circuit 66 ... Refresh timer 80 ... Field memory 100 ... VPP voltage output Terminal 101 ... VPPO voltage output terminal 200 ... Oscillation signal input terminal 201 ... ON / OFF control signal VPHPEN input terminal 202, 209 ... NAND circuit 203, 204, 207, 210-215 ... Inverter 205, 206 ... Delay circuit 208 ... NOR Circuit 220 ... Output terminals YCMP0 to YCMP7, CCMP0 to CCMP7, D
CMP _{0 to} DCMP _X ... Comparison circuit YDLY0 to YDLY7, CDLY0 to CDLY7, D
LY ₀ ~DLY _X ... delay circuit ORG ... OR circuit TFF ... T flip-flop _{D 1, D 2, D 3} ... diode _{C 1, C 2, C 3} , C 4 ... capacitor _{SW 1, SW 2, SW 3} , SW ₄ ... switching circuit _{NT 1, NT 2 ~NT 8 ...} nMOS transistor YDO_0~YDO_7, CDO_0~CDO_7, D
T _{0 to} DT _X ... Data input terminal NTR _{0 to} NTR _X ... nMOS transistor R ... Resistor BAMP ... Output amplifier T _OUT ... Output terminal V _CC ... Power supply voltage GND ... Ground potential

Claims (3)

[Claims] 1. A voltage supply circuit for supplying a data output drive voltage to a data output system, detecting the presence or absence of a change in input data to the data output system, and changing the data when there is a change in the data. A voltage supply circuit having data change detection means for outputting a detection signal and voltage generation means for receiving the data change detection signal and generating a data output drive voltage for the data output system and supplying the voltage to the data output system. . 2. The voltage supply circuit according to claim 1, wherein the data change detection means detects the presence or absence of a change for each bit constituting data and outputs the data change detection signal. 3. The data change detecting means outputs the data change detecting signal having a content corresponding to the number of changed bits in the bits forming the data, and the voltage generating means outputs the content of the data change detecting signal. The voltage supply circuit according to claim 1, which supplies a voltage of a corresponding level.