JPH09231744A - Storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve an easy mode setting from the outside and a mode setting of a storage device even in the state where it is not incorporated in a system by providing a mode setting register capable of inputting from the outside. SOLUTION: In an ordinary operation, a test mode selection signal is off, and a select circuit 6 selects output of an access control circuit 4 and a system clock. When the power is on, an ordinary control signal such as a mode setting command, etc., is transferred to the access control circuit 4 from the system. The access control circuit 4 generates a control signal for mode setting and an address. The control signal and address are selected by the select circuit 6 to be transferred to a storage 10. The content of the address controlled by the control signal generated in the access control circuit 4 is written into a mode holding member 11 in the storage 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device that requires an access mode setting. The conventional semiconductor memory can be accessed for writing and reading by executing a dummy cycle for a fixed time after the power is turned on. However, recently, a semiconductor memory (SDRAM) that requires setting of an access mode has been developed, and this memory device enables desired access by setting a mode in the memory. For example, burst length (Burst Length) that determines the number of bits to be read or written in one clock, wrap type that determines the method of reading or writing such as sequential or interleave, and until the data is read or written after the CAS signal is input. The normal read / write is started after setting the mode such as CAS Latency that determines the number of clocks.

In a memory device that does not require mode setting, a memory test was easy, but in the case of a memory that sets a mode, since the fixed mode setting data is given from the system side, The change is not easy and the memory test cannot be done easily. In particular, the test was impossible in a state where the memory device was not incorporated in a device to be incorporated (hereinafter referred to as a system).

[0003]

2. Description of the Related Art FIG. 7 shows the structure of a memory device required for conventional mode setting. In FIG. 7, 110 is a memory device.

Reference numeral 111 is a CPU. Reference numeral 112 is a control program. Reference numeral 112 'is a monitoring program for setting a mode in the memory.

A memory access controller 113 controls memory access according to commands. 114 is a timing signal generation circuit,
The CAS (column address strobe signal), RAS (row address strobe signal), WE (write enable signal), and CS (chip select signal) are generated.

Reference numeral 115 denotes an address generation circuit, which generates an address necessary for setting a mode setting address. The mode setting data is the address for setting in the memory.

Reference numeral 116 is a memory, which is a semiconductor memory. Reference numeral 121 denotes a mode setting unit, which holds mode setting data that defines the operation mode of the memory.

The operation of the configuration shown in FIG. 7 will be described. When the power is turned on to use the system including the memory device 110, the CPU 111, and the control program 112, the control program 112 and the CPU 111 start the operation,
A command for setting the mode to the memory is issued according to the monitoring program 112 ′, and the memory access controller 113 controls the timing signal generation circuit 114 and the address generation circuit 115 according to the command. The timing signal generation circuit 114 generates the RAS, CAS, WE, and CS signals necessary for setting the mode in the memory 116. Further, the address generation circuit 115 generates an address necessary for mode setting in the mode setting unit 121. The address is mode setting data, and RAS, CAS, W generated in the address generation circuit 115 are generated.
According to the E and CS signals, the mode setting data is written in the mode setting unit 121 and the mode is set.

[0009]

As described above, the mode setting for the memory is made by the monitoring program of the system using the memory device. Therefore, it is not easy to change the mode setting, and when the memory device is not installed in the system (device into which the memory device is installed), it is not possible to set the mode in the memory device and it is installed in the system. The memory device could not be tested without it.

According to the present invention, the mode setting can be easily set and changed from the outside, and the mode setting can be performed on the memory device even when it is not incorporated in the system, so that the memory device can be easily tested. It is an object of the present invention to provide a memory device capable of performing

[0011]

SUMMARY OF THE INVENTION According to the present invention, in a memory device which requires mode setting for access, mode setting data input from outside the device into which the memory is to be installed or in a state where the memory is not installed is externally input. It has a mode setting register that holds it, and the memory access mode can be set externally by setting the mode setting data of the mode setting register to the memory.

FIG. 1 shows the basic configuration of the present invention (claim 2).
Corresponding to). In FIG. 1, 1 is a memory device.

Reference numeral 2 is an input means for inputting mode setting data. Reference numeral 3 denotes a mode setting input control unit which performs control for inputting mode setting data to the mode setting register 5.

An access control circuit 4 controls the access to the memory 10 in a normal operation. A mode setting register 5 holds mode setting data input from the input means 2.

A selection circuit 6 selects the contents of the mode setting register 5 in the test mode and transfers the contents to the memory 10. In the normal operation mode, the contents of the access control circuit 4 are selected and stored in the memory. It is to be transferred to 10.

Reference numeral 10 is a memory that requires mode setting. A mode holding unit 11 holds the mode setting data. The operation of the basic configuration of the present invention shown in FIG. 1 will be described.

In normal operation, the test mode selection signal is off, and the selection circuit 6 selects the output of the access control circuit 4 and the system clock. When the power is turned on, a normal control signal such as a mode setting command is transferred from the system side to the access control circuit 4.
The access control circuit 4 generates a control signal and an address for setting the mode. Then, the control signal and the address are selected by the selection circuit 6 and transferred to the memory 10. In the memory 10, the content of the address (mode setting data) is written in the mode holding unit 11 under the control of the control signal generated by the access control circuit 4.

In the test mode, the test mode signal is turned on and the selection circuit 6 causes the mode setting register 5 to operate.
Select the contents and external clock. The mode setting data is input by the external input means 2 and held in the mode setting register 5 by the mode setting input control section 3.
The contents of the mode setting register 5 are control data necessary for mode setting and mode setting data (address).

The selection circuit 6 selects the mode setting register 5 and the external clock. Then, the data of the address is written in the mode holding unit 11 by the external clock and the control data (for example, CAS, RAS, WE, CS, etc.) set in the mode setting register 5.

According to the present invention, it is possible to easily set and change the mode of the memory. In addition, even when the memory device mounted on the board or the like cannot be set or changed because the memory device is not incorporated in the system, the mode can be set and changed easily. Therefore, the memory device can be easily tested even when the memory device is not incorporated in the system.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a first embodiment of the configuration of the present invention. In FIG. 2, reference numeral 21 is a CPU.

Reference numeral 22 is a memory device. Reference numeral 23 is an input means. Reference numeral 24 is a mode setting input control unit.

Reference numeral 32 is a mode setting register. 33
Is an access control circuit. A memory access controller 35 receives commands from the CPU 21 and controls access to the memory 40.

Reference numeral 36 is a timing signal generating circuit,
Control signals for accessing the memory 40 (CAS, R
(AS, WE, CS, etc.). An address generation circuit 37 generates an address for mode setting in the memory 40 (the generated address is mode setting data).

Reference numeral 40 denotes a memory, which is used by setting a mode. A mode holding unit 41 holds the mode setting data in the memory 40.

Reference numeral 50 is a selection circuit. Reference numeral 51 is an inverter for inputting and inverting the test mode signal (1e).

Reference numeral 52 denotes an AND circuit, which is an inverter 5
The test mode signal (1e) inverted by 1 and the system clock (1a) are input and the logical product is obtained. 53 is an AND circuit, which is a test mode signal (1
e) and an external clock are input to take a logical product.

Reference numeral 54 is an OR circuit, and AND circuit 52
And the output of the AND circuit 53. 5
An AND circuit 5 inputs a test mode signal and the contents of the mode setting register 32 to obtain a logical product, and becomes a control signal for mode setting (CAS, RAS, WE, and CS are all active) ( 4 bits) are output.

Reference numeral 56 denotes an AND circuit, which is a negative logic of the test mode signal and control signals (CAS, RAS, WE, C) generated by the timing signal generation circuit 36 for mode setting.
All S inputs active (4 bits), takes a logical product, and outputs a control signal for mode setting in a normal use state.

Reference numeral 57 is an OR circuit, which is an AND circuit 55.
And the output of the AND circuit 56. 5
An AND circuit 8 inputs a test mode signal and the contents of the mode setting register 32 to obtain a logical product and designates an address for mode setting (a holding area of the mode holding unit 41 in the test mode). And outputs the mode setting data).

Reference numeral 59 is an AND circuit, which inputs the negative logic of the test signal and the address (mode setting data) for setting the mode of the address generating circuit 37, calculates the logical product,
The address is output in a normal use state.

An OR circuit 60 is an AND circuit 58.
And the AND circuit 59. FIG. 3 is an explanatory diagram of a mode setting method of the memory device used in the present invention.

In FIG. 3, FIG. 3A is an explanatory diagram of the mode setting register, and 32 is the mode setting register.

The mode setting register of the present invention holds 4-bit control data and 12-bit mode setting data (address), and can externally change the content of the data.

Control data is CAS, RAS, WE, CS
Is 4-bit data that activates. Mode setting data represents the contents of mode setting (see Fig. 3 (b)) 1
It is 2-bit data. The mode setting data is composed of, for example, 12 bits, the lower 3 bits are BL (burst length), the next 1 bit is WT (wrap type), and the next 3 bits are LTMODE.

Reference numeral 40 is a memory. Reference numeral 41 denotes a mode holding unit which holds 12-bit mode setting data.

Reference numeral 61 is a normal use area, which is an area used for normal writing and reading. Reference numeral 62 denotes mode setting data, which is the output of the address generation circuit 37 or the mode setting register 32.

Reference numeral 63 is control data, which is the output of the timing signal generating circuit 36 or the mode setting register 32. The mode setting data 62 is the data fetched from the mode setting register 32 in the test mode, and the data output from the address generating circuit 37 in the normal operation. Mode setting for the memory 40 is performed based on the control data 63. RAS, CA
The mode setting data 62 is set in the mode holding unit 41 of the memory 40 by the control signal including S, WE, and CS.

FIG. 4 is a time chart of the operation of the first embodiment of the present invention. In FIG. 4, symbols such as 1a and 1b correspond to those in FIG. Reference numeral 1e is a test mode signal which becomes H when a memory test is performed.

1a is a system clock, which is a system clock of a system using the memory device of the present invention. An external input clock 1b is a clock for setting data in the mode setting register 32 and setting the mode setting data held in the mode setting register 32 in the memory.

1c is external input data, which is data given from the outside to be set in the mode setting register 32. Reference numeral 1f is a control signal for mode setting, which is a control signal generated based on the control data output from the mode setting register 32 in the test, and the timing signal generation circuit 3 in the normal operation.
6, the output of the address generation circuit 37.

* CAS, * RAS, * WE, and * CS are low-active CAS signal, RAS signal, and WE, respectively.
Signal and CS signal. The address is mode setting data.

When testing the memory, the test mode signal goes high. The H test mode signal is an AND circuit 53,
The data is input to the AND circuits 55 and 58, the external input clock 1b, the control data and the address data of the mode setting register 32 are selected, and the OR circuit 5 is selected.
7, input to the memory 40 via the OR circuit 60. The test mode signal is inverted by the inverter 51, and the output of the inverter 51 is L during the test. Since the L signal is input to the AND circuit 52, the AND circuit 56, and the AND circuit 59, in the test mode, the system clock 1
a, the output of the timing signal generation circuit 36 (1d-1),
The output (1d-2) of the address generation circuit 37 is not selected and is not input to the memory 40.

In the test mode, mode setting data is input from the outside. At this time, 4-bit control data is set so that * CAS, * RAS, * WE, and * CS become L. The external data is set in the mode setting register 32 by the mode setting input control unit 24 according to the external input clock (1b) (time t ₁ ).

In the test, L active * CA
Control data for S, * RAS, * WE, and * CS are output from the mode setting register 32, and the data is given to the memory 40 by the external clock, and the memory 40 sets the mode in the mode holding unit 41 according to the control data. Data is written (time t ₂ ). When the mode setting is completed, the mode setting register 32 is set according to the external clock.
Contents of control data * CAS, * RAS, * WE, * C
Set so that S becomes H (time t ₃ ).

In the normal mode, the test mode signal is L, and the input sides of the test signals of the AND circuits 53, 55, and 58 are L. Therefore, the external input clock 1b and the mode setting register 32 are used. Data is not selected. At that time, the output of the inverter 51 is H, which is input to the AND circuit 52, the AND circuit 56, and the AND circuit 59. Therefore, the system clock 1a which is the other input signal of the AND circuit 52, the AND circuit 56, and the AND circuit 59, the output 1d-1 of the timing signal generation circuit 36, and the output 1d-2 of the address generation circuit 37 are selected, and the memory 40 Entered in. Then, * CAS, * RAS, * output from the timing signal generation circuit 36
Controlled by the L signal of WE and * CS, the mode setting data output from the address generating circuit 37 is set in the mode holding area of the memory.

FIG. 5 shows a second embodiment of the configuration of the present invention. In FIG. 5, the register used to set the mode in the normal operation is used as the mode setting register in the test.

In FIG. 5, reference numeral 21 is a CPU. 22
Is a memory device.

Reference numeral 23 is an input means. Reference numeral 24 is a mode setting input control unit. A mode setting register 32 is a register used for mode setting in a normal operation. It can also be used for other than test mode setting.

Reference numeral 33 is an access control circuit. Reference numeral 35 is a memory access controller. 36 is a timing signal generation circuit.

Reference numeral 37 is an address generation circuit. 40 is a memory. 41 is a mode holding unit.

Reference numeral 71 is an inverter for inputting, inverting and outputting a test signal. Reference numeral 72 is an AND circuit, which takes the logical product of the output of the inverter 71 which is the system clock 2a and the test mode signal 2e inverted.

An AND circuit 73 receives the test mode signal 2e and the external input clock 2b to take a logical product. An AND circuit 74 receives the test mode signal 2e and the external input data 2d and takes a logical product.

Reference numeral 75 is an AND circuit, which ANDs the output of the start signal 2g of the start timing signal generating circuit 80 and the output of the external start mode setting signal 2h. Reference numeral 76 is an OR circuit, which takes the logical sum of the AND circuit 75 and the mode setting register 32.

Reference numeral 80 denotes a start timing signal generating circuit, which generates a start signal 2g by a start input signal 2f and generates a start signal for setting the contents of the mode setting register 32 in the mode holding section 41 of the memory 40. To do.

2a is a system clock. 2b is an external input clock. 2c is a control signal, CA
These are S, RAS, WE, CS signals and addresses.

2d is external input data. 2e is a test mode signal. 2f is a start input signal,
This is a signal that gives the timing for generating the activation signal 2g from the activation timing signal generation circuit 80.

Reference numeral 2g is a start signal which gives a timing for loading the contents of the mode setting register 32 into the memory 40. FIG. 6 is a time chart of the second embodiment of the present invention.

The operation of the configuration of FIG. 5 will be described with reference to FIG. In the test mode, the test mode signal 2e is H
become. The H signal is the AND circuit 73 and the AND circuit 7.
4, the external input clock 2b and the external input data 2d are selected and set in the mode setting register 32. The mode setting data given from the outside is input using the external input means 23, input controlled by the mode setting input control section 24, and set in the mode setting register 32. When the mode setting data is set in the mode setting register 32, the mode test signal is set to L. The external activation mode setting signal 2h is set to H at the timing when the mode test signal becomes L.

As a result of the mode test signal becoming L, the output of the inverter 71 becomes H, and the AND circuit 72 selects the system clock 2a. The mode setting register 32 operates with the system clock. Therefore, the activation input signal 2f is externally applied, and the activation timing signal generating circuit 80 generates the activation signal 2g. Since one input 2h of the AND circuit is H, the activation signal 2g passes through the AND circuit 75 and the OR circuit 76 and is input to the memory 40. Since the start signal 2g is input to the memory 40, the contents of the mode setting register 32 are taken out, and the control signal (active at L, * CAS, * RAS, *).
The mode setting data (address) is set in the mode holding unit 41 of the memory 40 by WE, * CS. When the mode setting data is set in the memory 40, the external start mode setting signal is set to L so that the contents are not prevented from being set in the memory 40 when the mode setting register 32 is used for other than the mode setting. .

In normal operation, the test mode signal 2e is L
It is. Therefore, the external clock and external data, which are the other inputs of the AND circuit 73 and the AND circuit 74 for inputting the L signal, are not selected. On the other hand, the inverter 71
Inverts the test mode signal 2e to H and inputs it to the AND circuit 72. Therefore, the system clock 2a, which is the other input of the AND circuit 72, is selected, and the mode setting register 32 inputs the outputs 2c-1 and 2c-2 of the timing signal generation circuit 36 and the address generation circuit 37.
Then, normal mode setting data is input to the mode setting register 32.

Therefore, a start trigger signal is generated to generate a start signal from the start timing signal generation circuit 80,
Extract the contents of the mode setting register. Then, the control signal (* CAS, * RAS, * W active at L
E, * CS) sets an address, which is mode setting data, in the mode holding unit 41 of the memory 40. Therefore,
The external start mode setting signal 2h is set to L so that setting the contents of the mode setting register 32 in the memory 40 when the mode setting register 32 is used in addition to the mode setting is not hindered.

[0063]

According to the present invention, in a memory that requires mode setting, the system in which the mode setting is mounted in the memory can be set from the outside, so that the mode setting can be facilitated regardless of the operation of the system. it can. Also,
Therefore, the operability in the memory test is improved, and the efficiency of the memory test can be significantly improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention.

FIG. 2 is a diagram showing a first embodiment of the configuration of the present invention.

FIG. 3 is an explanatory diagram of a mode setting method for a memory that requires mode setting.

FIG. 4 is a diagram showing a time chart of the first embodiment of the present invention.

FIG. 5 is a diagram showing a second embodiment of the configuration of the present invention.

FIG. 6 is a diagram showing a time chart of Example 2 of the present invention.

FIG. 7 illustrates a conventional memory device that requires mode setting.

[Explanation of symbols]

 1: Memory device 2: Input means 3: Mode setting input control unit 4: Access control circuit 5: Mode setting register 6: Selection circuit 10: Memory 11: Mode holding unit

Claims (5)

[Claims] 1. A memory device that requires mode setting for access, including a mode setting register that holds mode setting data input from outside the device into which the memory is to be installed or in a state where the memory device is not installed to the device. The memory device is characterized in that the access mode of the memory can be set externally by setting the mode setting data of the mode setting register in the memory. 2. A memory device includes an access control circuit for setting a mode in a memory in a normal operation, and a selection circuit for selecting an output of the access control circuit and an output of a mode setting register. The selection circuit is a test mode signal. 2. The memory device according to claim 1, wherein the mode is set by selecting the output of the access control circuit in the normal operation and selecting the output of the mode setting register in the test mode. 3. The mode setting register holds an output from an access control circuit that sets a mode in a memory in a normal operation, and holds mode setting data given from the outside in a test. The memory device according to claim 1, wherein the mode setting data held in the register is set in the memory by a start signal. 4. The memory according to claim 1, wherein the data held in the mode setting register is control data and mode setting data necessary for setting the mode setting data in the memory. apparatus. 5. A mode setting input control section for writing data externally supplied by the input means to a mode setting register, wherein the mode setting input control section is provided.
Alternatively, the memory device according to item 4.