JPH09231350A - Image processing method and its device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To magnify a pixel in a high quality by assigning each pixel in divided pixel sections to each pixel positioned at the vertex of a magnified pixel section while maintain their relative positional relation to interpolate each pixel except for the assigned pixels. SOLUTION: At the time of inputting a source picture from another image processor, a control part 7 connects a selector 1 in the order of buffers A →B → C → D → A → B.... Then data read out of the buffer A is outputted to an output signal OUT 1 and data read out of the buffer A is outputted to OUT 2. Next, the control part 7 connects a selector 3 in the order of the buffers (A, B) → (C, D) → (A, B)→... to read the same set of buffers by respectively three times. In addition the signal of OUT 1 is latched by FF 11 and 12 and the signal of OUT 2 is latched by FF 21 and 22. An arithmetic part 5 inputs the output signals of FF 11, 12, 21 and 22 to execute five kinds of prescribed arithmetic, as the result, a selector 6 converts a 2×2 pixel on an image to a corresponding 2×2 pixel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing method and an apparatus thereof, and more particularly to an image processing method and an apparatus thereof for enlarging a binary source image in a bitmap format.

[0002]

2. Description of the Related Art A laser beam printer (LBP) is known as a printing means for a facsimile. When printing an image of the same size, it is necessary to match the image resolution with the printing resolution of the LBP itself. Conventionally, the printing resolution of LBP is 400D
Although it was about PI, it was convenient for printing the received image of the facsimile.

Taking a G4 facsimile as an example,
The resolution of the received document is 100 × 200, 200 × 2
A typical number is 00,400 × 400 DPI. If the received image is 100x200, add 4x2 to this image
If the double processing is performed, a 400 × 400 DPI image is obtained. Also, if the received image is 200 × 200, then if this image is subjected to 2 × 2 times processing, then 400 × 400.
Get DPI image. Furthermore, the received image is 400 ×
In the case of 400, a 400 × 400 DPI image is obtained by subjecting this image to 1 × 1 times processing.

If a 400 DPI LBP is used as the printing means, the image resolution can be adjusted to the LBP resolution by the simple enlargement processing of 4 × 2, 2 × 2, 1 × 1 as described above. FIG. 1 is a diagram illustrating a 2 × 2 simple enlargement process. As shown in FIG. 1, the columns are overlapped and parallel to each other. Here, it is assumed that the columns are in the sub scanning direction and the rows are in the main scanning direction.

The left side of FIG. 1 is the source image, and the right side is the enlarged destination image. A number or alphabetic symbol that indicates the position of a row or column. Rows and columns marked with a dash are duplicates of rows or columns having the same symbol. Generally, in the simple enlargement process, when the main and sub-magnifications are integers, each matrix is overlapped by the number of magnifications.

Due to the recent technological progress, the resolution of LBP has been improved, and for example, LBP of about 600 DPI has appeared. If a document received by a G4 facsimile is to be printed on an LBP of 600 DPI as in the conventional example, 100 × 200, 200 × 200, 400 × 400
6x3, 3x3, 1.5 for each DPI received document
× 1.5 times image enlargement processing is required. 4x2,2x
The image of the received original is faithfully reproduced even in the simple enlargement processing such as 2, 1 × 1, 6 × 3, 3 × 3 times.

[0007]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
When printing a 400 x 400 DPI received original using the DPI LBP, 1.5 x 1.5 times enlargement processing is required. However, as shown in Fig. 2, the processing method is based on the simple enlargement processing. If the enlargement process is performed such that the columns are overlapped every two columns and the lines are duplicated every two lines, there is a drawback that image deterioration occurs.

The left side of FIG. 2 is the source image, and the right side is the enlarged destination image. A number or alphabetic symbol that indicates the position of a row or column. Rows and columns marked with a dash are duplicates of rows or columns having the same symbol. FIG. 3 is an example of a case where a 4 × 4 pixel image is enlarged by the method of FIG. The left is the source image, and the right is the enlarged 6 × 6 pixel destination image. It is clear from this figure that granular lumps are formed. In the case of a pseudo-halftone-binarized document, this lump appears in the isolated pixels dispersed in the halftone portion of the error diffusion process to give a rough feeling, and the image quality deteriorates.

The present invention has been made in view of the above conventional example, and provides an image processing method and apparatus for performing 1.5 × 1.5 times image enlargement with high quality and a simple processing configuration. With the goal.

[0010]

In order to achieve the above object, an image processing method and apparatus according to the present invention have the following arrangement. That is, a dividing unit that divides a predetermined image into 2 × 2 pixel sections, and a vertex of a 3 × 3 pixel section while maintaining the relative positional relationship between the pixels of the 2 × 2 pixel sections that are divided by the dividing section. Based on the allocation means for allocating to each pixel located at, and each pixel located at the apex of the 3 × 3 pixel partition allocated by the allocation means, each pixel other than each pixel located at the apex of the 3 × 3 pixel partition And an interpolating means for interpolating pixels.

Another aspect of the present invention is to divide a predetermined image into 2 × 2 pixel sections and to maintain the relative positional relationship between the pixels of the 2 × 2 pixel sections divided in the dividing step. A step of assigning to each pixel located at the apex of the 3 × 3 pixel section, and a vertex of the 3 × 3 pixel section based on each pixel located at the apex of the 3 × 3 pixel section assigned in the assigning step And an interpolation step of interpolating each pixel other than each pixel located at.

[0012]

DETAILED DESCRIPTION OF THE INVENTION An image processing configuration according to an embodiment of the present invention will be described in detail below. FIG. 4 is a configuration diagram showing the image enlarging device of the embodiment. In this embodiment, image processing is performed by the raster scan method. Hereinafter, pixels arranged in the main scanning direction are called lines.

Reference numeral 1 is a selector, which distributes the serially input image signal to one of four outputs. Reference numeral 2 denotes a line buffer, which can store pixel data for 4 lines. The buffer for each 1 line is A, B,
Called C and D buffers. Each buffer has a FIFO structure capable of asynchronous writing and reading.

Reference numeral 3 is a selector. Selector 3 is A,
One of the serial image signals read and output from the B buffer and the C and D buffers is selected and used as two output signals. Reference numeral 4 denotes a pixel buffer, which is a 2 × 2 latch for two pixels output from the selector 3 on adjacent lines.
It is a flip-flop group of a matrix. A common clock (CLK
2) is entered.

Here, the output of FF11 is connected to the input of FF12, and the output of FF21 is connected to the input of FF22. Reference numeral 5 denotes a calculation unit. The arithmetic unit 5 inputs the four outputs of the pixel buffer 4 and performs five types of arithmetic operations, and outputs five types of signals as respective arithmetic results. The details of this calculation will be described later.

Reference numeral 6 denotes a selector, which selects one of the four signals output from the pixel buffer 4 and the five signals output from the arithmetic unit 5 to input a single serial image. Output as a signal. 7 is a control unit. The control unit 7 controls the blocks 1 to 6. SEL1 is a selection signal. SEL1 is an output signal of the control unit 7, and is a 2-bit selection signal for the selector 1 to connect one input to one of four outputs.

WR1 (P) is a write signal. WR1
(P) is an output signal of the control unit 7, which is commonly input to the A and B buffers of the line buffer 2. WR1
(P) becomes active at the timing of writing the 1-pixel signal into each buffer of the line buffer 2. It also includes a signal for clearing the pointer of each buffer.

WR1 (CL) is an output signal of the control unit 7 and is commonly input to the A and B buffers of the line buffer 2. WR1 (CL) is a signal that clears the internal pointers of the A and B buffers of the line buffer 2 at the L level. WR1 (P) is an output signal of the control unit 7 and is commonly input to the A and B buffers of the line buffer 2. WR1 (P) becomes active at the timing of writing the 1-pixel signal into each buffer of the line buffer 2.

WR2 (CL) is an output signal of the control unit 7 and is commonly input to the C and D buffers of the line buffer 2. WR2 (CL) is a signal that clears the internal pointers of the C and D buffers of the line buffer 2 at the L level. WR2 (P) is an output signal of the control unit 7 and is commonly input to the C and D buffers of the line buffer 2. WR2 (P) becomes active at the timing of writing one pixel signal into each buffer of the line buffer 2.

RD2 (CL) is an output signal of the control unit 7 and is commonly input to the buffers C and D of the line buffer 2. RD2 (CL) is a signal for clearing the pointers of the buffers C and D. RD2 (P) is a read signal. This is an output signal of the control unit 7 and is commonly input to the buffers C and D of the line buffer 2. RD2 is
It becomes active when one pixel signal is read from each buffer.

RD1 (CL) is an output signal of the control unit 7 and is commonly input to the buffers A and B of the line buffer 2. RD1 (CL) is a signal for clearing the pointers of the buffers A and B. RD1 (P) is a read signal. This is an output signal of the control unit 7, and is commonly input to the buffers A and B of the line buffer 2. RD2 is
It becomes active when one pixel signal is read from each buffer.

SEL2 is a selection signal. It is an output signal of the control unit 7, and is a selection signal for the selector 3 to select two sets of two input signals and connect them to two outputs. SE
L3 is a selection signal. SEL3 is an output signal of the control unit 7, and is a 4-bit selection signal for the selector 6 to select the input 9 signal and connect it to the 1 output.

VIN is a serial image input signal. C
LK1 is a clock signal that gives the timing of image transfer to the control unit 7. SYNC1 is a line synchronization input signal to the control unit 7. RQ is a line request output signal from the control unit 7. VIN, CLK1, SYNC1, R
Each signal of Q is a signal exchanged with another image processing device (not shown) (hereinafter referred to as image processing device B).

FIG. 2 is a time chart showing the operation timing of the above four signals. Referring to FIG. 2, if the line buffer 2 has a free space, the control unit outputs the L level to RQ and requests the image processing apparatus B to output the line. In response to the request, the image processing apparatus B outputs an L-level active signal for SYNC1 for one pulse in synchronization with CLK1. After the line synchronization is established, effective pixels are transferred (VIN) one pixel at a time in synchronization with each clock from the next timing of CLK1.

Next, referring to FIG. 4 again, description will be made. V
OUT is a serial image output signal for an LBP (not shown). CLK2 is an image transfer clock input from the LBP. SYNC2 is a line synchronization input signal input from the LBP. That is, VOUT, CLK
Regarding the signals 2 and SYNC2, the above three signals are signals exchanged with the LBP.

FIG. 6 is a timing chart showing the operation timing of the three signals. The SYNC 2 establishes line synchronization by outputting an L level active signal for one pulse in synchronization with CLK 2. After the line synchronization is obtained, a valid time is transferred one pixel at a time (VOUT) in synchronization with each cycle of CLK2. Then, the transferred data is printed by LBP.

The operation of this embodiment will be described below. First, the source image is input from the image processing apparatus B. When inputting the first line, the control unit 7 selects SEL so as to connect the selector 1 to the A buffer of the line buffer 2.
Output 1 signal. FIG. 7 is a timing chart showing the operation timing of writing a line in the buffer A of the line buffer 2.

WR1 (CL) input to the buffers A and B of the line buffer 2 is a signal that clears the pointers of the buffers A and B at the L level, becomes valid at the timing of SYNC1, and becomes the buffer of the line buffer 2. A, B
The internal pointer of is cleared. RD1 (P) is a write clock for the buffers A and B, and accumulates data at the rising edge.

Each time the SYNC 1 becomes active, the control section 7 causes the selector 1 to move the buffers A → B → C → D → A → B.
Connect in this order. Writing to the buffers C and D of the line buffer 2 is similar to writing to the buffers A and B, and WR1 (CL) and WR1 (P) in FIG. 7 are replaced with WR2 (CL) and WR2 (P), respectively. It is similar to

Next, the destination image is output to the LBP. The image can be output to the LBP when a line is input from the top of the page and at least two lines are input. First, the first line is LBP
SEL2 that selects the selector 2 selects the buffers A and B in the case of outputting to the buffer. FIG. 8 is a chart showing the timing of reading lines from the buffers A and B.
RD1 (CL) input to the buffer A is a signal for clearing the pointers of the buffers A and B at the L level, and S
It becomes active at the timing of YNC2 and the pointer is cleared.

RD1 (P) is a read clock for the buffers A and B, outputs data at the rising edge, and outputs 2 during transfer clock CLK2 to LBP three times.
Read at a rate of times. The data read from the buffer A is output to the output signal OUT1, and the data read from the buffer B is output to OUT2.

Each time the SYNC 2 becomes valid three times, the control unit 7 causes the selector 3 to buffer (A, B) → (C, D) →
(A, B) → ... are connected in this order, and the same set of buffers is read three times. Further, the reading of the buffers C and D is similar to the reading of the buffers A and B, and RD1 of FIG.
(CL) and RD1 (P) are respectively RD2 (CL),
It may be replaced with RD2 (P).

Next, the signal of OUT1 (the first
(Pixels on the line) are latched by FF11, and OUT2
Signal (pixel on the second line) is latched by the FF 21. The output of FF11 is latched by FF12 of the next stage,
The output of the FF21 is latched by the FF22 in the next stage. In FIG. 8, the state in which the pixels on the first line are latched is FF.
11 and the output signal of FF12. Although not shown, it goes without saying that the pixels on the second line are similarly latched by the FF 21 and the FF 22.

The calculation unit 5 includes FF11, FF12 and FF2.
1 and the output signal of the FF 22 are input to perform five types of calculations. Five kinds of signals of the calculation result are respectively given to D12 and D2.
1, D22, D23, D32. Although various calculation methods are conceivable, the following calculation is performed in the present embodiment. Here, & means AND and # means OR. D12 = FF11 & FF12 D21 = FF11 & FF21 D23 = FF12 & FF22 D32 = FF21 & FF22 D22 = (FF11 & FF22) # (FF21 & FF2)
1) FIG. 8 and FIG. 9 show the state of the SEL3 signal output by the control unit 7. The selector 6, depending on the state of SEL3,
Select as follows. here,! Means the inversion of the following signal.

VOUT = FF11 & [! SEL3 (R) & SEL3 (L1) &! SEL3 (L2) &! SEL3 (L3)] # D12 & [SEL3 (R) & SEL3 (L1) &! SEL3 (L2) &! SEL3 (L3)] # FF12 & [SEL3 (R) & SEL3 (L1) &! SEL3 (L2) &! SEL3 (L3)] # D21 & [! SEL3 (R) &! SEL3 (L1) & SEL3 (L2) &! SEL3 (L3)] # D22 & [SEL3 (R) &! SEL3 (L1) & SEL3 (L2) &! SEL3 (L3)] # D23 & [SEL3 (R) &! SEL3 (L1) & SEL3 (L2) &! SEL3 (L3)] # FF21 & [! SEL3 (R) &! SEL3 (L1) &! SEL3 (L2) & SEL3 (L3)] # D32 & [SEL3 (R) &! SEL3 (L1) &! SEL3 (L2) & SEL3 (L3)] # FF22 & [SEL3 (R) &! SEL3 (L1) &! SEL3 (L2) & SEL3 (L3)] Next, Figure 10 shows the source image. 2 × 2 pixels are converted into corresponding 3 × 3 pixels on the destination image. According to the description of the above embodiments, the correspondence between the source pixel and the destination pixel in FIG. 10 is as follows.

D11 = S11 D12 = S11 & S12 D13 = S12 D21 = S11 & S21 D22 = (S11 & S22) # (S12 & S21) D23 = S11 & S21 D31 = S21 D32 = S21 & S22 D33 = S22 FIG. It is a figure showing the case where a source image is expanded by the image processing of this Embodiment. Unlike the conventional example, the slanted line is reproduced neatly.

As described above, the effects peculiar to the present embodiment are as follows: 1) Since it can be realized by a relatively simple circuit, the circuit scale can be small. 2) Significantly improve image quality deterioration after 1.5 × 1.5 enlargement. 3) If the control method of the control unit is changed, an integer multiple enlargement process can be performed as it is, so that there is a remarkable effect such that one type of image processing device for LBP resolution conversion of 600 DPI is effective. <Other Embodiments> Other embodiments of the enlargement processing will be described below. The present embodiment is an example of processing by software.

For the sake of convenience, it is assumed that the source image is data in which one pixel has one address and is one-dimensionally stored in the memory in the raster scan format. Here, in a system in which one address is one byte, one pixel is one byte of data. One line of the source image is N pixels, the total number of lines is L lines,
If the stored start address is SPTR, S1
The values of 1, S12, S21, S22 are expressed as follows.

S11 = [SPTR + 2 * N * (Y + 0) + 2 * X + 0] S12 = [SPTR + 2 * N * (Y + 0) + 2 * X + 1] S21 = [SPTR + 2 * N * (Y + 1) + 2 * X + 0] S22 = [SPTR + 2 * N * (Y + 1) + 2 * X + 1] Y is a parameter from 0 to (L / 2−1 ) Between +1.

X is a parameter, and Y is fixed and is incremented by 1 from 0 to (N / 2-1). [] Represents the data stored at the address in parentheses. S11, S12, S21 and S22 are determined for each X and Y, and D11, D12, D13 and D2 are set in the same manner as the above-mentioned embodiment.
1, D22, D23, D31, D32, D33 are determined. If the head address for storing the destination image is DPTR, it is stored as follows.

[DPTR + 3 * N * (Y + 0) + 3 * X + 0] = D11 [DPTR + 3 * N * (Y + 0) + 3 * X + 1] = D12 [DPTR + 3 * N * (Y + 0) + 3 * X + 2] = D13 [DPTR + 3 * N * (Y + 1) + 3 * X + 0] = D21 [DPTR + 3 * N * (Y + 1) + 3 * X + 1] = D22 [DPTR + 3 * N * (Y + 1) + 3 * X + 2] = D23 [DPTR + 3 * N * (Y + 2) + 3 * X + 0] = D31 [DPTR + 3 * N * (Y + 2) + 3 * X + 1] = D32 [DPTR + 3 * N * (Y + 2) + 3 * X + 2] = D33 FIG. 12 shows the image processing described above. It is a figure which shows the structural example of an information processing apparatus in the case of performing by software.

The CPU 200 controls the entire information processing apparatus by reading, interpreting and executing various control programs stored in the memory 202. Memory 202
In advance, a program corresponding to the above-mentioned processing is stored. Further, it is assumed that the memory 202 stores image data to be processed in advance.

The keyboard 203 and pointing device 204 input commands and data. The display monitor 201 displays processing results of the CPU 200 and commands and data input from the keyboard 203 and pointing device 204. As described above, as a peculiar effect of the present embodiment, 1) it can be realized by relatively simple processing, so that the program code is small. 2) the algorithm is simple, so that it is processed at high speed. 3) 1 There is a remarkable effect such as a great improvement in image deterioration after being enlarged by 5 × 1.5.

The present invention may be applied to either a system composed of a plurality of devices or an apparatus composed of a single device. Further, an object of the present invention is to provide a storage medium storing a program code of software for realizing the functions of the above-described embodiments to a system or an apparatus,
Computer (or CP) of the system or device
It is needless to say that it is also achieved by (U or MPU) reading and executing the program code stored in the storage medium.

In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention. As a storage medium for supplying the program code, for example, a floppy disk, a hard disk, an optical disk, a magneto-optical disk, C
A D-ROM, a CD-R, a magnetic tape, a non-volatile memory card, a ROM, etc. can be used.

When the computer executes the readout program code, not only the functions of the above-described embodiment are realized, but also the OS (Operating System) running on the computer based on the instruction of the program code. ) May perform some or all of the actual processing, and the processing may realize the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written into a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, based on the instructions of the program code, It goes without saying that the CPU included in the function expansion board or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

When the present invention is applied to the above storage medium, the storage medium stores the program code corresponding to the above-described processing. As explained above,
According to the present embodiment, with simple control, the image of 1.5 ×
1.5 times expansion is possible. Also, with a simple circuit,
1.5 × 1.5 times magnification is possible. Furthermore, 1.5
× 1.5 Image deterioration after zooming can be significantly improved.

The present embodiment is particularly suitable for enlargement processing when printing a received image of a facsimile.

[0050]

As described above, according to the present invention,
Image enlargement of 1.5 × 1.5 times can be performed with high quality and a simple processing configuration.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a conventional 2 × 2 enlargement method of image enlargement processing.

FIG. 2 is a diagram illustrating a 1.5 × 1.5 enlargement method of a conventional image enlargement process.

FIG. 3 is a diagram for explaining problems of conventional processing.

FIG. 4 is a configuration diagram showing an image enlarging device of the present embodiment.

FIG. 5 is a timing chart showing operation timing of image input according to the present embodiment.

FIG. 6 is a timing chart showing the operation timing of image output according to the present embodiment.

FIG. 7 is a timing chart showing the write timing of the line buffer according to the present embodiment.

FIG. 8 is a chart showing the timing of reading the line buffer according to the present embodiment.

FIG. 9 is a timing chart showing the timing of a selection signal output by the control unit of the present embodiment.

FIG. 10 is a diagram showing a correspondence between a source image piece and a destination image piece according to the present embodiment.

FIG. 11 is a diagram illustrating an example of a processing result according to the present embodiment.

FIG. 12 is a hardware configuration diagram for executing the processing of the present embodiment by software.

Claims (6)

[Claims] 1. A dividing unit that divides a predetermined image into 2 × 2 pixel sections, and 3 × 3 pixels while maintaining the relative positional relationship between the pixels of the 2 × 2 pixel sections divided by the dividing section. Based on the assigning means assigned to each pixel located at the apex of the partition and each pixel located at the apex of the 3 × 3 pixel partition assigned by the assigning means, each pixel located at the apex of the 3 × 3 pixel partition And an interpolating unit that interpolates each pixel other than the above. 2. The image processing apparatus according to claim 1, wherein the predetermined image is a binary image. 3. The interpolation means is a logical operation based on the pixels D ₁₁ , D ₁₃ , D ₃₁ , D ₃₃ located at the vertices of the 3 × 3 pixel section assigned by the assigning means: D ₁₂ = D ₁₁・ D ₁₃ D ₂₁ = D ₁₁・ D ₃₁ D ₃₂ = D ₃₁・ D ₃₃ D ₂₃ = D ₁₃・ D ₃₃ D ₂₂ = D ₁₁・ D ₃₃ + D ₁₃・ D ₃₁ Based on the 3 × 3 pixel section The image processing apparatus according to claim 2, wherein each pixel D ₁₂ , D ₂₁ , D ₂₂ , D ₂₃ , and D ₃₂ other than each pixel located at the apex of is determined. 4. A dividing step of dividing a predetermined image into 2 × 2 pixel sections, and 3 × 3 pixels while maintaining the relative positional relationship of each pixel of the 2 × 2 pixel section divided in the dividing step. Based on the allocation step of allocating to each pixel located at the apex of the partition and each pixel located at the apex of the 3 × 3 pixel partition allocated in the allocation step, each pixel located at the apex of the 3 × 3 pixel partition And an interpolation step of interpolating each pixel other than the above. 5. The image processing method according to claim 4, wherein the predetermined image is a binary image. 6. The logical operation based on the pixels D ₁₁ , D ₁₃ , D ₃₁ , D ₃₃ located at the vertices of the 3 × 3 pixel section assigned in the assigning step: D ₁₂ = D ₁₁・ D ₁₃ D ₂₁ = D ₁₁・ D ₃₁ D ₃₂ = D ₃₁・ D ₃₃ D ₂₃ = D ₁₃・ D ₃₃ D ₂₂ = D ₁₁・ D ₃₃ + D ₁₃・ D ₃₁ Based on the 3 × 3 pixel section The image processing method according to claim 5, wherein the pixels D ₁₂ , D ₂₁ , D ₂₂ , D ₂₃ , and D ₃₂ other than the pixels located at the vertices of are obtained.