JPH09231134A - Memory control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the occupation time of a host bus. SOLUTION: For back writing by single writing, single write data is latched by a single-write buffer 14a and back write data is latched by a back write buffer 4c. A data selecting and merging circuit 14b merges the back write data and single write data and outputs them by every 128 bits to a memory 5 through an input/output buffer 14b. A memory control signal generating circuit 4i generates a memory control signal to write the data in the memory 5. For back writing by single reading, the back write data is latched by the back write latch 4c. The data selecting and merging circuit 14b writes the back write data by every 128 bits in the memory 5 through the input/output buffer 14b. A data selecting circuit 14d, on the other hand, selects data from a burst data buffer 4c and outputs it to the host bus 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control circuit in a multiprocessor system having a write-back type cache.

[0002]

2. Description of the Related Art In recent years, it has become commonplace to add a cache to a processor in a computer, and most processors include a primary cache. High-end computers such as servers are equipped with a secondary cache to improve performance. Also,
A multiprocessor system has been realized for further performance improvement. In the multiprocessor system, various protocols are adopted in order to maintain the consistency between the caches. Among them, the MESI protocol is often used. is there. Among the MESI protocols, cache management is roughly divided into a write-through method and a write-back method, and most systems use the write-back method. Handling the write-back is the most important technology when the write-back method is adopted. Conventionally, a bus control system and a memory control circuit in a multiprocessor system having a cache device adopting a write-back system have the same configuration as a single processor system.

FIG. 2 is a functional block diagram showing a configuration example of a conventional memory control circuit. When writing single data, the data from the host bus 3 side is latched by the write buffer 4c under the control of the controller 4j and the buffer / data selection control circuit 4e, and then selected by the data selection circuit 4d to be input / output buffer. Through 4b,
It is written in the memory 5 under the control of the controller 4j and the memory control signal generation circuit 4i. At the time of writing burst data, the write data of four consecutive transmissions from the host bus 3 side is latched in the write buffer 4c by the control of the controller 4j and the buffer data selection control circuit 4e, and then sequentially selected by the data selection circuit 4d. Then, the data is written to the memory 5 through the input / output buffer 4b under the control of the controller 4j and the memory control signal generation circuit 4i. When reading single data, the data read from the memory 5 under the control of the controller 4j and the memory control signal generation circuit 4i is latched in the read buffer 4f under the control of the controller 4j and the buffer / data selection control circuit 4h. Then, it is selected by the data selector 4g and output to the host bus 3 through the input / output buffer 4a.

When reading burst data, the data read from the memory 5 under the control of the controller 4j and the memory control signal generation circuit 4i is stored in the read buffer 4f under the control of the controller 4j and the buffer / data selection control circuit 4h. After the data is latched, it is selected by the data selector 4g and is output to the host bus 3 through the input / output buffer 4a in four consecutive transmissions. At the time of write back for writing, the write back data is latched in the write buffer 4c by the control of the controller 4j and the data buffer selection control circuit 4e, and then the data selection circuit 4
The data is sequentially selected by d and written in the memory 5 through the input / output buffer 4a under the control of the controller 4j and the memory control signal generation circuit 4i. After that, the write-back data is latched in the write buffer 4c under the control of the controller 4j and the buffer / data selection control circuit 4e, then selected by the data selection circuit 4d, and passed through the input / output buffer 4b to the controller 4j and the memory control signal. It is written in the memory 5 under the control of the generation circuit 4i.

At the time of write back for a single read, the controller 4j and the data buffer selection control circuit 4
After the write-back data is latched in the write buffer 4c by the control of e, it is sequentially selected by the data selection circuit 4d and passed through the input / output buffer 4a to the controller 4
It is written in the memory 5 under the control of j and the memory control signal generation circuit 4i. After that, single data is read from the memory 5 under the control of the controller 4j and the memory control signal generation circuit 4i, and latched in the read buffer 4f under the control of the controller 4j and the buffer / data selection control circuit 4h. It is selected by the selector 4g and output to the host bus 3 through the input / output buffer 4a. At the time of write back for burst read, the controller 4j and the data buffer selection control circuit 4
After the write-back data is latched in the write buffer 4c by the control of e, it is sequentially selected by the data selection circuit 4d and passed through the input / output buffer 4a to the controller 4
It is written in the memory 5 under the control of j and the memory control signal generation circuit 4i. After that, single data is read from the memory 5 under the control of the controller 4j and the memory control signal generation circuit 4i, and latched in the read buffer 4f under the control of the controller 4j and the buffer / data selection control circuit 4h. It is selected by the selector 4g and is output to the host bus 3 by four continuous transmissions through the input / output buffer 4a.

[0006]

However, the conventional memory control circuit has the following problems. When a write-back occurs in the conventional memory control circuit, the write-back data is written back to the memory 5, and then the write-back data is read or the write-back data is updated, so that the occupied time of the memory 5 and the host bus 3 becomes long, As an example in which the overhead of data transfer is large, the operation in a processor and a cache having a 64-bit data processing unit and a burst transfer function of 4 consecutive transmissions and a multiprocessor system having a 128-bit memory bandwidth is timed. This will be explained using a chart. FIG. 3 is a time chart showing write back for the single write in FIG.

(A) At the time of write-back for writing As a result of a write request from a certain processor 1-i, the cache 2-i drives the address to the address bus 3-AD in order to perform a single write to the memory 5. The controller 4j asserts the signal ADRY # indicating that the address has been confirmed, and asserts the signal DRDY # indicating that the data is accepted. Each cache 2-j (j ≠ i) and processor 1-j other than the processor that started the cycle for that address perform snooping, and the data is cached in another cache 2-n (n ≠ i).
The signal is asserted by the signal QHTM # indicating that the modification line of the cache memory is hit, and the signal WBDS # indicating that the write-back is ready is used. The controller 4j uses a signal DRDY # to indicate that the backlight data is received. Under the control of the controller 4j and the buffer / data selection control circuit 4e, the data write back data D1 to D4 are latched in the write buffer 4c. Then, under the control of the buffer / data selection control circuit 4e, the data selection circuit 4d selects the backlight data from the write buffer 4c for every 128 bits, and writes it in the memory 5 under the control of the memory control signal generation circuit 4i. After that, single data D2
Is latched in the write buffer 4c, the data is selected by the data selection circuit 4d, and the single data D2 is written in the memory 5 through the input / output buffer 4b. In this case, the cache 2-i that tried to perform a single write
Will be kept waiting until the write-back data is written in the memory 5.

(B) At Write Back for Single Read FIG. 4 is a time chart showing write back for single read in FIG. A processor 1-
cache 2-i as a result of a read request from i
Drives the address to the address bus 3-AD in an attempt to read the memory 5 single. Each cache 2-j (i ≠ j) other than the processor 1-i that started the cycle for that address and the processor 1-j perform snoop, and the data is cached in another cache 2-n (n ≠).
i) is asserted by the signal QHTM # indicating that the modify line of the cache memory is hit, and is indicated by using the signal WBDS # indicating that the write back is ready. The controller 4j uses a signal DRDY # to indicate that the backlight data is received. Under the control of the buffer / data selection control circuit 4, the data writeback data D1 to D4 are latched in the write buffer 4c. Then, under the control of the buffer / data selection control circuit 4e, the data selection circuit 4d selects from the write buffer 4c for every 128 bits, and the memory control signal generation circuit 4i.
Write to the memory 5 under the control of. Single read from the memory 5 is performed under the control of the memory control signal generation circuit 4i, and single read data D1 is latched in the read buffer 4f under the control of the buffer / data selection control circuit 4h. Under the control of the buffer / data selection control circuit 4h, the data selection circuit 4g selects from the read buffer 4f and passes through the input / output buffer 4b to output the data bus 3-D.
Output to B. Also in this case, the cache 2-i, which is going to perform the single read, has to wait until the write-back data is written in the memory 5.

(C) At the time of write back for burst read FIG. 5 is a time chart showing the write back for burst read in FIG. A processor 1-
cache 2-i as a result of a read request from i
Drives the address to the address bus 3-AD in an attempt to read the memory 5 single. Each cache 2-j (i ≠ j) other than the processor 1-i that started the cycle for that address and the processor 1-j perform snoop, and the data is cached in another cache 2-n (n ≠).
i) is asserted by the signal QHTM # indicating that the modify line of the cache memory is hit, and is indicated by using the signal WBDS # indicating that the write back is ready. The controller 4j uses a signal DRDY # to indicate that the backlight data is received. Under the control of the buffer / data selection control circuit 4e, the data writeback data D1 to D4 are latched in the write buffer 4c. Then, under the control of the buffer / data selection control circuit 4e, the data selection circuit 4d selects from the write buffer 4c for every 128 bits, and the memory control signal generation circuit 4
Write to the memory 5 under the control of i. Burst read is performed from the memory 5 under the control of the memory control signal generation circuit 4i, and burst read data D1 to D4 are latched in the read buffer 4f under the control of the buffer / data selection control circuit 4h. Buffer / data selection control circuit 4
Under the control of h, the data selection circuit 4g selects from the read buffer 4f for every 64 bits, and the input / output buffer 4b.
Through the data bus 3-DB, the burst data D1 to
D4 is sequentially output. In this case as well, the cache 2-i that tried to perform the burst read is kept waiting until the write-back data is written in the memory 5.

[0010]

According to the present invention, in order to solve the above-mentioned problems, in a memory control circuit for controlling read / write of data from / to a memory of a plurality of write-back type caches, the cache is a single data unit. If the data hits the modify line of another cache when trying to write or single read, the first buffer that receives the write-back data on the modify line hit by the other cache from the other cache and retains it. And a second buffer that receives and holds data to be single-written by the cache from the cache. And
When writing back the data on the modify line for the single write of the cache, the single write data held in the second buffer with respect to the write back data held in the first buffer is written. For the same address in the memory, select the data to be single-written instead of the data in the write-back data, select the write-back data other than the write-back data having the same address as the data, and select the data When outputting according to the address in the memory and writing back the data on the modify line for the single read of the cache, the write-back data held in the first buffer is according to the address in the memory,
A data selection / merge circuit for selecting and outputting is provided. Further, at the time of write back for the single read, a data selection circuit for selecting and outputting the data held in the first buffer according to the address of the data to be single read in the memory, and for the memory And a memory control signal generation circuit for generating a memory control signal for read / write.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment FIG. 1 is a functional block diagram of a memory control circuit according to a first embodiment of the present invention, in which elements common to those in FIG. Attached. The memory control circuit of the first embodiment is different from the conventional memory control circuit in that when the backlight is for a single write, the backlight data and the single write data are merged and written in the memory. In the case of backlight for single read or burst read, the data of the backlight is directly output from the buffer to the cache. As shown in FIG. 1, the memory control circuit 14 according to the first embodiment of the present invention includes an input / output buffer 4a on the host bus 3 side, an input / output buffer 4b on the memory 5 side, and a burst data buffer (first buffer). 4c, a single data buffer (second buffer) 14a, a data selection / merge circuit 14b, a buffer / data selection control circuit 14c,
A data buffer 4f, a data selection circuit 14d, a buffer / data selection control circuit 14e, a memory control signal generation circuit 4i, and a controller 14f are provided.

The memory control circuit 14 is connected to the cache 2-i (i = 1 to n) via the host bus 3 and to the memory 5 via the data bus 3. The cache 2-i is connected to the processor 1-i. The input / output buffer 4a is the data bus 3-D of the host bus 3.
B. The output of the input / output buffer 4a is connected to the burst data buffer 4c and the input of the single data buffer 14a. The output of the burst data buffer 4c is connected to the inputs of the data selection / merge circuit 14b and the data selection circuit 14d. The output of the single data buffer 14a is connected to the input of the data selection / merge circuit 14b. The output of the buffer / data selection control circuit 14c is connected to the clock inputs of the burst data buffer 4c and the single data buffer 14a and the selection signal input of the data selection / merge circuit 14b. The output of the data selection / merge circuit 14b is connected to the input of the input / output buffer 4b. The output of the input / output buffer 4b is connected to the data input of the memory 5 and the input of the data buffer 4f. The output of the data buffer 4f is connected to the input of the data selection circuit 14d.

The output of the buffer / data selection control circuit 14e is connected to the clock input of the data buffer 4f and the selection signal input of the data selection circuit 14e. The output of the data selection circuit 14d is connected to the input of the input / output buffer 4a. The output of the input / output buffer 4a is connected to the data bus 3-DB. The memory control signal generation circuit 4i is connected to the address bus 3-AD. The output of the memory control signal generation circuit 4i is connected to the input of the memory 5. Control line 3-CTL of host bus 3
The address bus 3-AD is connected to the controller 14f. The output of the controller 14f is a buffer
It is connected to the inputs of the data selection control circuits 14c and 14e and the memory control signal generation circuit 4i. Processor 1
-I has, for example, a burst transfer mechanism of four consecutive transmissions with a data width of 64 bits. The cache 2-i has, for example, a burst transfer mechanism and a bus control circuit for four consecutive transmissions with a data width of 64 bits. The host bus 3 is
For example, it has a 64-bit wide data bus 3-DB, a 32-bit wide address bus 3-AD, and a control line 3-CTL. The memory 5 is composed of a plurality of chips, for example, a 128-bit width data signal, an 11-bit width address signal, a signal RAS #, a signal CAS #, and a signal WE.
#, A DRAM input to the signal OE #.

The input / output buffer 4a is a buffer for inputting / outputting 64-bit wide data to / from the host bus 3. The input / output buffer 4b is a buffer for inputting / outputting data of 128-bit width to / from the memory 5. The burst data buffer 4c is, for example, a 64-bit × 4 buffer. The single data buffer 14a is, for example, a 64-bit buffer. The data selection / merge circuit 14b receives the selection signal from the buffer / data selection control circuit 14c and inputs it to the burst data buffer 4c.
And a circuit for selecting an input of the single write buffer 14a and an output line of the single write buffer 14a. In accordance with an instruction from the controller 14f, the buffer / data selection control circuit 14c controls the timing at which the burst data buffer 4c and the single data buffer 14a latch data, and a data input selection signal and an output destination of the data selection / merge circuit 14b. Is a circuit for generating the selection signal of.

The data buffer 4f is a buffer of 64 bits × 4 structure. The data selection circuit 14d receives the selection signal from the buffer / data selection control circuit 14e and receives the burst data buffer 4c and the data buffer 4f.
This is a circuit for selecting 64 bits from and. The buffer / data selection control circuit 14e is a circuit that generates a selection signal for selecting the input of the burst data buffer 4c and the burst data buffer 4f according to an instruction from the controller 14f. The memory control signal generation circuit 4i
It is a circuit that generates a memory control signal for reading / writing to / from the memory 5 according to an instruction from the controller 14f. The controller 14f is a circuit that controls the buffer / data selection control circuits 14c and 14e, the memory control signal generation circuit 4i, and the like in order to synchronize read / write between the memory 5 and the cache 2-i. Hereinafter, the operation of FIG. 1 will be described.

(A) Single write When the data to be single-written by the processor 1-i misses in the cache 2-i and is single-written to the memory 5, the cache 2-i will write the single data. Drive the address to the address bus 3-AD. The controller 14f asserts a signal indicating that the address has been confirmed. For that address, the processor 1 that initiated the cycle
The cache 2-j other than i (j ≠ i) and the processor 1-j perform snooping, and the cache 2-i that started the cycle outputs data to the data bus 3-DB without waiting for the result of snooping. To do. The buffer / data selection control circuit 14c outputs a signal indicating the timing of latching the single write data in the latch single data buffer 14a according to an instruction from the controller 14f. Then, the single data is latched in the single data buffer 14a.

If the line containing the single write data is not hit in any cache 2-j (j ≠ i), the signal indicating that the modify line is hit is negated. The buffer / data selection control circuit 14c follows the instruction of the controller 14f,
The selection signal for selecting the output of the single write buffer 14a and the selection signal for selecting the output line of the data selection / merge circuit 14b are sent to the data selection / merge circuit 14b according to the value of the [3: 3] bits of the address of the data. Output. The data selection / merge circuit 14b selects single data in accordance with the selection signal from the buffer / data selection control circuit 14c, and outputs the designated input / output buffer 4b.
The single data is output to the output destination of. The single data is output to the data line of the memory 5 through the input / output buffer 4b. The memory control circuit 4i sequentially generates and outputs a write control signal, a row control signal, an address, and a column control signal to the memory 5 according to the value of the [3: 3] bit of the address of the data according to the instruction of the controller 14f. Then, the memory 5 writes the single data.

(B) When writing burst data from the burst write cache 2-i to the memory 5, the address is driven to the address line 3-AD of the host bus 3. The controller 14f asserts a signal indicating that the address is confirmed, and asserts a signal indicating that the data is accepted. The cache 2-i that started the cycle is data D of four consecutive transmissions.
1, D2, D3, D4 are sequentially output to the data bus 3-DB. The buffer / data selection control circuit 14c outputs a signal indicating the timing of latching to the burst data buffer 14a according to an instruction from the controller 14f. The burst data D1, D2, D3, D4 are sequentially latched in the burst data buffer 14a. The buffer / data selection control circuit 14c outputs a selection signal for selecting the output of the burst data buffer 14a to the data selection / merge circuit 14b. Data selection / merge circuit 14
In accordance with a selection signal from the buffer / data selection circuit 14c, b inputs data from the burst data buffer 4c every 128 bits and outputs it to the input / output buffer 4b. The burst write data D1, 2, D3, 4 are sequentially output to the data line of the memory 5 through the input / output buffer 4b. The memory control signal generation circuit 4i follows the write control signal, in accordance with the instruction from the controller 14f.
A row control signal, an address, and a column control signal are sequentially generated and output. The memory 5 sequentially writes burst data.

(C) Single read When the data that the processor 1-i is about to single read misses in the cache 2-i and the single data is read from the memory 5, the cache 2-i.
Drives an address to the address bus 3-AD to read / write single data. For that address, a cache 2-j (j ≠ i) other than the processor 1-i that started the cycle and a processor 1-j
Do snoop. Which cache 2-j (j ≠ i)
Even if the line including the single write data does not hit in the above, since the signal indicating that the modify line is hit is negated, the memory control signal generation circuit 4i follows the instruction from the controller 14f, Row control signal, address,
The column control signals are sequentially generated and output. The memory 5 is
Read single data according to the address. The read data is latched in the input / output buffer 4b.
The buffer / data selection control circuit 14e outputs a signal indicating the timing of latching the data of the input / output buffer 4b in the data buffer 4f according to the instruction of the controller 14f. Single read data is latched in a predetermined buffer area of the data buffer 4f. The buffer / data selection control circuit 14e outputs a selection signal for selecting a 64-bit buffer area input from the data buffer 4f having a 64 × 4 bit structure, according to the value of the [4: 3] bits of the address of the single read data. . The data selection circuit 14d receives the 64-bit single read data via the input / output buffer 4a and the data bus 3-D according to the selection signal from the buffer / data selection control circuit 14e.
Output to B.

(D) Burst read When the data to be burst read by the processor 1-i misses in the cache 2-i and the burst data is read from the memory 5, the cache 2-i is read.
Drives an address onto address bus 3-AD in an attempt to read burst data. For the address, the cache 2-j (j ≠ i) and the processor 1-j other than the processor 1-i that started the cycle perform snooping. If the line containing the single write data is not hit in any of the caches 2-j (j ≠ i), the signal indicating that the modify line is hit is negated. Follow the instructions from 14f
A read control signal, a row control signal, an address, and a column control signal are sequentially generated and output. The memory 5 reads the burst data according to the address. The read burst data is latched in the input / output buffer 4b.
The buffer / data selection control circuit 14e outputs a signal indicating the timing of latching the burst data in the data buffer 4f in accordance with the instruction from the controller 14f.
The burst read data is latched in the data buffer 4f. The buffer / data selection control circuit 14e is 64 ×
A selection signal is output so as to sequentially select every 64 bits input from the 4-bit data buffer 4f. The data selection circuit 14d is the buffer / data selection control circuit 1
In accordance with the selection signal from 4e, burst read data is output every 64 bits via the input / output buffer 4a to the data bus 3-DB in four consecutive transmissions.

(E) Write Back for Single Write FIG. 6 is a time chart showing write back for single write in FIG. Hereinafter, the operation of the memory control circuit 14 at the time of write back for a single write will be described with reference to FIG. As shown in FIG.
When the data to be single-written by the processor 1-i misses in the cache 2-i and is single-written to the memory 5, the cache 2-i asserts the signal AS # in an attempt to write the single data, Drive address to address bus 3-AD.
The controller 14f asserts the signal ADRY # indicating that the address has been confirmed. For the address, the cache 2-j (j ≠ i) and the processor 1-j other than the processor 1-i that started the cycle perform snooping, and the cache 2-i that starts the cycle outputs the result of the snooping. Without waiting, the signal SBSYi # is asserted to output the data D2 to the data bus 3-DB. The buffer / data selection control circuit 14c follows the instruction from the controller 14f and outputs the single data buffer 1
4a outputs a signal indicating the timing of latching. The single data D2 is latched in the single data buffer 14a.

The other cache 2-j (j ≠ i) determines whether or not the single write data hits the modify line. And it is assumed that the cache 2-n hits the modify line. Cache 2-n
Asserts the signal SBSYn #, asserts that the modified line has been hit with the signal QHTM #, and indicates that the write-back data is ready by the signal WBDS #.
It is shown using. Then, the write back data D1 to D4
Are sequentially output to the data bus 3-DB. Controller 1
4f indicates that the data is accepted by using the signal DRDY #. The controller 14f instructs the buffer / data selection control circuit 14c to latch the burst write data in the burst write buffer 4c according to the signal WBDS #. Buffer / data selection control circuit 14c
Outputs a signal indicating the timing of sequentially latching the backlight data D1 to D4 input every 64 bits in the burst data buffer 4c according to an instruction from the controller 14f. Backlight data D1 to D
4 is a burst data buffer 4 of 64 × 4 bit configuration
It is sequentially latched to c. According to the instruction from the controller 14f, the buffer / data selection control circuit 14c has an address on the same memory 5 as the output of the single write buffer 14a and the single write data D2 from the [4: 3] bits of the address of the single write data. A selection signal for selecting the output of the burst data buffer 4c other than the data and the output line of the single write data (the output line of 0 to 63 bits of the output line of 128 bit width or the output line of 64 to 127 bits) is output.

The data selection / merge circuit 14b selects from the output of the burst write buffer 14 and the output of the single write buffer 14c in accordance with the selection signal from the buffer / data selection circuit 4c, and the buffer / data selection circuit 4c selects it. 128 bits are selected and output to the designated output line. Data selection / merge circuit 14b
The 128-bit output from is output to the data line MD [127: 0] of the memory 5 through the input / output buffer 4b. As a result, the backlight data D1 to D4 and the single write data D2 are merged to form the 128-bit backlight data D1 and the single write data D.
2. Backlight data D3 and D4 are sequentially selected /
It is output from the merge circuit 14b. The memory control signal generation circuit 4i follows the write control signal WE # and the row control signal RA according to an instruction from the controller 14f.
S #, address MAB [10: 0], column control signal C
The AS # is sequentially generated and output to the memory 5. Memory 5
Writes the data. In this case, the cache 2-i trying to perform the single write does not have to wait until the write-back data is written in the memory 5, and the writing to the memory 5 is completed only once.

(F) Write Back for Single Read FIG. 7 is a time chart showing write back for single read in FIG. Hereinafter, the operation of the memory control circuit 14 at the time of write back for single read will be described with reference to FIG. 7. As shown in FIG.
When the data that the processor 1-i is trying to read from a single memory is a mishit in the cache 2-i and is single-read to the memory 5, the cache 2-i asserts the signal AS # to read the single data, Drive address to address bus 3-AD.
The controller 14f asserts the signal ADRY # indicating that the address has been confirmed. For the address, the cache 2-j (j ≠ i) and the processor 1-j other than the processor 1-i that started the cycle perform snooping. The cache 2-j (j ≠ i) determines whether the single read data hits the modify line. And it is assumed that the cache 2-n hits the modify line. The cache 2-n asserts the signal SBSYn #, asserts that the modify line has been hit with the signal QHTM #, and uses the signal WBDS # to indicate that the write-back data is ready. Then, the write back data D1 to D4 are sequentially output to the data bus 3-DB.

The controller 14f uses a signal DRDY # to indicate that it accepts data. Controller 1
4f instructs the buffer / data selection control circuit 14c to latch the burst write data in the burst write buffer 4c according to the signal WBDS #. In accordance with an instruction from the controller 14f, the buffer / data selection control circuit 14c outputs a signal indicating the timing of sequentially latching the backlight data D1 to D4 input every 64 bits in the burst write buffer 4c.
The backlight data D1 to D4 are sequentially latched in the burst data buffer 4c having a 64 × 4 bit structure. The buffer / data selection control circuit 14c is the controller 1
According to an instruction from 4f, a selection signal is output to the data selection / merge circuit 14b so that the output of the 64-bit × 4 burst data buffer 4c is sequentially selected and output every 128 bits. The data selection / merge circuit 14b is
The output of the 64-bit × 4-bit burst data buffer 4c is set to 1 in accordance with the selection signal from the controller 14c.
It is sequentially selected every 28 bits and output to the output line.

The memory control signal generation circuit 4i follows the write control signal WE according to the instruction from the controller 14f.
#, Row control signal RAS #, address MAB [10:
0] and column control signal CAS # are sequentially generated and output to the memory 5. The memory 5 writes the write back data. On the other hand, the buffer / data selection control circuit 14e
According to the instruction from the controller 14f, the address [4: 3] of the single read data D1 is set as soon as the write-back data is latched in the burst data buffer 4c.
From the bits, a selection signal for instructing which 64-bit of the output of the burst data buffer 4c of 64 bits × 4 is selected is output. The data selection circuit 14d selects 64 bits from the burst data buffer 4c according to the selection signal from the buffer / data selection control circuit 14e, and outputs the single data D through the input / output buffer 4a.
1 is output to the data bus 3-DB. In this case, read data is output to the data bus 3-DB in parallel with writing the write-back data to the memory 5. Therefore, since the read is not performed directly in the memory 5, it is not necessary to wait for the write-back data to be written in the memory, and the write-back data is output to the host bus 3, and the occupied time of the memory 5 in the two cycles of write and read is also large. Instead, it only takes the time to complete one write cycle.

(F) Writeback for Burst Read FIG. 8 is a time chart showing writeback for burst read in FIG. Hereinafter, the operation of the memory control circuit 14 at the time of write back for burst read will be described with reference to FIG. As shown in FIG.
When the data to be single-read by the processor 1-i misses in the cache 2-i and is single-read to the memory 5, the cache 2-i asserts the signal AS # in an attempt to read the single data. , Drive address to address bus 3-AD. The controller 14f asserts the signal ADRY # indicating that the address has been confirmed. For the address, the cache 2-j (j ≠ i) and the processor 1-j other than the processor 1-i that started the cycle perform snooping. The cache 2-j (j ≠ i) determines whether the single read data hits the modify line. And it is assumed that the cache 2-n hits the modify line. The cache 2-n asserts the signal SBSYn #, asserts that the modify line has been hit with the signal QHTM #, and uses the signal WBDS # to indicate that the write-back data is ready. Then, the write back data D1 to D4 are sequentially output to the data bus 3-DB. Controller 14f
Indicates reception of data using signal DRDY #. The controller 14f instructs the buffer / data selection control circuit 14c to latch the burst write data in the burst data buffer 4c according to the signal WBDS #.

The buffer / data selection control circuit 14c is
In accordance with an instruction from the controller 14f, a signal indicating the timing of sequentially latching the backlight data D1 to D4 input every 64 bits in the burst data buffer 4c is output. Backlight data D1 to D4
Is a burst data buffer 4c having a structure of 64 × 4 bits.
Are sequentially latched. Buffer / data selection control circuit 1
4c, according to the instruction from the controller 14f, 64
12 bits x 4 burst write buffer 4c output
A selection signal is output to the data selection / merge circuit 14b so that the data is sequentially output every 8 bits. The data selection / merge circuit 14b sequentially selects the output of the 64-bit × 4-bit burst write buffer 4c for every 128 bits in accordance with the selection signal from the controller 14c and outputs it to the output line. The memory control signal generation circuit 4i follows the write control signal WE in accordance with the instruction from the controller 14f.
#, Row control signal RAS #, address MAB [10:
0] and column control signal CAS # are sequentially generated and output to the memory 5. The memory 5 writes the write back data. On the other hand, the buffer / data selection control circuit 14e
In accordance with an instruction from the controller 14f, outputs a selection signal instructing to sequentially select the output of the 64 bit × 4 burst write buffer 4c by 64 bits as soon as the write back data is latched in the write back buffer 4c. The data selection circuit 14d sequentially selects 64 bits from the burst data buffer 4c in accordance with the selection signal from the buffer / data selection control circuit 14e, and the data D1 of four consecutive transmissions through the input / output buffer 4a.
~ D4 is output to the data bus 3-DB.

In this case, the write data is written to the memory 5 and the read data is output to the data bus 3-DB in parallel. Therefore, since the read is not performed directly in the memory 5, it is not necessary to wait for the write-back data to be written in the memory, and the write-back data is output to the host bus 3, and the occupied time of the memory 5 in the two cycles of write and read is also large. Instead, it only takes the time to complete one write cycle. As described above, according to the first embodiment, the backlight data latched in the backlight buffer 4c is output to the host bus 3 during the single read or burst read backlight. Since the access to the memory 5 is required only once at the time of backlighting, the occupied time of the cache 2-i of the host bus 3 becomes short. Further, at the time of single write backlight, the backlight data latched in the backlight buffer 4c and the single write data latched in the single write buffer 14a are merged and written to the memory 5, so that the memory 5 Since the access is performed only once when the backlight is used, the occupied time of the cache 2-i of the host bus 3 is shortened.

Second Embodiment FIG. 9 is a functional block diagram of a memory control circuit according to the second embodiment of the present invention. The memory control circuit of the second embodiment is different from the memory control circuit of the first embodiment in that the memory 25 has a cache 22-i and an I / O unit 26-.
I / O unit 26-
When the light back light for the light from j,
Merge the data and write it in the memory 25,
At the time of the backlight for the read, the read data is not read from the memory 25, but the backlight data is output from the buffer to the I / O unit 26-j. As shown in FIG. 9, the memory control circuit according to the second embodiment of the present invention includes two memory control circuits 24.
-1 and 24-2. The two memory control circuits 24-1 and 24-2 are configured by common elements. In this way, two memory control circuits 24-
The reason for dividing into 1,4-2 is because of the problem of the number of pins. The memory control circuit 24-1 includes an input / output buffer 24a on the host bus side, an input / output buffer 24b on the memory side, and
Burst data buffer (first buffer) 24d of 2 bits × 4 configuration, 32-bit single write buffer (second buffer) 24g, data selection / merge circuit 2
4f, buffer / data selection control circuit 24g, 16-bit × 4 data buffer 24h, data selection circuit 2
4i, 24j, 24l (second data selection circuit), buffer / data selection control circuit 24k, 16-bit × 4 configuration buffer (third buffer) 24m, data selection / merge circuit 24n, buffer / data control circuit 24o Three
It is provided with a data buffer 24p of 2 bits × 2 structure, data selection circuits 24q, 24r, 24s (first data selection circuit), a buffer / data selection control circuit 24t, a memory control signal generation circuit 24u, and a controller 24v.

The memory control circuits 24-1 and 24-2 are connected to the cache 22-i (i = 1 to 1) via the host bus 23.
n), is connected to the I / O unit 26-j via the I / O bus 27, and is connected to the memory 25 via the data bus. The input / output buffer 24a is connected to the data bus 23-DB of the host bus 23.
The output of the input / output buffer 24a is connected to the burst data buffer 24d and the input of the single data buffer 24e. The output of the burst data buffer 24d is connected to the inputs of the data selection / merge circuit 24n and the data selection circuit 24l. The output of the single write buffer 24e is connected to the inputs of the data selection / merge circuit 24n and the data selection circuit 24i. The output of the buffer / data selection control circuit 24g is connected to the selection signal inputs of the burst data buffer 24d, the single write buffer 24e, and the data selection circuit 24f. The input / output buffer 24b is connected to the memory 25. The output of the input / output buffer 24b is connected to the inputs of the data buffer 24p and the data buffer 24h. The output of the data buffer 24h is the data selection circuit 2
It is connected to the input of 4j.

The outputs of the data selection circuits 24j and 24i are
It is connected to the input of the data selection circuit 24l. The output of the buffer / data selection control circuit 24k is the data buffer 24h and the data selection circuits 24i, 24j, and 24l.
Is connected to the selection signal input of. Data selection circuit 24
The output of l is connected to the input of the input / output buffer 24c. The input / output buffer 24c is connected to the address bus 27-AD of the I / O bus 27. The output of the input / output buffer 24c is connected to the input of the data buffer 24m. The output of the data buffer 24m is data selection /
It is connected to the inputs of the merge circuit 24n and the data selection circuit 24r. The output of the buffer / data selection control circuit 24o is connected to the selection signal inputs of the data buffer 24m and the data selection / merge circuit 24n. The output of the data buffer 24p is connected to the input of the data selection circuit 24p. The outputs of the data selection circuits 24p and 24r are connected to the inputs of the data selection circuit 24s. The output of the buffer / data selection control circuit 24t is the data buffer 24p and the data selection circuits 24p, 24q, 24.
It is connected to the selection signal inputs of r and 24s.

The processor 21-i has, for example, a burst transfer mechanism of four continuous transmission with a data width of 64 bits. The cache 22-i has, for example, a burst transfer mechanism and a bus control circuit that continuously transmit four bits with a data width of 64 bits. The host bus 23 has, for example, a 64-bit wide data bus 23-DB, an address bus 23-AD, and a control line 23-CTL. The memory 25 is, for example, a DRAM to which a 128-bit width data signal, an 11-bit width address signal, a row control signal signal, a column control signal, a write control signal, and a read control signal are input. The input / output buffer 24a is a buffer for inputting / outputting 32-bit wide data to / from the host bus 23. The input / output buffer 24b is 64
It is a buffer that inputs and outputs bit width data. The input / output buffer 24c is the I / O unit 26-j (j = 1.
It is a 16-bit wide buffer for inputting / outputting data between m) to m). The burst data buffer 24d is a buffer of 32 bits × 4 structure. The single data buffer 24e is a 32-bit buffer. The data selection circuit 24f is a circuit that selects 64 bits from the output of the burst data buffer 24d of 32 bits × 4 configuration. The buffer / data selection control circuit 24g includes a burst data buffer 24d and a single write buffer 24e.
Is a circuit for generating a signal indicating the timing of latching the data and a selection signal for selecting the output of the burst data buffer 24d by the data selection circuit 24f.

The data buffer 24h has 16 bits × 4.
It is a configuration buffer. The data selection circuit 24i has 32
It is a circuit that selects a 16-bit output from the output of the single write buffer 24e having a bit configuration. The data selection circuit 24l is a circuit that selects one of the outputs of the data selection circuits 24i and 24j. Data buffer 24m
Is a buffer for inputting the output of the I / O unit 26-j of 16 bits × 4 configuration. The data selection / merge circuit 24n is a circuit that selects / merges the output of the single write buffer 24e, the output of the data selection circuit 24f, and the output of the data buffer 24m. The buffer / data selection control circuit 24o receives a signal indicating the timing of latching data in the data buffer 24m, and
This is a circuit for generating a selection signal to the merge circuit 24n.
The data buffer 24p is a buffer of 32 bits × 2. The data selection circuit 24q is a circuit that selects a 32-bit output from the data buffer 24p having a 32-bit × 2 configuration. The data selection circuit 24r is a circuit that selects a 32-bit output from the output of the data buffer 24m having a 16-bit × 4 configuration.

The data selection circuit 24s is a circuit for selecting one of the 32-bit outputs of the data selection circuits 24r and 24p. Buffer / data selection control circuit 24t
Is a circuit for generating a signal indicating a timing at which the buffer 24p latches data and a selection signal for the data selection circuits 24q, 24r, and 24s. The memory control signal generation circuit 24u is a circuit that generates a control signal for reading / writing the memory 25. Controller 24v
Is a control circuit for synchronizing the entire memory control circuit 24-1. I / O unit 26-j (j = 1 to
m) is a SCSI controller or LAN controller. The I / O bus 27 has a 32 × 2 bit data bus 27-DB, an address bus 27-AD, and a control line 27-CTL. The operation of FIG. 9 will be described below.

(A) Single write from the host bus side It is assumed that the processor 21-i attempts to write single data to the memory 25 and a miss is made in the cashier 22-i. The cache 22-i drives the address to the address bus 3-AD in an attempt to perform a single write. The controller 24v asserts a signal indicating that the address has been confirmed. For the address, the cache 22-j (j ≠ i) other than the processor 21-i that started the cycle and the processor 21-j perform snoop, and the cache 22-i that started the cycle waits for the result of the snoop. Data to the host bus 23 without
To the data bus 23-DB. The buffer / data selection control circuit 24g outputs a signal instructing the latch timing to the single data buffer 24e in accordance with the instruction from the controller 24v. Single data is
It is latched in the single data buffer 24e. Assuming that the line including the single write data does not hit in any of the other caches 22-j (j ≠ i), the signal indicating whether or not the modify line is hit is negated. Buffer / data selection control circuit 2
4o is 6 from the selection signal for selecting the output of the single write buffer 24e and the address [4: 3} bit of the single write data according to the instruction of the controller 24v.
A selection signal for instructing which of 0 to 31 bits or 32 to 63 bits of the 4-bit output line the single data is output is output. The data selection circuit 24n selects the output of the single write buffer 24e according to the selection signal from the buffer / data selection control circuit 24o, and outputs 32 bits according to the selection signal. The single data is output to the data line of the memory 25 through the input / output buffer 24b. Memory control signal generation circuit 24
u stores in the memory 25 according to the instruction from the controller 24v.
A control signal for writing to is generated and output to the memory 25. The memory 25 writes single data.

(B) Burst write from the host bus side It is assumed that the processor 21-i tries to write the burst data to the memory 25, but misses the cashier 22-i. The cache 22-i drives the address to the address bus 3-AD in an attempt to perform a single write. The controller 24v asserts a signal indicating that the address has been confirmed. Cache 22-i is 4
The continuous transmission data is output to the data bus 23-DB. The buffer / data selection control circuit 24g includes a controller 24
In accordance with the instruction v, the burst data buffer 24d outputs a signal instructing the timing of latching. The burst data is sequentially latched in the burst data buffer 24e having a 32 × 4 bit structure. The buffer / data selection control circuit 24g outputs a selection signal to sequentially select the output of the burst data buffer 24e every 64 bits in accordance with an instruction from the controller 24v. The data selection circuit 24f selects and outputs the output of the burst data buffer 24e every 64 bits in accordance with the selection signal from the buffer / data selection control circuit 24g. buffer·
The data selection control circuit 24o outputs a selection signal to select the 64-bit output of the data selection circuit 24f.
The data selection circuit 24f is responsive to the selection signal from the buffer / data selection control circuit 24o.
Select the output of f, and through the input / output buffer 24b,
Output to the data line of the memory 5. The memory control signal generation circuit 24u generates a memory control signal according to an instruction from the controller 24v. The memory 25 sequentially writes burst data.

(C) Single read from the host bus side It is assumed that the processor 21-i attempts to read single data from the memory 25, but misses in the cache 22-i. The cache 22-i tries to read the single data and sends the address to the address bus 23-A.
Drive to D. The controller 24v asserts a signal indicating that the address has been confirmed. For that address, the cache 22-j (j ≠ i) other than the processor 21-i that started the cycle, the processor 21-
j and the I / O unit 26-k perform snoop.
If no other cache 22-j (j ≠ i) containing a single read data line is hit, the signal indicating whether or not the modify line is hit is negated.

(C1) When I / O unit 26-k holds read data When I / O unit 26-k holds read data, I / O unit 26-k reads data. Is held by a signal, and the signal indicates that data is ready. The controller 24v uses a signal to indicate that it accepts data. buffer·
The data selection control circuit 24o outputs a signal for latching data to the data buffer 24m according to an instruction from the controller 24v. I / O data bus 27-
The data output to DB is latched in the data buffer 24m. The buffer / data selection control circuit 24o
According to the instruction from the controller 24u, a selection signal is output so as to select the output of the data buffer 24m.
The data selection circuit 24n selects and outputs the output of the data buffer 24m. Memory control signal generation circuit 24u
Generates a memory control signal according to an instruction from the controller 24v. The memory 25 is the I / O data bus 2
Data from 7-DB is sequentially written. On the other hand, the buffer / data selection control circuit 24t is the controller 24v.
A selection signal is output to select the output from the data buffer 24m according to the instruction from. Data selection circuit 2
4r selects the output of the data buffer 24m and outputs it to the data bus 23-DB through the data selection circuit 24s and the input / output buffer 24a.

(C2) When the I / O unit 26-k does not hold read data The memory control signal generation circuit 24u is the controller 24v.
Memory control signal to generate the memory 2
5 is output. The memory 25 reads the data. The buffer / data selection circuit 24t is the controller 24v.
In accordance with the instruction, a signal indicating the timing of latching the data is output to the data buffer 24p. The data from the memory 25 is latched in the data buffer 24p.
The data latched in the data buffer 24p is selected by the data selection circuits 24q and 24s according to the selection signal from the buffer / data selection control circuit 24t, and is output to the data bus 23-DB through the input / output buffer 24a.

(D) Burst read from the host bus side It is assumed that the processor 21-i attempts to read single data from the memory 25, but misses in the cache 22-i. The cache 22-i tries to read the single data and sends the address to the address bus 23-A.
Drive to D. The controller 24v asserts a signal indicating that the address has been confirmed. For that address, the cache 22-j (j ≠ i) other than the processor 21-i that started the cycle, the processor 21-
j and the I / O unit 26-k perform snoop.
If no other cache 22-j (j ≠ i) containing a single read data line is hit, the signal indicating whether or not the modify line is hit is negated. Then, if the I / O unit 26-k holds a part of the data to be burst read, the data is written to the memory 25, and then the burst data is output from the memory 25 in four consecutive transmissions to the data buffer. 24
It is latched by p and output to the data bus 23-DB through the data selection circuits 24q and 24s and the input / output buffer 24a.

(E) Write-back for single write from the host side It is assumed that the processor 21-i attempts to write single data to the memory 25 and a mishit is made by the cashier 22-i. The cache 22-i drives the address to the address bus 3-AD in an attempt to perform a single write. The controller 24v asserts a signal indicating that the address has been confirmed. For the address, the cache 22-j (j ≠ i) other than the processor 21-i that started the cycle and the processor 21-j perform snoop, and the cache 22-i that started the cycle waits for the result of the snoop. Data to the host bus 23 without
To the data bus 23-DB. Controller 24
v asserts a signal indicating that it has confirmed the address. For the address, the cache 22-j (j ≠ i) and the processor 21-j other than the processor 21-i which started the cycle perform snoop, and the cache 22-i which started the cycle outputs the result of the snoop. Data can be transferred to the data bus 23-DB of the host bus 3 without waiting.
Output to

The buffer / data selection control circuit 24g is
In accordance with the instruction from the controller 24v, the single data buffer 24e outputs a signal instructing the latch timing. The single data is latched in the single data buffer 24e. The cache 22-n asserts that a modify line has been hit with a signal and uses a signal to indicate that write-back data is ready. The controller 24u uses a signal to indicate that it accepts data. Buffer / data selection control circuit 24
In response to an instruction from the controller 24v, g outputs a signal indicating the timing of latching in the burst data buffer 24d. Burst write data is sequentially latched in the burst data buffer 24d. In accordance with an instruction from the controller 24u, the buffer / data selection control circuit 24g outputs a selection signal instructing to select the 32-bit × 4 burst data buffer 24d for every 64 bits. The data selection circuit 24f selects and outputs every 64 bits from the burst data buffer 24d.
The buffer / data selection control circuit 24o outputs a selection signal from the address [4: 3] of the single write data to the data selection / merge circuit 24n according to an instruction from the controller 24u. Data selection / merge circuit 24n
Selects / merges the output of the data selection circuit 24f and the output of the single write buffer 24e according to a selection signal from the buffer / data selection control circuit 24o, and outputs the selected / merged data. The output from the data selection / merge circuit 24n is latched by the input / output buffer 24b and output to the data line of the memory 25 every 64 bits. The memory control signal generation circuit 24u generates an address control signal according to an instruction from the controller 24v and outputs it to the memory 25. The memory 25 writes data.

(F) Write-back for single read from the host side It is assumed that the cache 22-i makes a miss hit while trying to read single data into the memory 25. The cache 22-i drives an address to the address bus 3-AD in an attempt to perform a single read. The controller 24v asserts a signal indicating that the address has been confirmed. For the address, the cache 22-j (j ≠ i) other than the processor 21-i that started the cycle and the processor 21-j perform snoop, and the cache 22-i that started the cycle waits for the result of the snoop. Data to the host bus 23 without
To the data bus 23-DB. Controller 24
v asserts a signal indicating that it has confirmed the address. For the address, the cache 22-j (j ≠ i) and the processor 21-j other than the processor 21-i which started the cycle perform snoop. The cache 22-n asserts that a modify line has been hit with a signal and uses a signal to indicate that write-back data is ready. The controller 24u uses a signal to indicate that it accepts data. The buffer / data selection control circuit 24g outputs a signal indicating the timing of latching in the burst data buffer 24d according to an instruction from the controller 24v. Burst write data is sequentially latched in the burst write buffer 24d.

The buffer / data selection control circuit 24g is
32 bits x 4 according to the instruction from the controller 24u
A selection signal for instructing to select the burst write buffer 24d having the configuration every 64 bits is output. The data selection circuit 24f includes burst data buffers 24d through 64d.
Select each bit and output. The buffer / data selection control circuit 24o outputs a selection signal to select the output of the data selection circuit 24f according to an instruction from the controller 24u. The data selection / merge circuit 24n selects and outputs the output of the data selection circuit 24f for every 64 bits. The output from the data selection / merge circuit 24n is latched by the input / output buffer 24b and output to the data line of the memory 25 every 64 bits. The memory control signal generation circuit 24u generates an address control signal according to an instruction from the controller 24v and outputs it to the memory 25. The memory 25 writes the backlight data. On the other hand, the buffer / data selection control circuit 24t
In accordance with an instruction from the controller 24v, the data selection circuit 24 starts from [4: 3] of the single read address in parallel with writing the write-back data to the memory 25.
A signal indicating the timing for selecting the output of f is output. The data selection circuit 24s selects the output of the data selection circuit 24f and outputs it to the data bus 23-DB through the input / output buffer 24a.

(G) Writeback for burst read from the host side It is assumed that the cache 22-i misses the cache data while trying to read the burst data into the memory 25. The cache 22-i drives the address to the address bus 3-AD in an attempt to burst read. The controller 24v asserts a signal indicating that the address has been confirmed. For the address, the cache 22-j (j ≠ i) other than the processor 21-i that started the cycle and the processor 21-j perform snoop, and the cache 22-i that started the cycle waits for the result of the snoop. Data to the host bus 23 without
To the data bus 23-DB. Controller 24
v asserts a signal indicating that it has confirmed the address. For the address, the cache 22-j (j ≠ i) and the processor 21-j other than the processor 21-i which started the cycle perform snoop. The cache 22-n asserts that a modify line has been hit with a signal and uses a signal to indicate that write-back data is ready. The controller 24u uses a signal to indicate that it accepts data.

The buffer / data selection control circuit 24g is
In accordance with an instruction from the controller 24v, a signal indicating the timing of latching is output to the burst data buffer 24d. Burst write data is sequentially latched in the burst write buffer 24d. The buffer / data selection control circuit 24g follows the instruction from the controller 24u, and the burst write buffer 24 of 32 bits × 4 configuration.
A selection signal for instructing to select d every 64 bits is output. The data selection circuit 24f selects and outputs every 64 bits from the burst data buffer 24d. The buffer / data selection control circuit 24o includes the controller 24
According to the instruction from u, a selection signal is output so as to select the output of the data selection circuit 24f. The data selection / merge circuit 24n selects and outputs the output of the data selection circuit 24f for every 64 bits. Data selection / merge circuit 24n
The output from is latched by the input / output buffer 24b,
It is output to the data line of the memory 25 every 64 bits. The memory control signal generation circuit 24u includes the controller 2
An address control signal is generated according to the instruction from 4v and output to the memory 25. The memory 25 writes the backlight data. On the other hand, the buffer / data selection control circuit 24t outputs a signal instructing to sequentially select the output of the data selection circuit 24f in parallel with the writing of the write-back data to the memory 25 in accordance with the instruction from the controller 24v. Data selection circuit 24s
Selects the output of the data selection circuit 24f and outputs the burst read data to the data bus 23-DB through the input / output buffer 24a.

(H) Write from I / O Bus Side When writing data to the memory 25, the I / O unit 26-j drives an address to the address bus 27-AD of the I / O bus 27. The controller 24v is
Assert a signal indicating that the address has been confirmed. Processor 2 that started the cycle for that address
The cache 22-j (j ≠ i) other than 1-i and the processor 21-j perform snooping, and the cache 22-i which started the cycle transfers data to the data bus 27-DB without waiting for the result of snooping. Output to. The cache 22-j (j ≠ i) determines whether or not the write data hits the modify line. And
It is assumed that the modify line is not hit in any cache 22-j. The controller 24v uses a signal to indicate that it accepts data. buffer·
According to an instruction from the controller 24v, the data selection control circuit 24o outputs a signal indicating an output destination from the data address to the 16-bit × 4-structured buffer 24m.
The data from the I / O data bus 27-DB is latched in the data buffer 24m. The data latched in the data buffer 24m is written in the memory 25 through the input / output buffer 24b.

(I) Read from I / O Bus Side When reading data to the memory 25, the I / O unit 26-j drives an address to the address bus 27-AD of the I / O bus 27. The controller 24v is
Assert a signal indicating that the address has been confirmed. Processor 2 that started the cycle for that address
The cache 22-j (j ≠ i) other than 1-i and the processor 21-j perform snooping, and the cache 22-i which started the cycle transfers data to the data bus 27-DB without waiting for the result of snooping. Output to. The cache 22-j (j ≠ i) determines whether or not the write data hits the modify line. And
It is assumed that the modify line is not hit in any cache 22-j. The controller 24v determines from the address of the data to be read whether the burst data buffer 24d or the single write buffer 24e has latched that data. .Data selection control circuits 24g, 24k
To select data from the burst data buffer 24d, and to select the data selection circuit 24f and the data selection circuit 2
4 l, through the input / output buffer 24 c, the data bus 27
-Output to DB.

If the data is latched in the single write buffer 24e, the data latched in the single write buffer 24e is transferred from the data address to the data bus via the data selection circuit 24i, the data selection circuit 24l, and the input / output buffer 24c. 27-Output to DB.
If the read data is not latched in the burst data buffer 24d and the single write buffer 24e,
The memory control signal generation circuit 24u is the controller 24v.
A memory control signal is generated and output to the memory 25 in accordance with the instruction from. The memory 25 reads the data.
The buffer / data selection control circuit 24k outputs a signal indicating the timing for latching the data read from the memory 25 in accordance with an instruction from the controller 24v.
The data read from the memory 25 is stored in the data buffer 2
It is latched in a predetermined buffer for 4h. The buffer / data selection control circuit 24k includes data selection circuits 24j and 24j.
The selection signal is output to l. The data selection circuit 24j selects from the output of the data buffer 24h having a 16 × 4 bit structure according to the selection signal from the buffer / data selection control circuit 24k, and the data selection circuit 24l selects the output of the data selection circuit 24j. And outputs it to the data bus 27-DB through the input / output buffer 24c.

(J) Write Back for Writing from I / O Bus Side When writing data to the memory 25, the I / O unit 26-j sends an address to the address bus 27-AD of the I / O bus 27. drive. The controller 24u is
A signal indicating that the address is confirmed is asserted, and a signal indicating that the data is accepted is asserted. The processor 21 that started the cycle for that address
The cache 22-j (j ≠ i) other than -i and the processor 21-j perform snoop. I / O unit 26
-J outputs data to the data bus 27-DB without waiting for the result of snoop. The buffer / data selection control circuit 24o outputs a signal indicating the timing of latching in the data buffer 24m in accordance with an instruction from the controller 24v. The data from the data bus 27-DB is latched in the data buffer 24m. The cache 22-j (j ≠ i) determines whether or not the write data hits the modify line. Then, it is assumed that the cache 22-n hits the modify line. The cache 22-n asserts that a modify line has been hit with a signal and uses a signal to indicate that write-back data is ready. Controller 2
4v uses a signal to indicate that data is accepted.

The buffer / data selection control circuit 24g is
According to the instruction from the controller 24v, the data bus 2
The write data buffer 24d output to 3-DB generates and outputs a signal indicating the timing of latching data. Burst write data is sequentially latched in the burst data buffer 24d. The buffer / data selection control circuit 24g generates and outputs a selection signal for selecting the output of the burst data buffer 24d for every 64 bits. The data selection circuit 24f selects and outputs the output from the burst data buffer 24d for every 64 bits in accordance with the selection signal from the buffer / data selection control circuit 24g. According to an instruction from the controller 24v, the buffer / data selection control circuit 24o selects a selection signal indicating which of the outputs of the data buffer 24m is to be selected from the address of the write data and which of the outputs of the data selection circuit 24f at which timing. A selection signal indicating whether to select is generated and output. The data selection / merge circuit 24n outputs the data from the data selection circuit 24f and the data buffer 2 according to the selection signal from the buffer / data selection control circuit 24o.
4m output is selected / merged and output. The output of the data selection / merge circuit 24n is output to the memory 25 through the input / output buffer 24b. The memory control signal generation circuit 24u generates a memory control signal according to an instruction from the controller 24v and outputs the memory control signal to the memory 25. The memory 25 writes the output of the input / output buffer 24b.

(K) Write-back for reading from the I / O bus side When reading data to the memory 25, the I / O unit 26-j drives an address to the address bus 27-AD. The controller 24u asserts a signal indicating that the address is confirmed, and asserts a signal indicating that the data is accepted. For that address, the cache 22-j (j ≠ i) and the processor 21-j other than the processor 21-i that started the cycle
Do snoop. The I / O unit 26-j transfers the data to the data bus 27- without waiting for the result of the snoop.
Output to DB. The cache 22-j (j ≠ i) determines whether or not the write data hits the modify line. Then, it is assumed that the cache 22-n hits the modify line. In accordance with an instruction from the controller 24v, the buffer / data selection control circuit 24g generates and outputs a signal indicating the timing of latching data in the write data buffer 24d output to the data bus 23-DB. Burst data buffer 24
Burst write data is sequentially latched in d.

The buffer / data selection control circuit 24g is
A selection signal is generated and output so that the output of the burst data buffer 24d is selected every 64 bits. The data selection circuit 24f receives the burst data buffer 24d according to the selection signal from the buffer / data selection control circuit 24g.
The output from is selected every 64 bits and output. The buffer / data selection control circuit 24o is a controller 24v.
In accordance with the instruction from, a selection signal indicating which of the outputs of the data selection circuit 24f is to be selected at which timing is generated and output. The data selection / merge circuit 24n selects and outputs the output of the data selection circuit 24f according to the selection signal from the buffer / data selection control circuit 24o. The output of the data selection / merge circuit 24n is output to the memory 25 through the input / output buffer 24b. The memory control signal generation circuit 24u generates a memory control signal according to an instruction from the controller 24v and outputs the memory control signal to the memory 25. The memory 25 writes the output of the input / output buffer 24b. On the other hand, the buffer / data selection control circuit 2
4k is the memory 2 according to the instruction of the controller 24v.
In parallel with writing the write-back data to 5, the 0th to 15th bits, 16 to 3 of the output of the 64-bit data data selection circuit 24f are read from the address of the read data.
A selection signal indicating whether it is the 1st bit, the 32nd to 47th bits, or the 48th to 63rd bits, and which of the 64th bit outputs is the first time or the second time is generated and output.

The data selection circuit 24l selects and outputs the output of the data selection circuit 24f in accordance with the selection signal from the buffer / data selection control circuit 24k. The output of the data selection circuit 24l passes through the input / output buffer 24c,
Output to the data bus 27-DB. As described above, according to the second embodiment, when the write back to the write from the host bus 23 side to the memory 25 occurs, the write cycle is the write back as in the case of the first embodiment. There is no need to wait until the data is written to the memory 25, and writing to the memory 25 is 1
This can be done only once, and writing from the I / O bus 27 to the memory 25 can be performed in the same manner. When a write-back for a read from the host bus 23 side to the memory 25 occurs, the write-back data is written in the memory 25 because the read is not directly performed in the memory 25 as in the case of the first embodiment. The read data is output to the host bus 23 side in a fixed time after the write-back data is output to the host bus. The occupation time of the memory 25 is not the two cycles of writing and reading but one cycle of writing, and I
Reading from the / O bus 27 side to the memory 27 can be performed similarly.

The present invention is not limited to the above embodiment, and various modifications can be made. For example, there are the following modifications. An example has been described in which the invention is applied to a multiprocessor system including a cache having a 4-bit burst transfer control mechanism and a bus control circuit with a 64-bit data width and a memory control circuit having a 4-bit transmission mechanism with a 64-bit data width. , There is no limit to the data width and the number of continuous transfer of the burst transfer mechanism, and any burst transfer mechanism can be provided by changing the width and size of the buffer according to the respective data width and the number of continuous transfer of the burst transfer mechanism. It can also be applied to a system using a backlight type cache and a memory control circuit.

[0057]

As described in detail above, the first and the second
According to the invention, in the case of backlight for single read and single write, the data to be single read is directly output from the buffer to the data bus, and the data to be single written is merged and written to the memory. Only one write to memory is required, resulting in faster access.

[Brief description of drawings]

FIG. 1 is a functional block diagram of a memory control circuit according to a first embodiment of the present invention.

FIG. 2 is a functional block diagram of a conventional memory control circuit.

FIG. 3 is a time chart showing write back for the single write in FIG.

FIG. 4 is a time chart showing write back for single read in FIG.

5 is a time chart showing write back for burst read in FIG. 2. FIG.

FIG. 6 is a time chart showing write back for the single write in FIG.

FIG. 7 is a time chart showing write back for single read in FIG.

8 is a time chart showing write back for burst read in FIG. 1. FIG.

FIG. 9 is a functional block diagram of a memory control circuit according to a second embodiment of the present invention.

[Explanation of symbols]

1-1 to 1-n, 21-1 to 21-n processor 2-2 to 2-n, 22-1 to 22-n cache 3,23 host bus 4, 24-1, 24-2 memory control circuit 4a , 4b, 24a, 24b, 24c Input / output buffer 4c, 24d Burst data buffer 14a, 24g Single write buffer 14b, 24n Data selection / merge circuit 14c, 14e, 24g, 24k Buffer
Data selection control circuit 24o, 24n buffer
Data selection control circuit 14d, 24f, 24i, 24j, 24l Data selection circuit 24n, 24p, 24r, 24s Data selection circuit 5,25 Memory 4i, 24u Memory control signal generation circuit 14j, 24v Controller 26-1 to 26-m I / O unit

Claims (2)

[Claims] 1. A memory control circuit for controlling reading / writing of data from / to a memory of a plurality of write-back type caches, wherein when the cache attempts to write or read data, the data is stored in other caches. When the modification line is hit, the first buffer which receives and holds the write-back data on the modification line hit by the other cache from the other cache, and the data which the cache single-writes is received from the cache A second buffer to hold and when writing back data on the modify line for a single write of the cache, each writeback data held in the first buffer is held in the second buffer. Done If the data to be single-written and the address in the memory are the same, select the data to be single-written instead of the data in the write-back data, and select the write-back data other than the write-back data having the same address as the data. And outputs the selected data according to the address in the memory, and when writing back the data on the modify line for the single read of the cache, the write-back data held in the first buffer is A data selection / merge circuit for selecting and outputting according to the address of the data in the memory, and in the case of write back for the single read, holds in the first buffer according to the address of the memory for the data to be single read. And a memory control signal generation circuit for generating a memory control signal for reading / writing to / from the memory. Characteristic memory control circuit. 2. A memory control circuit for controlling read / write of data to a plurality of write-back type caches and memories of I / O units, wherein when the cache attempts a single write or a single read of data, or When the I / O unit tries to write or read data and the data hits the modify line of another cache, the write-back data on the modify line hit by the other cache is received from the other cache. A first buffer for holding, a second buffer for receiving data to be single-written by the cache from the cache, and a second buffer for holding, data for writing by the I / O unit from the I / O unit A third buffer to hold When writing back data on the modify line for a single write of the cache, for each of the write-back data held in the first buffer, the data to be single-written held in the second buffer and For the same address in the memory, select the data to be single-written instead of the data in the write-back data, select the write-back data other than the write-back data having the same address as the data, and select the selected data. When writing back data on the modify line for a single read of the cache, the writeback data held in the first buffer is selected according to the address in the memory. Out When writing back the data on the modify line for the write of the I / O unit, the writeback data held in the first buffer is held in the third buffer. If the data to be written has the same address in the memory, the data to be written is selected instead of the data in the writeback data, and the writeback data other than the writeback data having the same address as the data is selected, And a data select / merge circuit for outputting the data of the data according to the address in the memory, and during write back to the single read of the cache, the data is held in the first buffer according to the address of the data to be single read in the memory. Data from the single read A first data selection circuit for selecting and outputting as a data, and at the time of write back to the read of the I / O unit, the data is held in the first buffer according to the address of the data to be read in the memory. Second to select and output data as data to be read
And a memory control signal generation circuit for generating a memory control signal for reading / writing from / to the memory.