JPH09231129A - Memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce momentary consumption of large electric power and momentary generation of noise by making plural memory banks, constituting one memory space, different in the timing of refreshing. SOLUTION: Plural memory controllers 16-19 are connected to the memory banks 12-15 individually. The memory controllers 16-19 refresh the connected memory banks 12-15 and perform the refreshing process in different timing from others, so the memory banks 12-15 are not refreshed at the same time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device having a plurality of memory banks.

[0002]

2. Description of the Related Art Conventionally, the storage capacity required for a computer tends to increase, and there is a memory device that uses a plurality of memory banks in parallel to realize this. A conventional example of such a memory device will be described below with reference to FIGS.

The memory device 1 illustrated here has first and second memory banks 2 and 3, as shown in FIG. These memory banks 2 and 3 are a single RAS / CAS (Raster Address) corresponding to a memory controller.
The RAS / CAS control unit 4 is connected to an address decoding unit 5 and a refresh request unit 6.

The memory device 1 as described above is used, for example, as a storage device of a high-performance computer, and executes data read / write in response to an instruction of an external higher CPU (Central Processing Unit). . The plurality of memory banks 2 and 3 are DRAMs (Dynamic Random Acce
Since it consists of ss Memory), it has good productivity but requires refreshing. Data read / write is upper C
Although it is executed corresponding to the PU, the refresh control is executed by the internal processing of the memory device 1.

For example, the address decoding unit 5 decodes a read / write control signal and an address signal input from an external CPU, and the first and second memory banks 2, 2.
RAS by generating access request signals individually corresponding to 3
/ CAS is output to the control unit 4. When the access request signal is input, the RAS / CAS control unit 4 generates a RAS signal and a CAS signal as address signals and outputs them to the first and second memory banks 2 and 3, so that these memories In banks 2 and 3, data read / write is executed at an address designated by the RAS / CAS signal.

Further, the refresh request unit 6 has a built-in refresh timer which repeats the countdown from the set value "N" to "0", and the refresh request signal is sent every time the count is "0". Output to. RAS to which this refresh request signal is input
The / CAS control unit 4 causes the corresponding memory banks 2 and 3 to execute refresh. Then, when the access request or the refresh request as described above conflicts, the process started early is continuously executed and the other process is on standby.

[0007]

Since the memory device 1 as described above uses a plurality of memory banks 2 and 3 in parallel, it is possible to handle a large amount of data at a time.

However, since refresh is simultaneously executed in a plurality of memory banks 2 and 3, an excessive amount of power is instantaneously consumed. For this reason, a large-capacity drive power source is required, and noise is also a problem.

Further, since neither of the memory banks 2 and 3 can be accessed during the refresh operation, the plurality of memory banks 2 and 3 cannot be used with high efficiency. Further, since one memory space is formed by the plurality of memory banks 2 and 3, if one of the plurality of memory banks 2 and 3 is defective, the entire memory bank cannot be used.

[0010]

According to the first aspect of the present invention,
Multiple memory controllers are individually connected to multiple memory banks, and each of these multiple memory controllers
Refresh the connected memory banks,
The refreshing of the plurality of memory banks is executed at different timings. Therefore, each of the plurality of memory controllers individually refreshes the plurality of memory banks. However, since the plurality of memory banks are refreshed at different timings, the plurality of memory banks are simultaneously refreshed. Not done.

According to a second aspect of the present invention, a plurality of memory controllers are individually connected to a plurality of memory banks, and each of the plurality of memory controllers corresponds to setting data in which an address signal input from the outside can be changed. Then, the memory bank connected corresponding to the changed address signal is accessed. Therefore, when the memory controller changes the address signal input from the outside according to the variable setting data, the memory bank accesses the memory bank according to the changed address signal. The memory bank to be used is changed by the setting data.

According to a third aspect of the present invention, a plurality of memory controllers are individually connected to a plurality of memory banks, and each of the plurality of memory controllers is set so that the use prohibition of the connected memory bank can be switched. To be done. Therefore, the use prohibition of a predetermined memory bank is set in the memory controller connected thereto, so that the use of only the defective memory bank can be prohibited.

According to a fourth aspect of the present invention, a plurality of memory controllers are individually connected to a plurality of memory banks, and each of the plurality of memory controllers is set so that refresh inhibition of the connected memory banks can be switched. To be done. Therefore, the refresh inhibition of a predetermined memory bank is set in the memory controller connected to it, so that the refresh inhibition can be inhibited only for the unused memory bank.

According to a fifth aspect of the invention, in the second aspect of the invention, a plurality of memory controllers are individually connected to a plurality of memory banks, and each of the plurality of memory controllers is connected to the memory bank. Are refreshed and the plurality of memory banks are refreshed at different timings. Therefore, the refreshing of the plurality of memory banks is performed at different timings, so that the refreshing of the plurality of memory banks is not performed simultaneously. Moreover, since the memory controller accesses the memory bank in response to the address signal changed corresponding to the variable setting data, the memory bank accessed in response to the address signal is changed by the setting data. Therefore, if the refresh order and the access order are adjusted for a plurality of memory banks, the refresh and the access are executed at the same time.

According to a sixth aspect of the invention, in the third or fourth aspect of the invention, a plurality of memory controllers are individually connected to a plurality of memory banks, and each of the plurality of memory controllers is connected. The memory bank is refreshed and the plurality of memory banks are refreshed at different timings. Therefore, the refreshing of the plurality of memory banks is performed at different timings, so that the refreshing of the plurality of memory banks is not performed simultaneously. Moreover, since the use prohibition of a predetermined memory bank is set in the memory controller connected thereto, it is possible to prohibit use of only the defective memory bank. Alternatively, refresh inhibition of a predetermined memory bank is set in the memory controller connected to it, so that it is possible to inhibit refresh of only a memory bank that is not used. For this reason, when refresh is performed on a plurality of memory banks, the timing is different among the plurality of memory banks, and unnecessary refresh of unused memory banks is not performed.

According to a seventh aspect of the invention, in the third aspect of the invention, a plurality of memory controllers are individually connected to the plurality of memory banks, and each of the plurality of memory controllers receives an address signal input from the outside. Is changed corresponding to variable setting data, and the connected memory bank is accessed corresponding to the changed address signal. Therefore, the use prohibition of a predetermined memory bank is set in the memory controller connected thereto, so that the use of only the defective memory bank can be prohibited. Further, since the memory controller accesses the memory bank in response to the address signal changed corresponding to the variable setting data, the memory bank accessed in response to the address signal is changed by the setting data. Therefore, even if the use of a specific memory bank is prohibited, a continuous memory space is secured by changing the address signal.

According to an eighth aspect of the invention, in the third or fourth aspect of the invention, a plurality of memory controllers are individually connected to a plurality of memory banks, and each of the plurality of memory controllers is connected. The memory bank is refreshed, the refreshing of the plurality of memory banks is executed at different timings, the address signal input from the outside is changed in correspondence with the variable setting data, and the changed address signal is dealt with. And access the connected memory banks. Therefore, the refreshing of the plurality of memory banks is performed at different timings, so that the refreshing of the plurality of memory banks is not performed simultaneously. Moreover, since the memory controller accesses the memory bank in response to the address signal changed corresponding to the variable setting data, the memory bank accessed in response to the address signal is changed by the setting data. Therefore, if the refresh order and the access order are adjusted for a plurality of memory banks, the refresh and the access are executed at the same time. Moreover, since the use prohibition of a predetermined memory bank is set in the memory controller connected thereto, it is possible to prohibit use of only the defective memory bank. Alternatively, refresh inhibition of a predetermined memory bank is set in the memory controller connected to it, so that it is possible to inhibit refresh of only a memory bank that is not used. For this reason, when refresh is performed on a plurality of memory banks, the timing is different among the plurality of memory banks, and unnecessary refresh of unused memory banks is not performed.

According to a ninth aspect of the present invention, in the third aspect of the present invention, a memory check means is provided for individually inspecting a plurality of memory banks for defects and for setting the use prohibition of the corresponding memory controller in a freely switchable manner. . Therefore, the memory bank is checked for defects in the memory bank,
Since the use of the defective memory bank is prohibited in the memory controller, the use of the defective memory bank is automatically prohibited.

According to a tenth aspect of the present invention, in the seventh aspect of the present invention, memory check means for individually inspecting a plurality of memory banks for defects and setting the use prohibition to the corresponding memory controller so as to be switchable is provided. The memory controller changes the address signal so as to secure a continuous memory space in a state where the prohibited memory bank is excluded. Therefore, the defective memory bank is inspected by the memory check means, and the use prohibition of the defective memory bank is set in the memory controller, so that the use of the defective memory bank is automatically prohibited. Further, since the memory controller accesses the memory bank in response to the address signal changed corresponding to the variable setting data, the memory bank accessed in response to the address signal is changed by the setting data. Therefore, use of a defective memory bank is automatically prohibited, and even in such a state, a continuous memory space is secured by changing the address signal.

According to an eleventh aspect of the present invention, in the seventh aspect of the present invention, a memory check unit is provided for individually inspecting a plurality of memory banks for defects and setting a corresponding memory controller so that use prohibition can be switched. A spare memory bank that is unused in the initial state is provided, and the memory controller changes the address signal so that the reserved memory bank is complemented by the spare memory bank.
Therefore, the defective memory bank is inspected by the memory check means, and the use prohibition of the defective memory bank is set in the memory controller, so that the use of the defective memory bank is automatically prohibited. Since the memory controller changes the address signal so that this reserved memory bank is complemented by a spare memory bank, the use of the defective memory bank is automatically prohibited, and the same memory space is secured even in such a state. To be done.

[0021]

FIG. 1 shows a first embodiment of the present invention.
1 to 3 will be described below. With respect to the memory device 11 of the present embodiment, the same parts as those of the memory device 1 described above as a conventional example are denoted by the same names and reference numerals, and detailed description thereof will be omitted.

First, the memory device 11 of the present embodiment is
As shown in FIG. 1, the first to fourth memory banks 12 to
15 of the first to fourth memory banks 12 to 15 and the first to fourth memory controllers 16 to
19 are individually connected. These memory controllers 16 to 19 are connected to an address decoding unit provided outside, and the address decoding unit is connected to a higher CPU (not shown). Here, only the first memory controller 16 has a refresh timer 2
0 is connected to the first memory controller 16
The transmission line of the refresh request signal is connected to the fourth memory controller 19.

The refresh timer 20 repeats the countdown from the set value "N" to "0", and outputs a refresh request signal to the first memory controller 16 for each count of "0". The first memory controller 16 to which the refresh request signal is input causes the connected first memory bank 12 to execute the refresh, and when this is completed, the refresh request signal is transmitted to the second memory controller 17.

As described above, the first to fourth memory controllers 16 to 19 cause the connected first to fourth memory banks 12 to 15 to perform the refresh in accordance with the refresh request signals sequentially transmitted. That is, the connected memory banks 12 to 15 are refreshed, and the plurality of memory banks 12 to 15 are refreshed at different timings.

In such a configuration, the memory device 11 of the present embodiment is used as a storage device of a computer, and executes data read / write in response to an instruction of its CPU. Multiple memory banks 12-15
Since it consists of DRAM, it has good productivity but requires refreshing.

Data read / write is executed in the same manner as the memory device 1 described above, but refresh is executed in sequence in the plurality of memory banks 12-15. That is, the refresh timer 20 repeats the countdown from the set value “N” to “0”, and outputs the refresh request signal to the first memory controller 16 for each count of “0”. Then, the first memory controller 16
The connected first memory bank 12 is caused to execute refresh, and when this is completed, the refresh request signal is transmitted to the second memory controller 17. Similarly, since the second to third memory controllers 17 to 19 sequentially perform the refreshing of the second to third memory banks 13 to 15 in the same manner, all the memory banks 12 to 15 are refreshed. .

In the memory device 11 of the present embodiment, all of the plurality of memory banks 12 to 15 are refreshed as described above, but this refresh is performed at different timings of each of the plurality of memory banks 12 to 15. Since they are executed in order, they do not consume excessive power instantaneously. For this reason, a large-capacity drive power source is not required, and noise generation is eliminated.

Further, in the memory device 11 of the present embodiment, since the plurality of memory controllers 16 to 19 are individually connected to the plurality of memory banks 12 to 15, even if a certain memory bank 12 to 15 is performing refresh. The other memory banks 12-15 can be accessed. Therefore, even during refreshing, data read /
Writes can be performed and multiple memory banks 12
It is possible to improve work efficiency by efficiently using ~ 15.

Here, the state transition of the state machine that realizes the memory controllers 16 to 19 of the memory device 11 of the present embodiment will be described below with reference to FIG. First,
The first state is an idle state, and when a CS (Chip Select) signal corresponding to the decoded address signal is input, the state is changed to the second state and the RAS signal is output. At this time, if the R / W (Read / Write) signal is active, it transits to the fourth state and outputs the WRITE signal, then transits to the third state, and transits to the third state even if the R / W signal is inactive. To be done. CAS in this third state
A signal is output to transit to the fifth state, and in this fifth state, an ACK (Acknowledge) signal is output to transit to the first state. When transitioning to the first state in this way, all output signals are made inactive.

When the refresh request signal is input in the first state, the sixth state is entered and the CAS signal is output, and then the seventh state is entered and the RAS signal is output. When the state is changed to the eighth state, the refresh request signal is output to the next memory controller 17, etc., the state is changed to the first state, and all the output signals are made inactive.
The state machine as described above operates according to the CLOCK signal.

Further, the relationship of various signals of the memory device 11 of the present embodiment will be described below based on the time chart of FIG. First, at the time of data write, as shown in the right half of FIG. 5A, while the R / W signal is active, CS
The signal is made active, data is determined while this CS signal is active, and when the ACK signal becomes active, the CS signal becomes non-active and ends. When reading data, as shown in the left half of FIG.
Data is committed while both the S and ACK signals are active. Note that the refresh is executed by the CAS before RAS refresh as shown in FIG.

A second embodiment of the present invention will be described below with reference to FIGS. 4 and 5. With respect to the memory device 21 of the present embodiment, the same parts as those of the memory device 11 described as the first embodiment above are denoted by the same names and reference numerals, and detailed description thereof will be omitted.

First, the memory device 21 of the present embodiment is
As shown in FIG. 4, like the memory device 11 described above,
Although the plurality of memory controllers 22 are individually connected to the plurality of memory banks 12, ... Unlike the above-described memory device 11, the plurality of memory controllers 2 are connected.
A refresh timer 20 is connected to each of 2 ...

As shown in FIG. 5, the memory controllers 22 ... Decoder 2 corresponding to an address decoding unit.
3 are individually provided, to which the register 24 is connected. The output line of the register 24 is connected to the comparator 25 together with the address signal input line, and the output line of the comparator 25 is connected to the AND gate 26 together with the CS signal input line.

The decoder 23 decodes an address signal, which is an address signal, and a CS signal to generate a RAS / CA.
The S signal is generated and output to the register 24.
The register 24 is mapped in the memory space and changes the RAS / CAS signal which is an address signal corresponding to variable setting data. The comparator 2
5 compares the output signal of the register 24 with an address signal, and the AND gate 26 outputs the comparator 2
The logical product of the output signal 5 and the CS signal is output. Therefore, the memory controllers 22 ... Access the memory banks 12 ... In response to the RAS / CAS signals which are the address signals changed as described above.

In such a configuration, the memory device 21 of the present embodiment forms one memory space by the plurality of memory banks 12 ... And the addresses of the plurality of memory banks 12 ... Controller 22
Can be managed individually by….

That is, the address signal and the CS signal are decoded by the decoder 23, and the result is registered in the register 24.
If it is an access to, data setting is executed in this register 24. When accessing the memory banks 12 ..., The setting data of the register 24 and the address signal are compared by the comparator 25, and the AND product of the comparison result and the CS signal is output by the AND gate 26. Since the memory banks 12 ... Are accessed according to the output result, the memory banks 12 ... That are accessed corresponding to the address signal can be changed by the setting data of the register 24. The memory controllers 22 ... Reply with an ACK signal when the memory banks 12 ... Can be accessed as described above.

In the memory device 21 of the present embodiment, the addresses of the plurality of memory banks 12 forming one memory space can be individually managed by the plurality of memory controllers 22 ... Can be realized.

Next, a third embodiment of the present invention will be described with reference to FIG.
The following description is based on FIG. Regarding the memory device 31 of the present embodiment, the above-mentioned memory device 11
The same parts as the above are denoted by the same names and reference numerals, and detailed description thereof will be omitted.

First, the memory device 31 of the present embodiment is
As shown in FIG. 6, a plurality of memory controllers 32 ... Are individually connected to a plurality of memory banks 12 ..., and a refresh timer 20 is connected to each of the plurality of memory controllers 32. In the memory controllers 32, the use prohibition of the memory banks 12 is set to be switchable.

In such a structure, the memory device 31 of the present embodiment prohibits the use of a predetermined memory bank 12 ... And the memory controller 32 ...
Can be set to

That is, the state machines of the memory controllers 32 ... Operate in response to the CLOCK signal, and access or refresh the memory banks 12 ... In response to the CS signal which is the decoded address signal. At this time, a ME (Memory Enable) signal is also simultaneously input from the upper CPU to the memory controller 32.
When the E signal is active, the memory banks 12 ... Are accessed and refreshed as described above, but when they are non-active, neither access nor refresh is performed.

In this way, when the ME signal is active and the memory controllers 32 ... Do not access or refresh the memory banks 12 ..., This memory controller 32 ... Does not output the ACK signal either, so that the memory controller 32 ... And the memory bank. The upper CPU recognizes that 12 ... Does not exist.

Since the memory device 31 of the present embodiment can prohibit the use of the predetermined memory banks 12 in units of the memory controller 32 by making the ME signal inactive as described above, for example, , Use of only the defective memory bank 12 can be prohibited. Therefore, even if a defect occurs in one of the plurality of memory banks 12, ..., It is possible to prohibit the use of the defective memory bank 12 ... Without changing the hardware.

Here, the state transition of the state machine that realizes the memory controller 32 of the memory device 31 of the present embodiment will be described below with reference to FIG. First, the first state is the idle state, the CS signal and the ME signal are input, and only when the ME signal is active, the state transitions to the second state according to the CS signal. After that, as in the case of the memory device 11 described above, the data read / write is executed and then the first state is entered. Further, even when the refresh request signal and the ME signal are input in the first state, the transition to the sixth state is made according to the refresh request signal only when the ME signal is active, and after the refresh is executed, transition to the first state. To be done.

It should be noted that when the ME signal is inactive, the transition from the first state to the sixth state is not made. However, since the refresh timer 20 is connected to each of the plurality of memory controllers 32 ... It is not necessary to sequentially transmit, and even if the use of a predetermined memory bank 12 ... Is prohibited, the other memory banks 12 ... Can be refreshed without any problem.

Next, a fourth embodiment of the present invention will be described with reference to FIG.
This will be described below with reference to FIG. Regarding the memory device 41 of the present embodiment, the above-mentioned memory device 11
The same parts as the above are denoted by the same names and reference numerals, and detailed description thereof will be omitted.

First, the memory device 41 of the present embodiment is
As shown in FIG. 8, again, a plurality of memory controllers 42 ... Are individually connected to the plurality of memory banks 12, ... A refresh timer 20 is connected to each of these memory controllers 42. In the memory controllers 42, the refresh inhibition of the memory banks 12 is set to be switchable.

With such a configuration, the memory device 41 of the present embodiment can set the refresh inhibition of the predetermined memory banks 12 ... To the memory controllers 42 ... Connected thereto.

That is, the memory controllers 42 ... Access or refresh the memory banks 12 ... In response to the CS signal which is the decoded address signal, but the refresh is simultaneously input RE (Refresh Ena).
ble) signal is executed only when the signal is active, not executed when it is non-active.

Since the memory device 41 of the present embodiment can inhibit the refreshing of the predetermined memory banks 12 ... In units of the memory controllers 32 ... By making the RE signal inactive as described above, for example, , It is possible to reduce the power consumption by prohibiting the refresh only for the unused memory banks 12.

Here, the state transition of the state machine that realizes the memory controller 42 of the memory device 41 of this embodiment will be described below with reference to FIG. First, the first state is the idle state, the CS signal and the RE signal are input, and when the RE signal is active, the transition to the second state is made according to the CS signal. After that, as in the case of the memory device 11 described above, the data read / write is executed and then the first state is entered. But in the first state CS
When the signal and the non-active RE signal are input, it directly transits from here to the fifth state and outputs the ACK signal.

When the refresh request signal and the RE signal are input in the first state, the sixth state is transitioned to the sixth state according to the refresh request signal only when the RE signal is active, and the first state after the refresh is executed. Is transitioned to. When the RE signal is inactive, the first state does not transit to the sixth state, but here, the refresh timer 2 is provided to each of the plurality of memory controllers 42.
Since 0 is connected, even if the refreshing of the predetermined memory banks 12 ... Is prohibited, the refreshing of the other memory banks 12 ... Is executed without any problem.

The fifth embodiment of the present invention will be described below with reference to FIG. Note that, regarding the memory device 51 of the present embodiment, the same parts as those of the memory devices 11 and 21 described above use the same names and reference numerals, and detailed description thereof will be omitted.

First, the memory device 51 of the present embodiment is
It is equipped with first to fourth memory banks 12 to 15,
First to fourth memory controllers 52 to 55 are individually connected to the first to fourth memory banks 12 to 15. The refresh timer 20 is connected only to the first memory controller 52, and the transmission line of the refresh request signal is connected from the first memory controller 52 to the fourth memory controller 55.

The refresh timer 20 outputs a refresh request signal to the first memory controller 52 in response to the countdown, and the memory controller 52 outputs the refresh request signal.
Etc. transmits a refresh request signal to the next memory controller 53 etc. when the refresh of the connected memory banks 12-14 is completed. These memory controllers 52 to 55 are formed in the same structure as the memory controller 22 of the memory device 21 described above, and change the address signal in accordance with variable setting data.

In such a configuration, the memory device 51 of this embodiment has the same configuration as the memory device 11 described above.
The plurality of memory banks 12 to 15 are sequentially refreshed at different timings. Further, similarly to the memory device 21 described above, the addresses of the plurality of memory banks 12 to 15 forming one memory space are individually managed by the plurality of memory controllers 52 to 55.

Therefore, the memory device 51 according to the present embodiment.
Can easily and surely access the other memory banks 12 to 15 while the memory banks 12 to 15 are being refreshed, and the plurality of memory banks 12 to 15 can be used with high efficiency. It is possible to improve work efficiency.

A sixth embodiment of the present invention will be described below with reference to FIGS. 11 and 12. Regarding the memory device 61 of the present embodiment, the memory devices 11, 3
The same parts as 1 are denoted by the same names and reference numerals and detailed description thereof will be omitted.

First, the memory device 61 of the present embodiment is
As shown in FIG. 11, the first to fourth memory banks 12
˜15, and the first to fourth memory controllers 62 are provided in the first to fourth memory banks 12 to 15.
~ 65 are individually connected. Refresh timer 2
0 is connected only to the first memory controller 62, and a refresh request signal transmission line is connected from the first memory controller 62 to the fourth memory controller 65. The memory controller 62
Up to 65 are set so that the use prohibition of the memory banks 12 to 15 can be switched.

In such a configuration, the memory device 61 of the present embodiment has the same configuration as the memory device 11 described above.
The plurality of memory banks 12 to 15 are sequentially refreshed at different timings. Moreover, like the memory device 31 described above, the predetermined memory banks 12 ...
The use prohibition of 15 is set to the memory controllers 62 to 65 so as to be switchable.

Therefore, the memory device 61 of this embodiment is
For example, in a state where use of only the defective memory banks 12 to 15 is prohibited, the other memory banks 12 to 15 can be sequentially refreshed, and power consumption can be favorably reduced.

Here, the state transition of the state machine that realizes the memory controllers 62 to 65 of the memory device 61 of the present embodiment will be described below with reference to FIG. First, when the first state is the idle state, the CS signal and the ME signal are input, and only when this ME signal is active, C
The second state is transited according to the S signal. After that, as in the case of the memory device 11 described above, the data read / write is executed and then the first state is entered.

Also, when the refresh request signal and the ME signal are input in the first state, the transition to the sixth state is made according to the refresh request signal only when the ME signal is active. Similar to the case, after the refresh is executed, the refresh request signal is transmitted to the next memory controller 63 and the like, and the state is changed to the first state. When the ME signal is inactive and the refresh request signal is input, the first request state is directly changed to the eighth state, and the refresh request signal is transmitted to the next memory controller 63 without performing refresh. To be done.

The memory device 61 of the present embodiment is
The structure in which the memory devices 11 and 31 described above are combined is assumed, but the present invention is not limited to the above-described embodiment, and a memory device (not shown) having a structure in which the memory devices 11 and 41 described above are combined is also realized. it can. In that case, refreshing can be sequentially performed on the other memory banks 12 to 15 in a state where refreshing is prohibited only on the defective memory banks 12 to 15, so that power consumption can also be favorably reduced.

The seventh embodiment of the present invention will be described below with reference to FIG. Regarding the memory device 71 of the present embodiment, the same parts as the memory device 11 described above are
Detailed description will be omitted using the same names and reference numerals.

First, the memory device 71 of the present embodiment is
A plurality of memory controllers 72 are individually connected to the plurality of memory banks 12, and a refresh timer 20 is connected to each of the plurality of memory controllers 72. The memory controllers 72 have the same structure as the memory controller 22 of the memory device 21 described above, and the use prohibition of the memory banks 12 is set to be switchable.

In such a structure, the memory device 71 of the present embodiment has the same configuration as the memory device 31 described above.
The use prohibition of the predetermined memory banks 12 ... Is set to the memory controller 72 so as to be switchable, and like the memory device 21 described above, the plurality of memory banks 12 forming one memory space have a plurality of addresses. It is managed individually by the memory controller 72.

Therefore, the memory device 71 of the present embodiment is
For example, even if the use of the defective memory bank 12 is prohibited, the address can be set to another memory bank 12, so that even if the use of a predetermined memory bank 12 is prohibited, the upper CPU There is no need to change the behavior of.

An eighth embodiment of the present invention will be described below with reference to FIG. Regarding the memory device 81 of the present embodiment, the same parts as the memory device 61 described above are
Detailed description will be omitted using the same names and reference numerals.

First, the memory device 81 of the present embodiment is
It is equipped with first to fourth memory banks 12 to 15,
First to fourth memory controllers 82 to 85 are individually connected to the first to fourth memory banks 12 to 15. The refresh timer 20 is connected only to the first memory controller 82, and from the first memory controller 82 to the fourth memory controller 85.
Up to the refresh request signal transmission line is connected. The memory controllers 82 to 85 are formed in the same structure as the memory controller 22 of the memory device 21 described above, and the use prohibition of the memory banks 12 to 15 is set to be switchable.

In such a configuration, the memory device 81 of the present embodiment has the same structure as the memory device 11 described above.
The plurality of memory banks 12 to 15 are sequentially refreshed at different timings. Moreover, like the memory device 31 described above, the predetermined memory banks 12 ...
The use prohibition of 15 is set to the memory controllers 82 to 85 so as to be switchable. Further, like the memory device 21 described above, the addresses of the plurality of memory banks 12 to 15 forming one memory space are individually managed by the plurality of memory controllers 82 to 85.

Therefore, the memory device 81 of this embodiment is
For example, it is possible to sequentially refresh the other memory banks 12 to 15 while prohibiting use of only the defective memory banks 12 to 15. At this time, it is possible to easily and surely access the other memory banks 12 to 15 while the refresh of the certain memory banks 12 to 15 is being executed. Therefore, the power consumption can be favorably reduced, and the plurality of memory banks 12 to 1
5 can be used with high efficiency.

The memory device 81 of the present embodiment is
The structure in which the memory devices 11, 21 and 31 described above are combined is assumed, but the present invention is not limited to the above-described embodiment, and a memory device having a structure in which the memory devices 11, 21 and 41 described above are combined (not shown). Can also be realized. In that case, refreshing can be sequentially performed on the other memory banks 12 to 15 in a state where refreshing is prohibited only on the defective memory banks 12 to 15, so that power consumption can also be favorably reduced.

Next, a ninth embodiment of the present invention will be described with reference to FIG.
5 and FIG. 16 will be described below. With respect to the memory device 91 of the present embodiment, the same parts as those of the memory device 31 described above will be denoted by the same names and reference numerals and detailed description thereof will be omitted.

First, the memory device 91 of the present embodiment is
As shown in FIG. 15, a plurality of memory banks 12 ...
Are individually connected to each other, and prohibition of use of the memory banks 12 is set to each of the plurality of memory controllers 92. Memory check modules 93, which are memory check means, are individually connected to the memory controller 92 and the memory banks 12.

This memory check module 93 ...
As shown in FIG. 16, it has an up counter 94, a bus switch 95, a comparator 96, and an AND gate 97, and this AND gate 97 is connected to the memory controller 92. The up counter 94
Is inputted with an MC (Memory Check) signal and a CLOCK signal output from a high-order CPU, and outputs an R / W signal by the most significant 1 bit. The bus switch 95 is R /
The W signal switches between the address signals of the memory banks 12 ... And the recording data, and the comparator 96 compares the address signals of the memory banks 12 ... With the recording data. The AND gate 97 judges whether the comparison result of the comparator 96 is correct or not, and inputs this as a ME signal to the memory controllers 92 ...

With such a configuration, in the memory device 91 of the present embodiment, the plurality of memory check modules 93 ... Inspect each of the plurality of memory banks 12 ... Is prohibited in the memory controller 92 ...

More specifically, the memory check modules 93 ... Include the MC signal and CLOC output by the upper CPU.
The K signal is counted by the up counter 94, the data write signal is output until the most significant 1 bit thereof rises, and the data read signal is output when the 1 bit thereof rises. The bus switch 95 switches the address signal of the memory bank 12 ... And the recording data by such an R / W signal, and the comparator 96 compares this. If the comparison result is in agreement, the AND gate 97 is active M
The E signal is input to the memory controller 92, and if they do not match, the non-active ME signal is input.

Therefore, if the upper CPU outputs the MC signal, the memory check module 93 inspects the plurality of memory banks 12 for defects, and the memory controller 92 is set to prohibit use of the defective memory banks 12. Therefore, use of the defective memory banks 12 ... Is automatically prohibited.

Next, a tenth embodiment of the present invention will be described with reference to FIG.
This will be described below with reference to FIGS. With respect to the memory device 101 of the present embodiment, the same parts as those of the memory devices 21 and 91 described above use the same names and reference numerals, and detailed description thereof will be omitted.

The memory device 101 of this embodiment is similar to that of FIG.
As shown in FIG. 7, a plurality of memory banks 12 to 15 are also provided.
A plurality of memory controllers 102-105 are individually connected to the memory controller 102-105.
Each of the 105 is connected to the memory banks 12 to 1
Function for managing addresses of 5 and memory banks 12 to 15
Of the memory banks 12 to 15 and a function of freely setting the prohibition of use of the memory banks 12 to 15 are provided. Therefore, the memory controllers 102 to 105 individually inspect a plurality of memory banks 12 to 15 for defects and set the use prohibition so as to be switchable.
The address signal is changed so that a continuous memory space is secured with 15 excluded.

With such a configuration, in the memory device 101 of the present embodiment, the addresses of the memory banks 12 to 15 forming one memory space are individually managed by the memory controllers 102 to 105. And
The plurality of memory controllers 102 to 105 individually inspect the plurality of memory banks 12 to 15 for defects and prohibit their use if necessary. Therefore, even if the use of the memory bank 14 in which the defect is detected is prohibited, the address can be set in the other memory bank 15, and therefore, FIG.
As shown in, even if the use of the defective memory bank 14 is prohibited, one continuous memory space can be secured.

The memory device 101 of the present embodiment
As described above, even if the use of the defective memory bank 14 is prohibited, one continuous memory space can be secured, but this memory space has a lower capacity than the memory space in the initial state. If this causes a problem, it is preferable to prepare a spare memory bank 106 that is unused in the initial state, and change the address signal so that the spare memory bank 106 is complemented by the spare memory bank 106. . In this case, as shown in FIG. 19, even if the use of the defective memory bank 13 is prohibited, this is complemented by the spare memory bank 106, so that the same memory space as the initial state can be maintained.

[0085]

According to the first aspect of the present invention, each of the plurality of memory controllers individually connected to the plurality of memory banks refreshes the connected memory banks, and the plurality of memory banks are refreshed differently. By performing the refreshing at the timing of performing the refreshing, the refreshing of the plurality of memory banks is performed at the timings different from each other, so that the generation of noise can be eliminated without instantaneously consuming a large amount of power and the drive power supply Can be miniaturized.

According to a second aspect of the present invention, each of the plurality of memory controllers individually connected to the plurality of memory banks changes an address signal input from the outside in accordance with variable setting data. By accessing the memory bank connected corresponding to the changed address signal, the memory bank accessed corresponding to the address signal can be changed by the setting data. Can be managed freely.

According to the third aspect of the present invention, each of the plurality of memory controllers individually connected to the plurality of memory banks is set so that the use prohibition of the connected memory banks is set to be switchable. Since it is possible to prohibit the use of memory banks, for example, prohibiting the use of defective memory banks to prevent malfunctions,
It is possible to prevent unnecessary power consumption by prohibiting refreshing of unused memory banks.

According to a fourth aspect of the present invention, each of the plurality of memory controllers individually connected to the plurality of memory banks is set so that the refresh prohibition of the connected memory banks is switchable so that the predetermined memory banks can be refreshed. Since it is possible to prohibit refresh of the memory bank, for example,
It is possible to prevent power consumption by prohibiting refreshing of unused memory banks.

According to a fifth aspect of the present invention, in the second aspect of the present invention, each of the plurality of memory controllers individually connected to the plurality of memory banks refreshes the connected memory banks, and a plurality of memory banks are refreshed. By executing the refresh of the banks at different timings, for example, it is possible to access another memory bank during the refresh of a certain memory bank, and to use multiple memory banks with high efficiency. The efficiency can be improved.

According to a sixth aspect of the present invention, in the third or fourth aspect of the present invention, each of the plurality of memory controllers individually connected to the plurality of memory banks refreshes the connected memory banks, By executing the refresh of the memory banks at different timings, for example, the refresh timings of other memory banks can be made different while the refresh of the unused memory banks is prohibited. The power can be reduced well.

According to a seventh aspect of the invention, in the third aspect of the invention, each of the plurality of memory controllers individually connected to the plurality of memory banks can change the address signal input from the outside so as to change the setting data. Corresponding to the changed address signal and accessing the connected memory bank, for example,
Even if the use of a specific memory bank is prohibited, the address can be set to another memory bank to secure one continuous memory space.

According to an eighth aspect of the present invention, in the third or fourth aspect of the present invention, each of the plurality of memory controllers individually connected to the plurality of memory banks refreshes the connected memory banks, The memory banks are refreshed at different timings, the address signals input from the outside are changed in correspondence with the variable setting data, and the memory banks connected in correspondence with the changed address signals. By accessing the memory bank, for example, it is possible to prohibit the use and refresh of an unused memory bank, and even in such a state, it is possible to secure one continuous memory space by a plurality of memory banks. The refresh timings of the memory banks that form the space may be different. Since it is, it is possible to satisfactorily reduce the power consumption.

According to a ninth aspect of the present invention, in the third aspect of the present invention, the memory check means for individually inspecting a plurality of memory banks for defects and setting the use prohibition in the memory controller is provided. The use of defective memory banks can be automatically prohibited.

According to a tenth aspect of the present invention, in the seventh aspect of the present invention, memory check means for individually inspecting a plurality of memory banks for defects and setting the use prohibition to the memory controller is provided. Can automatically prohibit the use of a defective memory bank by changing the address signal so that one continuous memory space is secured while excluding the prohibited memory bank. One continuous memory space can be secured even in the state.

According to an eleventh aspect of the present invention, in the seventh aspect of the present invention, memory check means for individually inspecting a plurality of memory banks for defects and setting the use prohibition switchably in the memory controller is provided. A spare memory bank that is not used in
By changing the address signal so that the reserved memory bank is supplemented with the spare memory bank, the use of the defective memory bank can be automatically prohibited. Even in such a state, the same memory space as the initial state can be obtained. Can be secured.

[Brief description of drawings]

FIG. 1 is a block diagram showing a memory device according to a first embodiment of the present invention.

FIG. 2 is a state transition diagram showing a state machine of a memory controller.

FIG. 3 is a time chart showing various signals of the memory device.

FIG. 4 is a block diagram showing a main part of a memory device according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a memory controller.

FIG. 6 is a block diagram showing a main part of the memory device according to the first embodiment of the present invention.

FIG. 7 is a state transition diagram showing a state machine of the memory controller.

FIG. 8 is a block diagram showing a main part of a memory device according to a fourth embodiment of the present invention.

FIG. 9 is a state transition diagram showing a state machine of the memory controller.

FIG. 10 is a block diagram showing a memory device according to a fifth embodiment of the present invention.

FIG. 11 is a block diagram showing a memory device according to a sixth embodiment of the present invention.

FIG. 12 is a state transition diagram showing a state machine of the memory controller.

FIG. 13 is a block diagram showing a main part of a memory device according to a seventh embodiment of the present invention.

FIG. 14 is a block diagram showing a memory device according to an eighth embodiment of the present invention.

FIG. 15 is a block diagram showing a memory device according to a ninth embodiment of the present invention.

FIG. 16 is a block diagram showing a memory check module.

FIG. 17 is a block diagram showing a memory device according to a tenth embodiment of the present invention.

FIG. 18 is a schematic diagram showing a memory space.

FIG. 19 is a schematic diagram showing a memory space of a modified example.

FIG. 20 is a block diagram showing a conventional memory device.

FIG. 21 is a time chart showing various signals of the memory device.

[Explanation of symbols]

 11 memory device 12-15 memory bank 16-19 memory controller 21 memory device 22 memory controller 31 memory device 32 memory controller 41 memory device 42 memory controller 51 memory device 52-55 memory controller 61 memory device 62-65 memory controller 71 memory device 72 memory controller 81 memory device 82-85 memory controller 91 memory device 92 memory controller 93 memory check means 101 memory device 102-105 memory controller 106 memory bank

Claims (11)

[Claims] 1. A plurality of memory controllers are individually connected to a plurality of memory banks, each of the plurality of memory controllers refreshes the connected memory bank, and the plurality of memory banks are refreshed differently. A memory device characterized by being executed at the timing. 2. A plurality of memory controllers are individually connected to a plurality of memory banks, and each of the plurality of memory controllers changes an address signal input from the outside in accordance with variable setting data. A memory device, characterized in that the memory bank connected in response to a changed address signal is accessed. 3. A plurality of memory controllers are individually connected to a plurality of memory banks, and each of the plurality of memory controllers is set so that use prohibition of the connected memory banks is switchable. Memory device. 4. A plurality of memory controllers are individually connected to a plurality of memory banks, and each of the plurality of memory controllers is set so that refresh inhibition of the connected memory banks can be switched. Memory device. 5. A plurality of memory controllers are individually connected to a plurality of memory banks, each of the plurality of memory controllers refreshes the connected memory bank, and the plurality of memory banks are refreshed differently. 3. The memory device according to claim 2, wherein the memory device is executed at the timing. 6. A plurality of memory controllers are individually connected to a plurality of memory banks, each of the plurality of memory controllers refreshes the connected memory bank, and the plurality of memory banks are refreshed differently. 5. The memory device according to claim 3, wherein the memory device is executed at the timing of. 7. A plurality of memory controllers are individually connected to a plurality of memory banks, and each of the plurality of memory controllers changes an address signal input from the outside in accordance with variable setting data. 4. The memory device according to claim 3, wherein the memory bank connected in response to the changed address signal is accessed. 8. A plurality of memory controllers are individually connected to a plurality of memory banks, each of the plurality of memory controllers refreshes the connected memory banks, and the plurality of memory banks are refreshed differently. And changing the address signal input from the outside according to the variable setting data, and accessing the connected memory bank corresponding to the changed address signal. The memory device according to claim 3 or 4. 9. The memory device according to claim 3, further comprising a memory check unit for individually inspecting a plurality of memory banks for defects and setting a corresponding memory controller so that use prohibition can be switched. 10. A memory check unit for individually inspecting a plurality of memory banks for defects and setting a corresponding memory controller so that the use prohibition can be switched is provided, and the memory controller excludes the use prohibited memory banks. 8. The memory device according to claim 7, wherein the address signal is changed so that the memory space is continuous in the state. 11. A memory check means for individually inspecting a plurality of memory banks for defects and setting a corresponding memory controller so that use prohibition can be switched, and a spare memory bank which is unused in an initial state is provided. 8. The memory device according to claim 7, wherein the memory controller changes an address signal so as to complement the prohibited memory bank with a spare memory bank.