JPH0922590A - Semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage capable of rapid data read-out operation. SOLUTION: A second memory cell array 11 is composed of the memory cell of the same structure as a first memory cell array 10 written with the ROM data, and is written with '1' in one line and with '0' in the other line. A first output control signal generation circuit 12 and a second output control signal generation circuit 13 are the circuits equivalent to a sense amplifier circuit 55, and when the sense amplifier circuit 55 starts to read out the data from the first memory cell array 10, the circuits 12, 13 read out the data in the memory cells of respective lines of the second memory cell array 11. A control circuit 14 instructs to a data latch circuit 56 and an output buffer circuit 57 by a control signal VC1 so as to output the data VS read out by the sense amplifier circuit to the outside when the '1' is read out by the first output control signal generation circuit 12 and the '1' is read out by the second output control signal generation circuit 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a mask programmable ROM.
(Hereinafter referred to as mask ROM) and flash type EEPR
The present invention relates to data reading of a non-volatile semiconductor memory device such as an OM and an ultraviolet erasable EPROM.

[0002]

2. Description of the Related Art In recent years, semiconductor memory devices have been made larger in capacity as a result of advances in fine processing technology, and at the same time have been improved in speed, power consumption and multi-bit output due to advances in circuit technology. Specifically, a generally well-known address transition detection circuit (Address Transition Detector, hereinafter,
By controlling a sense amplifier circuit, an output buffer circuit, and the like using a clock generated by an ATD circuit or the like), high-speed and stable circuit operation and low power consumption are realized.

FIG. 5 is a circuit diagram of a conventional semiconductor memory device. Here, a mask ROM in which ROM data is written depending on the level of the threshold voltage of the memory cell transistor is taken as an example.

In FIG. 5, reference numeral 51 denotes a memory cell array in which memory cells M (i, j) (i = 1 to m, j = 1 to n) formed by n-type MOS transistors are arranged in m rows and n columns. Are arranged in an array. The gate of each memory cell M (i, j) is connected to a word line W _i (i = 1 to m), and the drain is connected to a bit line BL _j (j = 1 to n). QC _j (j = 1 to n) is a bit line selection transistor, its source is connected to each bit line BL _j , and its gate is a bit line selection signal line C _j (j = 1 to n).
Connected to each. Further, the drains of the transistors QC _j are commonly connected to the data output contact 54. Each word line W _i is connected to the row decoder 52, and each bit line selection signal line C _j is connected to the column decoder 53.

The ROM data of each memory cell M (i, j) is the threshold voltage V of the n-type MOS transistor.
_{Written according to} the height of _t . For example, the voltage V _t is set such that 0 V <V _t <1 V when the ROM data is “1”, and V _t > power supply voltage when the ROM data is “0”. The potential of the word line W _i is “H” level (power supply voltage)
Then the memory cell M (i,
j) is conductive, and the memory cell M whose ROM data is "0"
(I, j) remains non-conducting.

Reference numeral 55 is a sense amplifier circuit, which is conventionally well used as a data read circuit of a semiconductor memory device. It has a current detection type sense amplifier circuit configuration in which a load transistor QL for holding a potential and a precharge transistor QP for assisting charging of the bit line BL _{j for} a predetermined time are combined. The sense amplifier circuit 55 is connected to the contact 54 of the memory cell array 51, reads the data of the memory cell M (i, j) selected by the row decoder 52 and the column decoder 53, and outputs it as the data VS.

A data latch circuit 56 receives the data VS output from the sense amplifier circuit 55 as an input and outputs the data VL. The data VS is latched when the control signal VC ₂ input from the output control signal generating circuit 59 described later changes from the “L” level to the “H” level, and latched while the control signal VC ₂ maintains the “H” level. Data having the same phase as the generated data VS is output as the data VL. When the control signal VC ₂ is at “L” level, the latch is released and the data having the same phase as the input data VS is output as it is as the data VL.

Reference numeral 57 is a 3-state type output buffer circuit, which receives the data VL output from the data latch circuit 56 as an input and outputs the data VO. Control signal VC
_{When 2} is at "H" level, the data having the same phase as the data VL is output as it is as the data VO, and the control signal VC ₂
Is at the "L" level, the output terminal of the output buffer circuit 57 is in a high impedance state.

Reference numeral 58 denotes a precharge signal generation circuit composed of an ATD circuit, which generates a precharge signal VP which is at "L" level for a predetermined time from the start of reading the data written in the memory cell array 51.
The precharge signal VP becomes the gate input of the precharge transistor QP of the sense amplifier circuit 55.

Reference numeral 59 is an output control signal generating circuit, which is 2k.
(K is a natural number) Inverters (I ₁ , I ₂ , ...,
I _2k ) is composed of an inverter string and a logical product circuit connected in series. The inverter array receives the precharge signal VP as an input, and the AND circuit takes the logical product of the output signal of the inverter array and the precharge signal VP to obtain the control signal V.
Output C ₂ . The control signal VC ₂ controls the data latch circuit 56 and the output buffer circuit 57.

The operation of reading data from the memory cell M (i, j) in the i-th row and the j-th column of the semiconductor memory device configured as described above will be described with reference to the timing chart of FIG.

[0012] First, as to the "H" level of the word line W _i corresponding to the i-th row by the row decoder 52, the bit line select signal line corresponding to the j-th column by column decoder 53 C
Bit line selection transistor Q with _{j set} to "H" level
_Conduct C _j . At the same time, the sense amplifier activation signal VSE becomes "L" level, and the sense amplifier circuit 55
Goes from standby to active.

Further, the precharge signal VP has the time t ₂
Since it goes to "L" level during
The bit line BL _j connected to C _j is charged to a predetermined potential via the transistor QP. At this time, since the potential of the data VS output from the sense amplifier circuit 55 depends on the potential of the bit line BL _j at the start of precharge and the length of the precharge time t ₂ , it is “H” level or “L” level. Is in an indeterminate state.

After the completion of precharge, when the ROM data of the selected memory cell M (i, j) is "1", the memory cell M (i, j) becomes conductive and the charge of the bit line BL _j is stored in the memory. cell M (i, j) is discharged via the output data VS of the sense amplifier circuit 55 is determined in time after t ₁ "H" level. In addition, the selected memory cell M (i,
When the data of j) is “0”, the memory cell M (i,
Since j) remains in the non-conducting state, the bit line BL _j is continuously charged by the load transistor QL, and the output data VS of the sense amplifier circuit 55 becomes “L” after time t _0.
Confirm the level. Therefore, the output confirmation time t _AC required from the start of the read operation to the output confirmation of the sense amplifier circuit 55 is t _AC = t ₂ + (the larger _one of t ₀ or t ₁ ).

On the other hand, in the output control signal generation circuit 59, the control signal VC ₂ is obtained by taking the logical product of the signal obtained by delaying the precharge signal VP by the time t ₃ by the 2k inverter array and the precharge signal VP. Time (t ₂ + t
It becomes "L" level during ₃ ). Control signal VC ₂ is "L"
The output terminal of the output buffer circuit 57 is kept at high impedance during the level. When the control signal VC ₂ changes to “H” level, the output data VS of the sense amplifier circuit 55
Is latched by the data latch circuit 56 and output from the output buffer circuit 57 as data VO. Therefore, the output on time t _ON required from the start of the read operation to the data output of the output buffer circuit 57 is t _ON = t ₂ +
It becomes t ₃ .

The semiconductor memory device shown in FIG. 5 is designed so that the output on-time t _ON and the output confirmation time t _AC do not cause racing, that is, t _ON ≧ t _AC . Therefore, the data latch and the data output to the outside are performed after the read data from the memory cell is determined.

Most of the semiconductor memory devices have a multi-bit output structure of 8 to 16 bits, and 8 to 16 read circuits operate in parallel. Therefore, when the output buffer circuit 57 operates, the output buffer circuit 57 normally operates at tens to hundreds of pF. The external load capacities will be driven all at once. Therefore, by performing the data latch and the data output to the outside after the read data from the memory cell is determined, it is possible to avoid the noise generated at the time of the data output and to operate the sense amplifier circuit 55 stably. Further, by avoiding the output of the uncertain data from the output buffer circuit 57 during the precharge operation period, useless current consumption can be reduced.

[0018]

However, the conventional semiconductor memory device has the following problems.

In the conventional semiconductor memory device shown in FIG. 5, it is necessary to design so that the output on time t _ON is always longer than the output fixed time t _AC .

Here, the output on time t _ON can be set by the delay time t ₃ of the inverter train in the output control signal generating circuit 59. On the other hand, the output confirmation time t
_AC is the sensitivity and operating speed of the sense amplifier circuit 55 with respect to ROM data, the current drive capability of the memory cell M (i, j), the parasitic capacitance of the bit line BL _j (electrostatic formed between the bit line and the semiconductor substrate, etc. A pn formed in a junction region between a capacitor and a diffusion region such as a drain portion of a memory cell and a semiconductor substrate
Sum of junction capacitance) and the delay time at the word line W _i , etc.
It is determined by several different factors. In addition, there are differences between the devices due to variations in characteristics due to the manufacturing process,
It also varies with time due to the dependency on the power supply voltage or temperature.

Therefore, it is necessary to set the output on time t _ON with a sufficient margin with respect to the output fixed time t _AC . However, for this reason, there is a problem that it is difficult to realize a higher speed data read operation.

Further, in the case of designing to expand or reduce the memory capacity with the same circuit configuration, in the conventional semiconductor memory device, the output control signal generation circuit 59 is considered in consideration of various factors that determine the output determination time t _AC. By adjusting the delay time t ₃ of the inverter array of the output ON time t _ON
Had to be optimized. Therefore, there is also a problem that the optimum circuit design cannot be easily performed.

The present invention solves a problem in a conventional semiconductor memory device, and provides a semiconductor memory device capable of performing a data read operation at a higher speed than the conventional one and facilitating optimum circuit design. To aim.

[0024]

To achieve the above object, the present invention provides a semiconductor memory device having a memory cell array and a data read circuit, and a memory having the same shape as the memory cells forming the memory cell array. A memory cell array including cells and a circuit equivalent to the data read circuit for reading data from the memory array are further added,
The control signal output from the circuit controls so that the data read from the memory cell array is output to the outside without unnecessary waiting time.

The solving means taken by the invention of claim 1 is
A first memory cell array in which a plurality of memory cells storing any one data of "1" or "0" are arranged in a matrix for a desired storage capacity, and each row of the first memory cell array. And a row decoder connected to each of the first memory cell arrays to indicate the row in which the memory cells to be read out are arranged, and memory cells to be read out from each row are connected to each column of the first memory cell array. A column decoder for instructing a certain column, and a data read circuit for reading out data of memory cells arranged in a row instructed by the row decoder and in a column instructed by the column decoder in the first memory cell array. A semiconductor memory device having an output buffer circuit for outputting the data read by the data reading circuit to the outside. Hisage a plurality of memory cells having the same structure as a memory cell constituting the first memory cell array is 2
A second memory cell array arranged in columns, wherein the memory cells in the first column all store "1" while the memory cells in the second column all store "0"; The circuit is equivalent to the data read circuit, and when the data read circuit reads data of one memory cell of the first memory cell array, the data read circuit is arranged in the first column of the second memory cell array. A first circuit for reading data of one memory cell and a circuit equivalent to the data reading circuit, wherein when the data reading circuit reads data of one memory cell of the first memory cell array, A second circuit for reading the data of one memory cell arranged in the second column of the second memory cell array; and the data read by the first circuit and the second circuit as input, 1 When the data read by the circuit becomes "1" and the data read by the second circuit becomes "0", the data read by the data read circuit is transferred to the output buffer circuit. The control circuit for instructing output to the outside is further provided.

According to a second aspect of the invention, in the configuration of the first aspect of the invention, the control circuit instructs the output buffer circuit to output the data read by the data read circuit to the outside, and then the control circuit outputs the data to the outside. A configuration for instructing the data read circuit to enter the standby state is added.

The solution means taken by the invention of claim 3 is
A first memory cell array in which a plurality of memory cells storing any one data of "1" or "0" are arranged in a matrix for a desired storage capacity, and each row of the first memory cell array. And a row decoder connected to each of the first memory cell arrays to indicate the row in which the memory cells to be read out are arranged, and memory cells to be read out from each row are connected to each column of the first memory cell array. A column decoder for instructing a certain column, and a data read circuit for reading out data of memory cells arranged in a row instructed by the row decoder and in a column instructed by the column decoder in the first memory cell array. A latch circuit that holds and outputs the data read by the data read circuit, and a latch circuit that outputs the data. Assuming a semiconductor memory device including an output buffer circuit for outputting data to the outside, a plurality of memory cells having the same structure as the memory cells forming the first memory cell array are arranged in two columns. The memory cells in the column of "1" store all "1", while the memory cells in the second column store "0", and a circuit equivalent to the data read circuit. Yes,
When the data read circuit reads the data of one memory cell of the first memory cell array, the first data of the one memory cell arranged in the first column of the second memory cell array is read. And a circuit equivalent to the data read circuit, wherein when the data read circuit reads data of one memory cell of the first memory cell array, a second column of the second memory cell array is read. Second reading data of one arranged memory cell
And the data read by the first circuit and the second circuit as input, the data read by the first circuit becomes “1” and read by the second circuit. When the stored data becomes “0”, the latch circuit is instructed to hold and output the data read by the data read circuit, and the output buffer circuit outputs the data output from the latch circuit. And a control means for instructing to output the output to the outside.

According to a fourth aspect of the present invention, in the configuration of the third aspect, the control circuit instructs the output buffer circuit to output the data output from the latch circuit to the outside, and then reads the data. A configuration for instructing the circuit and the latch circuit to enter the standby state is added.

The solution means taken by the invention of claim 5 is as follows.
A first memory cell array in which a plurality of memory cells storing any one data of "1" or "0" are arranged in a matrix for a desired storage capacity, and each row of the first memory cell array. And a row decoder connected to each of the first memory cell arrays to indicate the row in which the memory cells to be read out are arranged, and memory cells to be read out from each row are connected to each column of the first memory cell array. A column decoder for instructing a certain column, and a data read circuit for reading out data of memory cells arranged in a row instructed by the row decoder and in a column instructed by the column decoder in the first memory cell array. A semiconductor memory device having an output buffer circuit for outputting the data read by the data reading circuit to the outside. Hisage a plurality of memory cells having the same structure as a memory cell constituting the first memory cell array 1
The plurality of memory cells is a circuit equivalent to the second memory cell array in which all of the plurality of memory cells store the same data and the data read circuit, and the data read circuit is the first memory. When reading data of one memory cell of the cell array, the data of one memory cell of the second memory cell array is read, and the read data is stored in the memory cell of the second memory cell array. And a control circuit for instructing the output buffer circuit to output the data read by the data reading circuit to the outside when the data matches the existing data.

According to a sixth aspect of the present invention, in the configuration of the fifth aspect, the control circuit instructs the output buffer circuit to output the data read by the data read circuit to the outside, and A configuration for instructing the data read circuit to enter the standby state is added.

The solution means taken by the invention of claim 7 is as follows:
A first memory cell array in which a plurality of memory cells storing any one data of "1" or "0" are arranged in a matrix for a desired storage capacity, and each row of the first memory cell array. And a row decoder connected to each of the first memory cell arrays to indicate the row in which the memory cells to be read out are arranged, and memory cells to be read out from each row are connected to each column of the first memory cell array. A column decoder for instructing a certain column, and a data read circuit for reading out data of memory cells arranged in a row instructed by the row decoder and in a column instructed by the column decoder in the first memory cell array. A latch circuit that holds and outputs the data read by the data read circuit, and a latch circuit that outputs the data. Assuming a semiconductor memory device including an output buffer circuit for outputting data to the outside, a plurality of memory cells having the same structure as the memory cells forming the first memory cell array are arranged in one column. Is a circuit equivalent to the second memory cell array storing all the same data and the data read circuit, and the data read circuit outputs data of one memory cell of the first memory cell array. Is read, the data in the memory cell of the second memory cell array is read, and when the read data matches the data stored in the memory cell of the second memory cell array, The output buffer circuit is instructed to hold and output the data read by the data read circuit, and the output buffer circuit is provided with the latch circuit. It is an arrangement further comprising a control circuit for instructing to output a et output data to the outside.

According to an eighth aspect of the present invention, in the configuration of the seventh aspect, the control circuit instructs the output buffer circuit to output the data output from the latch circuit to the outside, and then reads the data. A configuration for instructing the circuit and the latch circuit to enter the standby state is added.

According to the structure of the first aspect of the present invention, when the data of the one memory cell of the first memory cell array is read by the data read circuit, the first circuit of the second memory cell array is read by the first circuit. The data of one memory cell arranged in a column is read out and the data of one memory cell arranged in a second column of the second memory cell array is read out by the second circuit. All the memory cells in the first column of the second memory cell array store "1", while all the memory cells in the second column store "0". When the data read by the second circuit becomes "1" and the data read by the second circuit becomes "0", the data read by the data reading circuit is output to the output buffer circuit to the outside. Instruct them to do so. Here, the memory cells forming the second memory cell array have the same structure as the memory cells forming the first memory cell array, and moreover, the first circuit and the second circuit
Is a circuit equivalent to the data read circuit. Therefore, the time required for the data read by the first circuit to become "1" and the time required for the data read by the second circuit to become "0" are It is almost equal to the time required to read the data. Therefore, the data read from the first memory cell array is output from the output buffer circuit without unnecessary waiting time.

According to the second aspect of the invention, after the data is output from the output buffer circuit, the data read circuit goes into a standby state.

According to the structure of the third aspect of the invention, when the data of the one memory cell of the first memory cell array is read by the data read circuit, the first circuit of the second memory cell array is read by the first circuit. The data of one memory cell arranged in a column is read out and the data of one memory cell arranged in a second column of the second memory cell array is read out by the second circuit. The memory cells in the first column of the second memory cell array all store "1", while the memory cells in the second column all store "0". The control circuit reads the data read by the latch circuit when the data read by the first circuit becomes "1" and the data read by the second circuit becomes "0". It instructs to hold and output the data, and instructs the output buffer circuit to output the data output from the latch circuit to the outside. Here, the memory cells forming the second memory cell array have the same structure as the memory cells forming the first memory cell array, and the first circuit and the second circuit are equivalent to the data read circuit. Is. Therefore, the time required for the data read by the first circuit to become "1" and the time required for the data read by the second circuit to become "0" are It is almost equal to the time required to read the data. Therefore,
The data read from the first memory cell array will be output from the output buffer circuit via the latch circuit without unnecessary waiting time.

According to the fourth aspect of the invention, after the data is output from the output buffer circuit, the data read circuit and the latch circuit are in a standby state.

According to the structure of the invention of claim 5, when the data of the one memory cell of the first memory cell array is read by the data read circuit, the second data is read by the control circuit.
The data in one memory cell of the memory cell array is read. The memory cells of the second memory cell array all store the same data. When the read data matches the data stored in the memory cells of the second memory cell array, the control circuit instructs the output buffer circuit to output the data output from the latch circuit to the outside. Here, the memory cells forming the second memory cell array have the same structure as the memory cells forming the first memory cell array, and the control circuit is a circuit equivalent to the data read circuit. Therefore, the time required for the data read by the control circuit to match the data stored in the memory cells of the second memory cell array is substantially equal to the time required for the data read circuit to read the data. Become. Therefore, the data read from the first memory cell array is output from the output buffer circuit without unnecessary waiting time.

According to the sixth aspect of the invention, after the data is output from the output buffer circuit, the data read circuit goes into a standby state.

According to the configuration of the invention of claim 7, when the data of the one memory cell of the first memory cell array is read by the data read circuit, the second data is read by the control circuit.
The data in one memory cell of the memory cell array is read. The memory cells of the second memory cell array all store the same data. The control circuit instructs the latch circuit to hold and output the data read by the data read circuit when the read data matches the data stored in the memory cell of the second memory cell array. At the same time, it instructs the output buffer circuit to output the data output from the latch circuit to the outside. Here, the memory cells forming the second memory cell array have the same structure as the memory cells forming the first memory cell array, and the control circuit is a circuit equivalent to the data read circuit. Therefore, the time required for the data read by the control circuit to match the data stored in the memory cells of the second memory cell array is substantially equal to the time required for the data read circuit to read the data. Become. Therefore, the data read from the first memory cell array is output from the output buffer circuit via the latch circuit without unnecessary waiting time.

According to the eighth aspect of the invention, after the data is output from the output buffer circuit, the data read circuit and the latch circuit are in a standby state.

[0041]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 1 is a circuit diagram of a semiconductor memory device according to the first embodiment. Here, as in the conventional example, a mask ROM in which ROM data is written depending on whether the threshold voltage of the memory cell transistor is high or low is taken as an example. In FIG. 1, the same parts as those in FIG. 5 are designated by the same reference numerals, and only the different parts will be described.

Reference numeral 10 denotes a first memory cell array, which is similar to the memory cell array 51 in the conventional example shown in FIG. 5 and is formed by an n-type MOS transistor.
(I, j) are arrayed in a matrix of m rows and n columns. The present embodiment further includes a second memory cell array 11 in which memory cells are arranged in a matrix of m rows and 2 columns. That is,
The memory cell M (i, n + 1) (i = 1) in the (n + 1) th column
.About.m) are added and memory cells M (i, n + 2) (i = 1 to m) are added to the (n + 2) th column to form a matrix array configuration of m rows (n + 2) columns. There is. Memory cells M (i, n + 1) and M (i, n + 2)
Is also formed by an n-type MOS transistor having the same shape as that of the conventional memory cell. Further, the second memory cell array 11 has a first memory cell array when viewed from the row decoder 52A.
Of the memory cell array 10 of FIG.

Memory cells M (i, n + 1) and M (i,
The gate of (n + 2) is the word line W _i (i
= 1 to m), respectively. The drain of the memory cell M (i, n + 1) in the (n + 1) th column is connected to the bit line BL _{n + 1,} and the memory cell M in the (n + 2) th column is
The drain of (i, n + 2) is connected to the bit line BL _{n + 2} . The bit line BL _{n + 1} is connected to the source of the n-type MOS transistor QC _{n + 1} , and the bit line BL _{n + 2}
Is connected to the source of the n-type MOS transistor QC _{n + 2} . The transistors QC _{n + 1} and QC _{n + 2} are formed in the same shape as the bit line selection transistor QC _j (j = 1 to n), and their gates are connected to the bit line selection signal line C ₀ , respectively. The bit line selection signal line C ₀ is connected to the column decoder 53A like other bit line selection signal lines C _j (j = 1 to n).

Memory cell M (i, n +) in the (n + 1) th column
"1" is written in all of 1), and "0" is written in all of the memory cells M (i, n + 2) in the (n + 2) th column. Further, the potential of the bit line selection signal line C ₀ is set to the memory cell M (i, j) (i) from which data is read.
= 1 to m, j = 1 to n), the level becomes "H" during the read operation.

QR ₁ and QR ₂ are transistors for setting the bit line initial potential. The drain of the transistor QR ₁ is connected to the bit line BL _{n + 1} , while the drain of the transistor QR ₂ is the bit line BL _{n + 2.} And the sources are each grounded. The gates of the transistors QR ₁ and QR ₂ are bit line reset signal lines R
The bit line reset signal line R is connected to the row decoder 52A. Bit line reset signal line R
Potential changes to "H" level after the data read operation of the memory cell is completed, and the bit lines BL _{n + 1} and BL
The potential of _{n + 2} is set to 0V, and changes to "L" level at the start of the next data read operation.

Reference numeral 12 is a first output control signal generating circuit as a first circuit, which has the same circuit configuration as the sense amplifier circuit 55 as a data reading circuit. The first output control signal generation circuit 12 includes a second memory cell array 1
1 (n + 1) th memory cell column and transistor QC
They are connected via _{n + 1} and are controlled by the precharge signal VP and the sense amplifier activation signal VSE. ROM data “1” is written in the connected memory cells, and the output signal VS ₁ of the first output control signal generation circuit 12 becomes “H” level when the data read operation is completed.

Reference numeral 13 is a second output control signal generation circuit as a second circuit, and the first output control signal generation circuit 12
The same circuit configuration as the sense amplifier circuit 55. The second output control signal generation circuit 13 is connected to the (n + 2) th memory cell column of the second memory cell array 11 via the transistor QC _{n + 2,} and is connected to the precharge signal VP and the sense amplifier activation. It is controlled by the signal VSE. ROM data "0" is written in the connected memory cells, and the output signal of the second output control signal generation circuit 13 becomes "L" level when the data read operation is completed.

Reference numeral 14 is a control circuit, which is a logical product circuit 14a.
And a phase inversion inverter IV ₁ . The phase inversion inverter IV ₁ inverts the output signal of the second output control signal generation circuit 13 and outputs the signal VS ₀ . The AND circuit 14a includes the output signal VS _{1 of} the first output control signal generation circuit 12 and the phase inversion inverter IV _1.
Output VS ₀ of the above is obtained and output as a control signal VC ₁ . That is, the RO of the memory cell in the (n + 1) th column
RO of the memory cell of the M data “1” and the (n + 2) th column
When the reading operation of the M data “0” is completed, the control signal VC ₁ becomes “H” level. This control signal VC
_{By 1} , the data latch circuit 56 and the output buffer circuit 57 are controlled.

The operation of the semiconductor memory device configured as described above will be described with reference to the timing chart of FIG.

In the initial state, since the bit line reset signal R is at "H" level, the bit line initial potential setting transistors QR ₁ and QR ₂ are conducting. Therefore,
The bit lines BL _{n + 1} and BL _{n + 2} are set to the ground potential in the initial state.

When the data read operation is started, the data of the memory cell M (i, j) selected by the row decoder 52A and the column decoder 53A is read through the sense amplifier circuit 55, as in the conventional example.

Simultaneously with the start of the data read operation, the bit line reset signal R changes to the "L" level, and the bit line initial potential setting transistors QR ₁ and QR ₂ are turned off. At the same time, the word line W _i becomes "H" level, the bit line selection signal C ₀ becomes "H" level, and the transistors QC _{n + 1} and QC _{n + 2} become conductive, so that the memory cell M (i, j). ) And memory cell M in the same row
(I, n + 1) and M (i, n + 2) will be selected. Further, the precharge signal VP and the sense amplifier activation signal VSE cause the sense amplifier circuit 55 to start operating, and the first output control signal generating circuit 12 and the second output control signal generating circuit 13 also start operating. Data reading of the memory cells M (i, n + 1) and M (i, n + 2) is started.

After the end of the precharge operation, the read operation of the data "1" of the memory cell in the (n + 1) th column is completed at time t ₁ , and VS ₁ becomes "H" level. After the end of the precharge operation, at time t ₀ , the read operation of the data “0” of the memory cell in the (n + 2) th column is completed, and V
S ₀ becomes “H” level. Therefore, when the reading of both data is completed, the output signal control signal VC ₁ becomes “H” level, the data latch circuit 56 latches the output data VS of the sense amplifier circuit 55, and the output buffer circuit 57 outputs the data latch circuit 57. The output data VL of 56 is output as data VO.

Here, since the second memory cell array 11 is located farther from the row decoder 52A than the first memory cell array 51, the output signal control signal VC ₁ becomes "H" level. The timing is slightly later than the timing when the data reading by the sense amplifier circuit 55 is completed. Therefore, the read data can be output to the outside without needing a useless waiting time. Therefore, speeding up of the data read operation can be realized.

Note that, for example, row 1024 bits × column 102
When the present embodiment is applied to a ROM having a capacity of 1 Mbit of 4 bits, it suffices to add two columns of memory cells regardless of the output bit configuration. Therefore, the increment of the memory cell array area due to the added memory cells is It is about 0.2%, and the area increment is within 0.5% even if circuits other than the memory cells are included. Therefore, the increase in the chip size area according to the present embodiment is negligible.

Although an example of the NOR type mask ROM is shown here, it goes without saying that it can be applied to a read circuit of general nonvolatile memory such as a NAND type mask ROM, a flash type EEPROM, an ultraviolet erasing type EEPROM and the like. In the present embodiment, the data latch circuit 56 and the output buffer circuit are controlled by the control signal VC ₁ , but the output of the sense amplifier circuit 55 is output to the outside only through the output buffer circuit 57, and the output is performed. The buffer circuit 57 may be controlled by the control signal VC ₁ . Further, in the configuration of this embodiment, the sense amplifier activation signal VSE is also controlled by the control signal VC ₁ , and after the data is output from the output buffer circuit 57, the data latch circuit 56 and the sense amplifier circuit 55 are placed in a standby state. It is also possible to realize low power consumption.

(Second Embodiment) FIG. 3 is a circuit diagram of a semiconductor memory device according to the second embodiment. Here, a contact-type mask ROM is taken as an example.

In the contact-type mask ROM, whether or not the drain of the memory cell transistor and the bit line are connected corresponds to "1" and "0" of the ROM data. Generally, the access time of ROM data depends on the size of the parasitic capacitance of the bit line. This parasitic capacitance is divided into an electrostatic capacitance between the bit line and the semiconductor substrate, and a pn junction capacitance formed between the drain region of the memory cell and the semiconductor substrate. The contact-type mask ROM has a feature that the access time depends on the content of the ROM data because the number of memory cells connected to the bit line is different depending on the ROM data to be stored and therefore the parasitic capacitance is different for each bit line.

In FIG. 3, the same parts as those in FIGS. 1 and 5 are designated by the same reference numerals, and only the different parts will be described.

Reference numeral 20 denotes a first memory cell array, which is constituted by arranging contact type memory cells in a matrix of m rows and n columns. Where ●
Indicates that the drain of the memory cell is connected to the bit line, and ○ indicates that the drain of the memory cell is not connected to the bit line. ● corresponds to ROM data “1”, while ◯ corresponds to ROM data “0”.

Further, in this embodiment, the memory cell M (i,
second memory cell array 2 in which (n + 1) are arranged in one column
1 is provided. Each gate of the memory cell M (i, n + 1) is connected to a word line W _i (i = 1 to m). Further, the drains of the memory cells M (i, n + 1) are all connected to the bit line BL _{n + 1} via contacts, and the parasitic capacitance of the bit line BL _{n + 1} is different from that of the other bit line BL _j
It is set to be larger than the parasitic capacitance of (j = 1 to n). The bit line BL _{n + 1} is a transistor QC _{n + 1}
Connected to the source. The transistor QC _{n + 1} is formed in the same shape as the bit line selection transistor QC _j (j = 1 to n), and the gate thereof is the bit line selection signal line C.
Connected to ₀ . The bit line selection signal line C ₀ is connected to the column decoder 53B like the other bit line selection signal lines C _j (j = 1 to n).

QR ₁ is a transistor for setting a bit line initial potential, the drain of which is connected to the bit line BL _{n + 1} and the source of which is grounded. The gate is connected to the bit line reset signal line R, and the bit line reset signal line R is connected to the row decoder 52B. The potential of the bit line reset signal line R changes to the “H” level after the data read operation of the memory cell is completed, sets the potential of the bit line BL _{n + 1} to 0 V, and becomes “V” at the start of the next data read operation. Change to L "level.

Reference numeral 22 denotes a sense amplifier circuit as a data read circuit, which is a precharge type sense amplifier circuit often used in a small capacity ROM. The sense amplifier circuit 22 includes a precharging transistor QP ₁ and a potential fixing n-type MOS transistor Q during non-reading operation.
It is composed of N ₁ and an inverter IV ₂ . The contact 22a has a bit line selection transistor QC _i.
The drains of are commonly connected. Transistor QP
_The precharge signal VP is input to the gate of ₁ , and the drain is connected to the contact 22a. Transistor QN
_The sense amplifier activation signal VSE is input to the gate of ₁ , and the source is connected to the contact 22a. The input terminal of the inverter IV ₂ is also connected to the contact 22a, and the data VS is output from the output terminal.

An output control signal generating circuit 23 as a control circuit has the same circuit configuration as the sense amplifier circuit 22. The output control signal generation circuit 23 is connected to the memory cell column of the second memory cell array 21 via the transistor QC _{n + 1} and is controlled by the precharge signal VP and the sense amplifier activation signal VSE. The control signal VC ₁ output from the output control signal generation circuit 23 becomes “L” level at the same time when the data read operation is started, and the ROM data “1” is written in the connected memory cell. When it is completed, it goes to "H" level. The data latch circuit 56 and the output buffer circuit 57 are controlled by the control signal VC ₁ .

The operation of the semiconductor memory device configured as described above will be described with reference to the timing chart of FIG.

In the initial state, since the bit line reset signal R is at "H" level, the bit line initial potential setting transistor QR ₁ is conductive. Therefore, as in the first embodiment, the bit line BL _{n + 1} is set to the ground potential in the initial state.

In the data read operation, the memory cell M (i, j) to be read is selected by the row decoder 52B and the column decoder 53B. Precharge signal V
When P goes to "L" level, the transistor QP ₁
Becomes conductive, the contact 2 of the sense amplifier circuit 22
2a is precharged to a predetermined potential. When the selected memory cell M (i, j) holds the ROM data “1” (the drain has a contact with the bit line),
Simultaneously with the end of the precharge operation, the memory cell M (i, j)
The bit line charge is discharged via the V.sub.S and VS becomes "H" level. In addition, the selected memory cell M (i, j) is R
When the OM data “0” is held (the drain has no contact with the bit line), VS is output at the “L” level at the end of the precharge operation. Therefore, the data read operation becomes slowest when the read data is “1” and the memory cell holding the data is connected to the bit line having the maximum parasitic capacitance.

Simultaneously with the start of the data read operation, the bit line reset signal R changes to "L" level, and the bit line initial potential setting transistor QR ₁ becomes non-conductive. At the same time, since the word line W _i becomes "H" level, the bit line selection signal C ₀ becomes "H" level, and the transistor QC _{n + 1} becomes conductive, the memory cell M
The memory cell M (i, n + 1) in the same row as (i, j) is selected. Further, by the precharge signal VP and the sense amplifier activation signal VSE, the sense amplifier circuit 22 starts operating, the output control signal generating circuit 11 starts operating, and data reading of the memory cell M (i, n + 1) starts. To be done.

After the end of the precharge operation, the data read operation of the memory cell M (i, n + 1) is completed after the time t ₁ , and the output of the output control signal generating circuit 11, that is, the control signal VC ₁ becomes the “H” level. Control signal VC ₁ is "H"
At the level, the data latch circuit 56 latches the output data VS of the sense amplifier circuit 22 and the output buffer circuit 57 outputs the output data VL of the data latch circuit 56.
Is output.

Since the bit line BL _{n + 1} of the second memory cell array 11 has a larger parasitic capacitance than the other bit lines BL _{j, the} timing when the output signal control signal VC ₁ becomes "H" level is set. It is slightly later than the timing when the data reading by the sense amplifier circuit 22 is completed.
Therefore, the read data can be output to the outside without needing a useless waiting time. Therefore, speeding up of the data read operation can be realized.

The contact type mask RO is used here.
An example of using the precharge type sense amplifier circuit for reading data of M is shown, but the same sense amplifier circuit is used for reading data of all nonvolatile memories such as NAND type mask ROM, flash type EEPROM, and ultraviolet erasing type EEPROM. It goes without saying that the present embodiment can also be applied in this case. Further, in the present embodiment, the data latch circuit 56 and the output buffer circuit 57 are controlled by the control signal VC ₁ , but the output of the sense amplifier circuit 22 is output to the outside through only the output buffer circuit 57, The output buffer circuit 57 may be controlled by the control signal VC ₁ . Further, in the configuration of the present embodiment, the sense amplifier activation signal VSE is also controlled by the control signal VC ₁ , and after the data is output from the output buffer circuit 57, the sense amplifier circuit 55 together with the data latch circuit is set to the standby state. It is also possible to realize low power consumption. Further, here, the data “1” is set when the memory cell is connected to the bit line and the data “0” is set when the memory cell is not connected. It goes without saying that the present embodiment can be applied even if the data is "0" if connected and the data "1" if not connected.

[0072]

According to the semiconductor memory device of the first or fifth aspect of the present invention, the data read from the first memory cell array is output from the output buffer circuit without unnecessary waiting time. High-speed data read operation becomes possible. Further, even in the case of designing to expand or reduce the memory capacity with the same circuit configuration, it is not necessary to consider various factors that determine the time required for reading data, so that the optimum circuit design can be facilitated.

According to the semiconductor memory device of the second or sixth aspect of the present invention, since the data read circuit is in the standby state after the data is output from the output buffer circuit, the power consumption can be reduced.

According to the semiconductor memory device of the third or seventh aspect of the present invention, the data read from the first memory cell array is output from the output buffer circuit via the latch circuit without unnecessary waiting time. The data read operation can be performed faster than in the past. Further, even in the case of designing to expand or reduce the memory capacity with the same circuit configuration, it is not necessary to consider various factors that determine the time required for reading data, so that the optimum circuit design can be facilitated.

According to the semiconductor memory device of the fourth or eighth aspect of the invention, since the data read circuit and the latch circuit are in the standby state after the data is output from the output buffer circuit, the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a timing diagram showing an operation of the semiconductor memory device according to the first exemplary embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a semiconductor memory device according to a second example of the present invention.

FIG. 4 is a timing diagram showing an operation of the semiconductor memory device according to the second exemplary embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a conventional semiconductor memory device.

FIG. 6 is a timing chart showing the operation of the conventional semiconductor memory device.

[Explanation of symbols]

 10 First Memory Cell Array 11 Second Memory Cell Array 12 First Output Control Signal Generating Circuit (First Circuit) 13 Second Output Control Signal Generating Circuit (Second Circuit) 14 Control Circuit 20 First Memory cell array 21 second memory cell array 22 sense amplifier circuit (data read circuit) 23 output control signal generation circuit (control circuit) 51 memory cell array 52, 52A, 52B row decoder 53, 53A, 53B column decoder 54 contact 55 sense amplifier circuit (data read circuit) 56 data latch circuit 57 output buffer circuit 58 precharge signal generation circuit 59 output control generation circuit

Claims (8)

[Claims] 1. A first memory cell array in which a plurality of memory cells for storing one data of "1" or "0" are arranged in a matrix for a desired storage capacity, and the first memory cell array. A row decoder that is connected to each row of the memory cell array and indicates a row in which memory cells to be read data are arranged; and a row decoder that is connected to each column of the first memory cell array to read data A column decoder for designating a column in which memory cells are arranged, and data of memory cells arranged in a row designated by the row decoder and a column designated by the column decoder in the first memory cell array. A semiconductor having a data read circuit for reading and an output buffer circuit for outputting the data read by the data read circuit to the outside. In the body storage device, a plurality of memory cells having the same structure as the memory cells forming the first memory cell array are arranged in two columns, and all the memory cells in the first column store "1". On the other hand, the memory cells in the second column are a circuit equivalent to the second memory cell array storing all “0” and the data reading circuit, and the data reading circuit is the same as the first memory cell array. A first circuit for reading data of one memory cell arranged in a first column of the second memory cell array when reading data of one memory cell; and a circuit equivalent to the data read circuit. , When the data read circuit reads the data of one memory cell of the first memory cell array, the data of one memory cell arranged in the second column of the second memory cell array A second circuit for reading and data read by the first circuit and the second circuit as inputs, the data read by the first circuit becomes "1", and the second circuit And a control circuit for instructing the output buffer circuit to output the data read by the data read circuit to the outside when the data read by the data becomes "0". Semiconductor memory device. 2. The control circuit instructs the output buffer circuit to output the data read by the data read circuit to the outside, and then instructs the data read circuit to enter a standby state. The semiconductor memory device according to claim 1. 3. A first memory cell array in which a plurality of memory cells for storing one data of "1" or "0" are arranged in a matrix for a desired storage capacity, and the first memory cell array. A row decoder that is connected to each row of the memory cell array and indicates a row in which memory cells to be read data are arranged; and a row decoder that is connected to each column of the first memory cell array to read data A column decoder for designating a column in which memory cells are arranged, and data of memory cells arranged in a row designated by the row decoder and a column designated by the column decoder in the first memory cell array. A data read circuit for reading, a latch circuit for holding and outputting the data read by the data read circuit, and the latch circuit In a semiconductor memory device including an output buffer circuit that outputs data output from the outside, a plurality of memory cells having the same structure as the memory cells forming the first memory cell array are arranged in two columns. A second memory cell array in which all the memory cells in the first column store "1" while all the memory cells in the second column store "0" is equivalent to the data read circuit. A circuit for reading the data of one memory cell of the first memory cell array when the data read circuit reads the data of one memory cell arranged in the first column of the second memory cell array. A first circuit for reading and a circuit equivalent to the data reading circuit, wherein when the data reading circuit reads data of one memory cell of the first memory cell array, A second circuit for reading the data of one memory cell arranged in the second column of the two memory cell array; and a second circuit for inputting the data read by the first circuit and the second circuit, When the data read by the first circuit becomes "1" and the data read by the second circuit becomes "0", the data read by the data reading circuit is read by the latch circuit. And a control circuit for instructing the output buffer circuit to output the data output from the latch circuit to the outside. 4. The control circuit, after instructing the output buffer circuit to output the data output from the latch circuit to the outside, instructing the data read circuit and the latch circuit to enter a standby state. The semiconductor memory device according to claim 3, wherein the semiconductor memory device is a semiconductor memory device. 5. A first memory cell array in which a plurality of memory cells for storing one data of "1" or "0" are arranged in a matrix for a desired storage capacity, and the first memory cell array. A row decoder that is connected to each row of the memory cell array and indicates a row in which memory cells to be read data are arranged; and a row decoder that is connected to each column of the first memory cell array to read data A column decoder for designating a column in which memory cells are arranged, and data of memory cells arranged in a row designated by the row decoder and a column designated by the column decoder in the first memory cell array. A semiconductor having a data read circuit for reading and an output buffer circuit for outputting the data read by the data read circuit to the outside. In the body storage device, a plurality of memory cells having the same structure as the memory cells forming the first memory cell array are arranged in one column, and the plurality of memory cells all store the same data. A memory cell array and a circuit equivalent to the data read circuit, wherein when the data read circuit reads data of one memory cell of the first memory cell array, one memory of the second memory cell array The data of the cell is read, and when the read data matches the data stored in the memory cell of the second memory cell array, the data read by the data read circuit is externally output to the output buffer circuit. A semiconductor memory device further comprising a control circuit for instructing to output the data to the semiconductor memory device. 6. The control circuit instructs the output buffer circuit to output the data read by the data reading circuit to the outside, and then instructs the data reading circuit to enter a standby state. The semiconductor memory device according to claim 5. 7. A first memory cell array in which a plurality of memory cells for storing one data of "1" or "0" are arranged in a matrix for a desired storage capacity, and the first memory cell array. A row decoder that is connected to each row of the memory cell array and indicates a row in which memory cells to be read data are arranged; and a row decoder that is connected to each column of the first memory cell array to read data A column decoder for designating a column in which memory cells are arranged, and data of memory cells arranged in a row designated by the row decoder and a column designated by the column decoder in the first memory cell array. A data read circuit for reading, a latch circuit for holding and outputting the data read by the data read circuit, and the latch circuit In a semiconductor memory device having an output buffer circuit for outputting data output from the outside, a plurality of memory cells having the same structure as the memory cells forming the first memory cell array are arranged in one column, The plurality of memory cells are a second memory cell array that stores the same data, and a circuit equivalent to the data read circuit, wherein the data read circuit is one memory cell of the first memory cell array. The data in the memory cell of the second memory cell array is read, and when the read data matches the data stored in the memory cell of the second memory cell array, the latch A circuit to hold and output the data read by the data read circuit, and The semiconductor memory device characterized by further comprising a control circuit for instructing to output the data output from the latch circuit to the outside. 8. The control circuit, after instructing the output buffer circuit to output the data output from the latch circuit to the outside, instructs the data read circuit and the latch circuit to enter a standby state. The semiconductor memory device according to claim 7, wherein the semiconductor memory device is a semiconductor memory device.