JPH09224194A - Photographing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate image data for real-time monitor and image data for recording through a circuit system, for which no field memory is used, and to simplify configuration by adopting a photoelectric transducing means for attaining frame reading without requiring any mechanical shutter. SOLUTION: The image of light beam made incident through a lens system 2 is formed onto a CCD solid-state imaging device (CCD) 4 as a photoelectric transducing element. When performing monitor display at this device, the photoelectric transducing means (CCD 4) is let execute the image data output operations of two systems and a photographed image processing means is let execute the generating operation of monitor image data corresponding to the image data inputs of two systems. Besides, when executing a recording operation, the photoelectric transducing means is let execute the image data output operation of one system and the photographed image processing means is let execute the generating operation of recording image data corresponding to the image data input of one system. Namely, at the time of photographing, image data are line-sequentially read out of the photoelectric transducing means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photographing apparatus capable of capturing image data by a photoelectric conversion element and recording the image data on a recording medium as photographed image data, such as a digital still camera.

[0002]

2. Description of the Related Art A so-called electronic camera (digital still camera) using a CCD two-dimensional solid-state image pickup device is known. In such an electronic camera, image data of a still image captured by a CCD solid-state image pickup device is stored as recording image data in a recording medium such as a memory card, a magnetic disk, or a magneto-optical disk, so that a film like a normal camera can be obtained. Is unnecessary.

For example, at the time of shooting, a scene on the subject side captured by a CCD solid-state image pickup device is reproduced and output to a viewfinder. When the user confirms the image from the viewfinder and performs a shooting operation, the image data captured at that time is recorded in the recording medium as a captured image. Photographed image data taken in a recording medium can be reproduced and output to a viewfinder, or can be output to an external television monitor device or computer device to be displayed like a photographed photograph.

[0004]

In the conventional digital still camera, an interline transfer type (IT type) CCD solid-state image pickup element is often used as a photoelectric conversion element. FIG. 9 shows the configuration of an IT type CCD solid-state image sensor. As shown in FIG. 9, the CCD solid-state image sensor 120A includes a plurality of sensor units 121 arranged in a matrix in the vertical direction and the horizontal direction to store signal charges according to the amount of incident light, and the vertical direction of these sensor units 121. A plurality of vertical transfer registers 1 arranged in columns and vertically transferring the signal charges read from each sensor unit 121.
An image pickup area 123, which is an image portion, is formed by 22 and.

The signal charge accumulated in the sensor section 121 is
The charge transfer pulse XSG is applied from the drive circuit 130 to the read gate (not shown), whereby the vertical transfer register 1
22. Each vertical transfer register 122 is transfer-driven by the vertical transfer clock ΦV.

Below the image pickup area 123 in the drawing, a horizontal transfer register 124 is arranged in which signal charges corresponding to one scanning line are sequentially transferred from a plurality of vertical transfer registers 122. The horizontal transfer register 124 is transfer-driven by the horizontal transfer clock ΦH. Horizontal transfer register 1
A charge detection unit 125 is arranged at the end of 24, and the signal charges horizontally transferred are sequentially converted into electric signals by the charge detection unit 125. And it is amplified by the output amplifier 126,
It is derived from the terminal 127 as a CCD output according to the amount of light from the subject. In such an IT type CCD solid-state image sensor 120A, either field reading using an electronic shutter or frame reading using a mechanical shutter can be adopted.

As shown on the right side of the image pickup area 123 in the drawing, each line is referred to as O1, E1, O2, E2 ... For convenience. “O *” indicates an odd line, and “E *” indicates an even line. For field reading, each sensor unit 12
The charge is read from 1 to the vertical transfer register in units of fields, and the image data for one line is generated by the sum of the odd line and the even line. That is, in the odd field period of 1/30 second, (O1 + E1), (O2 + E)
2), (O3 + E3) ..., (E1 + O2), (E2 + O3), (E3 in the odd field period of 1/30 seconds
+ O4) ..., and the image data is output.

On the other hand, in the case of frame reading, charges from each sensor unit are read out to the vertical transfer register once per frame. That is, in the odd field period, O1, O
2, O3 ... Image data of only odd lines are output, and E1, E are generated in the odd field period.
2, E3 ..., Image data of only even lines are output.

In a digital still camera, in order to effectively make use of a limited number of CCD pixels, frame reading which can increase vertical resolution is often adopted.
However, it is known that a general IT type CCD solid-state imaging device cannot capture a moving object unless a mechanical shutter is mounted. That is, FIG.
As shown by 0, the light is shielded by the mechanical shutter as shown by the shaded portion every 1/60 second period. The period not exposed to light is the exposure period. Then, the odd-numbered line sensor portion 121 is read at the timing T _OD , and the even-numbered line sensor portion 121 is read at the timing T _EV . By doing so, the image data exposed in the sensor units of the odd line and the even line in the same period can be obtained.
However, the mounting of the mechanical shutter causes a problem regarding its durability and complicates the mechanism.

Therefore, in recent years, a CCD solid-state image sensor capable of full-frame reading without a mechanical shutter has been developed. This is PS-CCD (Progressive Scan CCD)
The image sensor is called an all-pixel readout type CCD) and is configured as shown in FIG. 11, for example.

That is, this PS-CCD solid state image pickup device 120
B has sensor units 121 arranged in a matrix in the vertical and horizontal directions and an imaging region 123 is formed in substantially the same manner as the CCD solid-state imaging device 120A of FIG. 9, but includes two systems of horizontal transfer registers 124a and 124b. . Along with this, the charge detectors 125a and 125b, the output amplifiers 126a and 126b, and the terminals 127a and 127b are arranged.

In this case, odd lines (O1, O2 ...
,) And the signal charges of the even lines (E1, E2, ...) Separately from the horizontal transfer registers 124a, 1a.
The horizontal transfer is simultaneously performed by 24b so that the signal charges for one frame are read out within 1H (H is a horizontal scanning period) which is 1/60 second as two-channel output. With such a method, it is possible to read out the information of all the pixels forming one frame for each exposure cycle.

However, when such a PS-CCD solid-state image pickup device 120B is adopted in a digital still camera, two signal memories are required in the signal processing system, which causes a problem that the circuit type becomes complicated and the cost increases. Occur. In the digital still camera, the image data taken in from the CCD solid-state image pickup device must be used as image data for real-time monitoring by the viewfinder and at the time of shooting as image data for recording. For a real-time monitor using a viewfinder, a so-called interlaced image signal may be supplied to the viewfinder. In this case, an interlaced image signal that forms a field image from odd line image data and even line image data that are obtained simultaneously on two channels. However, since the recorded image data is a non-interlaced signal, a field memory is required. In other words, the non-interlaced image data cannot be generated unless the odd line image data and the even line image data supplied at the same time are temporarily stored in the field memory and the data is read line by line from the field memory. is there.

[0014]

In view of such problems, the present invention adopts a photoelectric conversion means capable of frame reading without the need for a mechanical shutter in an image pickup apparatus to improve durability. And simplification of the mechanism, and simplification of the circuit configuration and cost reduction by making it possible to generate image data for real-time monitoring and image data for recording with a circuit system that does not use field memory. With the goal.

Therefore, the photoelectric conversion means is
An operation capable of switching between an operation of reading out image data for one frame in two periods by output of two systems and an operation of reading out exposed image data for one frame in two periods by output of one system is used. When the monitor means displays the monitor, the photoelectric conversion means 2
System image data output operation, the photographed image processing means performs monitor image data generation operation in response to two-system image data input, and the recording means performs recording operation, photoelectric conversion is performed. The conversion means is caused to execute the image data output operation of one system, and the captured image processing means is
A control means is provided for performing control so as to execute a recording image data generation operation in response to image data input from the system.
That is, by reading the image data line-sequentially from the photoelectric conversion means at the time of shooting, it is possible to generate non-interlaced image data without using a field memory.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital still camera as an embodiment of a photographing apparatus of the present invention will be described below in the following order. 1. Appearance of digital still camera 2. Digital still camera circuit configuration 3. 4. Configuration of DSP 4.1 Operation during 1-channel output and 2-channel output 5. Operation during shooting

1. Appearance of Digital Still Camera FIGS. 1A to 1F show a front view, a right side view, a plan view, a left side view, a bottom view and a rear view as appearances of the digital still camera. FIG. 1A is a front view directed to the subject side, in which the lens block 1 is arranged, and light rays on the subject side can be taken in. Further, a strobe light emitting section is provided as the strobe unit 36.

The right side of the digital still camera is shown in FIG.
The main switch 33 is arranged as shown in FIG.
The main switch 33 is a slide type operator,
Power off (OFF) and power save as operating positions
(PS) and three positions of power on (ON) are prepared, and the user selects three modes for power operation. That is, the power may be turned off when not in use, and may be turned on or off when used. Power-on is a mode in which the entire internal shooting and recording / playback circuit system is powered on. Further, although detailed description is omitted, power-saving is powering off unnecessary parts as needed. , It is a power mode that can be used while reducing power consumption.

The upper surface of the housing of the digital still camera is shown in FIG.
As shown in (c), the release switch 34 and the zoom operation section 37 are provided. The release switch 34 is a so-called shutter switch, and by pressing the release switch 34, the scene on the subject side is photographed. The zoom operation unit 37 is an operator for manually adjusting the zoom state to the wide side / tele side.

As shown in FIG. 1F, on the rear side of the digital still camera, that is, the side facing the user, the electronic viewfinder 44, the LCD unit 71, the mode / playback operation key 72, and the PC card driver 66 are provided. Is provided. A PC card is used as a recording medium in this digital still camera, and captured image data is recorded in the PC card loaded in the PC card driver 66.

On the electronic viewfinder 44, a scene on the subject side taken from the lens block 1 on the front side of the housing and a reproduced image recorded on a PC card are displayed. The LCD display unit 71 displays various operating states, shooting mode states, remaining battery level, and the like. The shooting mode referred to here is a mode of operation functions in shooting and playback operations, such as auto focus on / off, strobe on / off, single shot image playback, and continuous shot image playback. As the mode / reproduction operation key 72, various keys for performing a selection operation of these modes and a reproduction operation are prepared.

The normal use form of the user is as follows. At the time of shooting, the user first sets the main switch 33 to the power save mode or the power on mode as a power operation. The electronic viewfinder 44 is used to search for a subject to be photographed while checking the scene on the subject side, and the release switch 34 is pressed to take a photograph. That is, the scene obtained from the lens block 1 at the timing when the release switch 34 is pressed is processed as photographed image data and recorded in the PC card. By performing a reproduction operation from the mode / reproduction operation key 72 after photographing, the photographed image data recorded in the PC card is read out, converted into a television image signal form by a predetermined process, and reproduced and outputted to the electronic viewfinder 44. To be done.

2. Circuit Configuration of Digital Still Camera FIG. 2 is a block diagram showing the configuration of an image signal processing circuit system of the digital still camera. For the sake of explanation, the portions surrounded by the alternate long and short dash line are called the lens block 1, the photographing circuit block 10, the camera control block 30, the EVF (electronic viewfinder) block 40, the memory block 50, the image processing control block 60, and the LCD block 70, respectively. I will.

As the lens block 1, for example, a lens system 2 in which a 12 × zoom lens is arranged, and a lens driver 3 for performing focus drive, zoom drive and iris adjustment drive in the lens system 2 are provided.

A light beam incident through the lens system 2 is a CCD solid-state image pickup device 4 (hereinafter, simply CC
Image (referred to as D). CCD4 is so-called PS-C
It is a CD (Progressive Scan CCD Image Sensor; CCD for all-pixel reading method). That is, as described with reference to FIG. 11, photoelectric conversion elements are arranged in a matrix in the vertical and horizontal directions in the CCD 4 to form a two-dimensional image pickup area, and for example, two horizontal transfer registers are provided to provide a vertical odd number. The signal charges of the lines and the signal charges of the even-numbered vertical lines are simultaneously horizontally transferred by different horizontal transfer registers to read the signal charges for one frame within 1H (H is a horizontal scanning period). Yes (2-channel reading method). With this method,
Information of all pixels can be read out every exposure cycle of 1/60 second. Further, the CCD 4 can output the image information by the 1-channel reading method in addition to the 2-channel reading method. The 1-channel reading method is a method in which one of the horizontal transfer registers is used to sequentially read one line at a time. In this case, one frame is formed in a period of 1/30 second, which is twice as long as that of the 2-channel reading method. It is possible to read out the information of all the pixels forming the.

The driving of the CCD 4 and the processing of the read signal are performed by a circuit system as the photographing circuit block 10. That is, the timing generator 16 supplies the reference timing for driving the CCD 4 to the vertical / horizontal driver 13 and the pilot signal generator 14. The pilot signal generator 14 outputs the pilot signal, and the vertical / horizontal driver 13 outputs the vertical scanning signal and the horizontal scanning signal to the CCD 4 based on the reference timing to execute the image pickup operation of the CCD 4. Further, switching between 1-channel reading and 2-channel reading is also performed by setting control of vertical scanning signal and horizontal scanning signal.

When the 2-channel reading method is executed, C
The 2-channel image data output from the CD 4 is supplied to the sample hold / AGC circuits 11A and 11B, respectively. Sample hold / AGC circuit 11A, 1
In 1B, first, CDS (Correlated Double Sampling)
A sample / hold operation called is performed. Since the precharge level (black level) and the data level (signal level) are alternately output as the output of the CCD 4, the precharge level and the data level are sampled separately and the difference between them is taken. Then, the normal video signal state is set. After this CDS processing is performed, the gains are matched between the two channels, and the level is adjusted to an appropriate level with respect to the dynamic range of the A / D converters 12A and 12B in the subsequent stage, and the A / D
It is output to the converters 12A and 12B. The gain values in the sample hold / AGC circuits 11A and 11B are adjusted under the control of the gain control unit 15. A / D converter 1
2A and 12B convert the signal of each channel into, for example, 10-bit digital data, and use DSP (Digital Signal P
supply to the rocessor) 18.

When the 1-channel reading method is executed, the 1-channel image data output from the CCD 4 is sampled / holded / AGC circuits 11A, A / A.
It is processed by the D converter 12A and supplied to the DSP 18.

The DSP 18 performs correction processing, white balance adjustment, gamma correction and the like on digital image data input in two channels or one channel, and extracts R / G / B signals by color matrix processing. Then, Y signal generation and various Y signal processing, chroma signal generation and various color signal processing are performed from the R / G / B signal to obtain a luminance signal Y and color difference signals Cr (= RY), C.
It is supplied to the EVF block 40 and the memory block 50 in the form of b (= BY). Luminance signal Y, color difference signal C
The ratio of the data amounts of r and Cb is set to 4: 2: 2.
The timing reference of the processing in the DSP 18 is given from the timing generation section 16, so that the processing is performed in a state synchronized with the output from the CCD 4.

The signal generator 19 is a so-called sync signal generator. Since the luminance signal Y and the color difference signals Cr and Cb are used as television signals, the signal generator 1 is adapted to these image signal outputs.
The vertical synchronizing signal VD and the horizontal synchronizing signal HD are generated at 9,
It is supplied to the memory block 50. Although the signal generator 19 and the DSP 18 are shown separately in the drawing,
Actually, the signal generator 19 can be configured as a circuit system inside the DSP 18.

The memory block 50 is provided with a memory controller 51, D-RAMs 53 and 54, a signal generator 52, and a compression / expansion circuit 55. The memory controller 51 writes the luminance signal Y supplied from the DSP 18 into the D-RAM 53, and also writes the color difference signals Cr and Cb into the D-RAM 54. D-RAM 53, 54
Instead of this, an S-RAM or other semiconductor memory may be used.

Further, the signal generator 52 is a synchronizing signal generating section similar to the signal generator 19 described above. However, in this signal generator 52, D
When the vertical synchronizing signal VD and the horizontal synchronizing signal HD are supplied from the SP 18, the internal PLL circuit synchronizes and then the vertical synchronizing signal VD and the horizontal synchronizing signal HD are generated. Therefore, when the photographing circuit block 10 is in the operating state, that is, the operation of the memory block 50 at the time of photographing is performed in synchronization with the operation of the photographing circuit block 10. The vertical synchronizing signal VD and the horizontal synchronizing signal HD from the signal generator 52 are also supplied to the EVF block 40. If necessary while the signal generator 19 is not operating, the memory block 50 or EVF
The vertical synchronizing signal VD and the horizontal synchronizing signal HD from the signal generator 52 are used as they are for the processing in the block 40.

Although the signal generator 52 and the memory controller 51 are shown separately in the drawing, the signal generator 52 can actually be configured as a circuit system inside the memory controller 51.

The compression / expansion circuit 55 includes a D-RAM 53,
For the image data stored in 54, for example, JPEG
The method (Joint Photographic Experts Group) is used to perform compression processing, and vice versa, the operation of expanding compressed image data to original data is performed.

As the EVF block 40, a character generator 41, a D / A converter 42, a video encoder 43 and an electronic viewfinder 44 are provided. The D / A converter 42 supplies the luminance signal Y and the color difference signals Cr and Cb supplied from the DSP 81, or the luminance signal Y and the color difference signal Cr which are read and supplied from the D-RAMs 53 and 54 by the memory controller 51. RGB encoding processing and digital / analog conversion processing are performed on Cb, and an RGB image signal as an analog signal is output to the video encoder 43. When a character image is generated by the character generator 41, the character image signal is superimposed on the image signal and output.

The RG input in the video encoder 43
The B image signal is encoded for display on the electronic viewfinder 44, and the interlace system electronic viewfinder 44 is driven for display. In this EVF block, the signal generator 52
The vertical synchronizing signal VD and the horizontal synchronizing signal HD are supplied from the above, and the vertical synchronizing signal VD and the horizontal synchronizing signal HD are synchronized with those of the photographing circuit block 10 at the time of photographing operation. Image, that is, the image captured by the CCD 4 from the subject side can be displayed.

The camera control block 30 includes a camera controller 31 and an E by a microcomputer.
An EP-ROM 32 is provided. Camera controller 3
Reference numeral 1 controls mainly the photographing operation in the circuit system of FIG. Further, various constants and set values for the control operation are stored in the EEP-ROM 32.

The camera controller 31 monitors the operation position (power off / power save / power on) of the main switch 33, the operation of the release switch 34, and the operation of the zoom operation section 37 shown in FIG. Then, required control is performed according to these operations. Further, the reset circuit 35 is configured to be reset.

The control by the camera controller 31 is performed via the control bus B1. For example, the zoom operation unit 37
In response to the operation of or the setting of the autofocus mode, the lens driver 3 is instructed to perform an operation such as lens movement in the lens system 2. Further, the timing control unit 16 is instructed to generate timing serving as a reference at the time of photographing, and the D / A converter 17 is further used to notify the gain control unit 15 of the sample hold / AGC circuits 11A and 11B.
Gives the gain value to be set in. In addition, it controls various processes in the DSP 18 via the bus buffer 20. Furthermore, for the character generator 41,
The electronic viewfinder 44 gives an instruction to generate a character to be displayed. Further, when the strobe light emission mode is set, the strobe unit 36 is driven in synchronization with the operation of the release switch 34.

In addition to these controls, as described above, C
The timing generation unit 16 is instructed to switch between the 1-channel read mode and the 2-channel read mode for the reading method from the CD 4. Further, the processing in the DSP 18 is slightly different between the 1-channel read mode and the 2-channel read mode, and therefore, the operation mode of the DSP 18 is instructed via the timing generation section 16.

The image processing control block 60 includes an image processing controller 61, a RAM 62, and an EEP-.
A ROM 63 is provided. Image processing controller 6
Reference numeral 1 mainly controls the recording / reproducing operation in the circuit system of FIG. Further, various constants and set values for the control operation are held in the EEP-ROM 63. R
The AM 62 is a work area used for image processing.

The image processing controller 61 includes a RAM 62, an EEP-ROM 63, and a control / data bus B2.
Control signals and image data are exchanged with the memory block 50, the EVF block 40, the interface section 64, and the PC card driver 66. For example, in accordance with a control signal transmitted to each section via the control / data bus B2, the image data held in the D-RAMs 53 and 54 in the memory block 50 is compressed by the compression / expansion circuit 55, and the compressed image data is recorded in the RAM 62 in a recording format. Then, a header, an index image and the like required as the above are added as recording data and supplied to the PC card driver 66. At this time, by instructing the PC card driver 66 to perform a recording operation, the captured image data is recorded in the PC card.

Further, by instructing the PC card driver 66 to perform the PC card reproducing operation, the recorded image data can be read. And compression / expansion circuit 5
5, and then the memory controller 51 expands the D-R
The photographed image can be displayed on the electronic viewfinder 44 by writing the image data in the AM 53 and 54 and supplying the image data to the EVF block 40. Further, the image processing controller 61 can perform mute control of the display output operation in the electronic viewfinder 44 for the EVF block 40.

The interface section 64 is provided for transmitting photographed image data to an external computer or monitor device, and the connector 65 is connected to the external device. When transmitting captured image data to an external device, the image processing controller 61 is a PC.
The card driver 66 is instructed to perform the PC card reproduction operation, and the recorded captured image data is read. And compression /
After decompression by the decompression circuit 55, the memory controller 51 causes the D-RAMs 53 and 54 to write the image data, and further supplies the image data to the interface unit 64 and transfers the image data to an external device.

As the LCD block 70, the LCD unit 71 and the mode / reproduction key 72 shown in FIG. 1 (f) are provided. The image processing controller 61 monitors the operation of the mode / playback key 72, and makes various mode settings as described above in accordance with the operation. Further, the image processing controller 61 supplies display data to the LCD unit 71 to execute a display operation.

The image processing controller 61 and the camera controller 31 can communicate with each other via a communication bus BT, and are configured to mutually perform operation requests and various status confirmations.

The clock unit 67 is always operated by a dedicated battery and serves as a unit for counting the current date and time. The date and time information is supplied to the image processing controller 61, and the image processing controller 61 can display the date and time information on the LCD unit 71 and can add it as date and time data to the captured image data.

In the digital still camera of this example configured as described above, the basic operations are roughly classified into a shooting operation and a reproduction operation. The reproducing operation includes an operation of displaying an image recorded in the PC card on the electronic viewfinder 44 and an operation of transferring the image data reproduced from the PC card through the interface section.

During the photographing operation, the user searches for the photographing object while confirming the image captured by the operation of the lens block 1, the CCD 4 and the photographing circuit block 10 with the electronic viewfinder 44. And the release switch 34
When is pressed, the image data output from the photographing circuit block 10 at that timing is supplied to the image processing control block 60 via the processing of the memory block 50, and this is recorded in the PC card by the PC card driver 66.

When the user wants to view the image data recorded on the PC card with the electronic viewfinder 44, the user operates the mode / playback key 72 to perform a reproduction operation. Then, under the control of the image processing controller 61, as described above, P
The C card driver 66 executes the PC card playback operation,
The reproduced data is expanded by the compression / expansion circuit 55, supplied to the EVF block via the memory controller 51, and displayed on the electronic viewfinder 44.

When the image data recorded in the PC card is transferred to the external device, the operation control of the image processing controller 61 is performed by an operation from the external device side, and the PC card driver 66 reproduces it as described above. The memory block 50 performs processing such as decompression on the obtained image data, and transfers and outputs the image data from the interface unit 64.

3. Configuration of DSP The internal configuration of the DSP 18 is shown in FIGS. The 2-channel image data supplied from the A / D converters 12A and 12B is input to the DSP 18 from the terminals 81a and 81b of FIG. 3 and supplied to the digital clamp circuits 82a and 82b. The image data clamped by the digital clamp circuits 82a and 82b is subjected to defective pixel detection and correction processing by the defective pixel correction unit 83, and then white balance processing is performed by the white balance unit 84 at the next stage.

Next, gamma processing units 85a and 85b perform gamma correction processing, and offset addition units 86a and 86b add an offset value OFS. And the clip part 8
After being clipped by 7a and 87b, it is input to the line memory unit 88. The line memory unit 88 is configured as shown in FIG. That is, the line memory 101 for 1H,
102, 103, 104 are provided, and the write / read operation of the line memories 101, 102, 103, 104 is controlled by the line memory control unit 106.

The switch 105 has a T1 terminal connected when reading one channel and a T2 terminal connected when reading two channels. Further, the switch 107 is composed of a switch element unit of 6 units, and the TU terminal is connected during the 2-channel reading, but the TU terminal and the TL terminal are alternately connected every 1H period during the 1-channel reading.

The operation of the line memory unit 88 will be described later, but the clipping unit 87 is used when reading two channels.
Image data input to channels Ch1 and Ch2 from a and 87b. Line memories 101, 102, 103,
By outputting through 104, the image data for 6 lines is output as image data L0 to L5. When reading one channel, channel C from the clip portion 87a
Input of h1 image data Line memories 101, 1
Image data for 5 lines is output as image data L0 to L5 by being output via 02, 103, and 104. In this case, the image data L4 and L5 are image data of the same line.

Image data L0 from the line memory unit 88
3 to L5 are supplied to the color process unit 90 and the aperture generator 89 shown in FIG. Color process unit 90
Is RGB from 6 or 5 lines of image data
Decoding processing is performed, and R / G / B image signals are output to the YC matrix section 91. YC matrix section 91
Performs a so-called Y / C decoding process to obtain a luminance signal Y,
The color difference signals Cb (= BY) and Cr (= RY) are output.

The luminance signal Y is supplied to the adder 98. On the other hand, the aperture generator 89 generates an aperture component, which is sliced by the slicing unit 95, compressed by the compressing unit 96, negatively gained by the negative gain unit 97, and added by the adding unit 98.
Is supplied to. An aperture component is added to the luminance signal Y in the addition unit 98, and then a so-called knee process is performed in the knee correction unit 99, that is, the high luminance portion is compressed without slicing so that the high luminance portion is maintained in a state where the gradation is maintained. Is performed and is clipped by the clipping unit 100, and is supplied from the terminal 101a to the memory block 50 and the EVF block 40 as the luminance signal Y output of the DSP 18.

The color difference signals Cb and Cr are supplied to the chroma suppressor 9
After the color erasing processing is performed on the high-luminance portion and the low-luminance portion at 2 and 93, respectively, the black balance processing is performed at the block balancing portion 94, and the black balance processing is supplied to the clip portion 100. After being clipped by the clip unit 100,
The color difference signals Cb and Cr of the DSP 18 are supplied to the memory block 50 and the EVF block 40 from the terminal 101b.

4. Operation at the time of 1-channel output and 2-channel output In the case of this example, as will be described later in detail, when the user is monitoring the image on the subject side with the electronic viewfinder 44 in the photographing operation, the CCD 4 and DSP18
Performs the operation in the 2-channel reading mode, and when the release switch 34 is pressed to take a picture, C
The CD 4 and the DSP 18 will operate in the 1-channel read mode. Here, operations in the 1-channel read mode and the 2-channel read mode will be described.

The CCD 4 has a PS as shown in FIG.
Although it is a CCD solid-state image sensor, its pixel array (corresponding to each sensor section 121 in FIG. 11) is as shown in FIG. That is, in the first line, the third line, the fifth line, ... Odd lines O1, O2, O3, ..., G pixels, R pixels, G pixels, R pixels, ...・ Even lines E1, E2, such as the second line, the fourth line, the sixth line ...
In E3 ..., B pixel, G pixel, and
B pixels, G pixels, ... Are arranged.

In the 2-channel read mode, the two horizontal transfer registers (horizontal transfer registers 124a and 124b in FIG. 11) perform the odd line transfer and the even line transfer, respectively. As shown in b), odd-numbered lines O1, O
, O3 ... are sequentially output, and at the same time, even-numbered lines E1, E2, E3 are output as channel Ch2 output.
... are sequentially output.

The image data thus read out on the two channels is sampled / holded / AGC circuit 11 as described above.
DS via A, 11B and A / D converters 12A, 12B
Input to P18. Then, the DSP 18 processes the input of the two channels as shown in FIG. 3, but in this case, the line memory unit 88 shown in FIG.
The operation shown in FIG. 6 is performed in order to obtain image data L0 to L5 for 6 lines from image data input of 2 channels simultaneously with lines.

In the 2-channel read mode, the switch 105 is fixed to the T2 terminal and the switch 107 is fixed to the TL terminal in the line memory unit 88 of FIG. FIG. 6A shows the image data input as the channels Ch1 and Ch2 in line units. FIG.
(B) to (e) are writing / writing of the line memories 101 to 104.
The read operation is shown, and FIG. 6F shows the control signal of the switch 107.

At the timing when, for example, the odd line O3 and the even line E3 are input as the channels Ch1 and Ch2, the odd line O3 is written in the line memory 101 and the even line E3 is written in the line memory 103. Also,
During this period, the odd line O2 input 1H before is read from the line memory 101, and this is written in the line memory 102, and at the same time, the line memory 10 is read.
An even-numbered line E2 input 1H before is read from 3, and this is written in the line memory 104.
Further, in this period, the line memories 102 and 104
Further, the odd line O1 and the even line E1 which are input 1H before are read out.

Since the switch 107 is connected to the TL terminal, the output of the line memory 102 is the image data L0,
The output of the line memory 104 is the image data L1.
The output of the line memory 101 is the image data L2, and the output of the line memory 103 is the image data L3. Further, the input of the channel Ch1 becomes the image data L4, and the input of the channel Ch2 becomes the image data L5. Therefore, FIG.
In the period shown as, the image data L0 to L5 is set to O
The image data of each line of 1, E1, O2, E2, O3, E3 is output. Such an operation is continued, and O2, E2, and
The image data of each line of O3, E3, O4, and E4 is O as image data L0 to L5 during the period
Image data of each line of 3, E3, O4, E4, O5 and E5 is output.

In the color process unit 90 and the aperture generator 89, a predetermined decoding process is carried out from the image data thus inputted every 6 lines. Then, the luminance signal Y and the color difference signals Cb and Cr as the interlaced image data are obtained corresponding to the operation in the EVF block 40.

In the 1-channel read mode, one of the two horizontal transfer registers (see FIG. 1).
The horizontal transfer register 124a) of 1 is used to sequentially transfer the odd line and the even line, that is, as shown in FIG. 5C, the odd line O1, the even line E1, the odd line as the output of the channel Ch1. O2, even lines E2 ... Image data are sequentially output.

The image data thus read by one channel is input to the DSP 18 via the sample hold / AGC circuit 11A and the A / D converter 12A. And D
In SP18, various processes are performed on the input image data from the terminal 81a in FIG. 3, but in this case, the line memory unit 88 shown in FIG. L4, L5 (= L
4), the operation shown in FIG. 7 is performed.

In the 1-channel read mode, the switch 105 is fixed to the T1 terminal in the line memory section 88 of FIG. The switch 107 is switched to the TU terminal or the TL terminal every 1H period by the control signal shown in FIG. FIG. 7A shows the image data input as the channel Ch1 on a line-by-line basis.
(B) to (e) are writing / writing of the line memories 101 to 104.
The read operation is shown.

By the write operation control of the line memory control unit 106, the line memories 101 and 102 and the line memories 103 and 104 are alternately written every 1H period.

At the timing when, for example, the odd line O7 is input as the channel Ch1, the line memory 10
The writing operation of 1 and 102 is performed, and the odd line O7 is written in the line memory 101. Further, during this period, the odd line O6 input 2H before is read from the line memory 101, and this is written in the line memory 102. From the line memory 102, the odd line O5 input 4H before is read.

On the other hand, during this period the line memories 103, 10
No. 4 does not perform the write operation, the even line E6 input from the line memory 103 1H before the odd line O7 and written in the line memory 103 is read, and the line memory 104 reads the odd line E6. Even line E input 3H before O7 and written 1H before
5 has been read.

During this period, the control signal of FIG.
The switch 107 is connected to the TL terminal. Therefore,
The output of the line memory 102 is the image data L0, and the output of the line memory 104 is the image data L1. The output of the line memory 101 is the image data L2, and the output of the line memory 103 is the image data L3. Further, the input of the channel Ch1 becomes the image data L4 and L5.
Therefore, during the period shown in FIG. 7, the image data L0 to L5
As O5, E5, O6, E6, O7, (O7) 5
Image data for a line is output.

In the period shown as the following, that is, in the period when the odd line E7 is input, the line memories 101 and 102 do not perform the write operation, but the line memories 103 and 104 perform the write operation. Therefore, the even line E7 is written in the line memory 103, and the even line E6 read from the line memory 103 is read in the line memory 104.
Is written to. The read output from the line memory 101 is an odd line 07, the read output from the line memory 102 is an odd line 06, the read output from the line memory 103 is an even line E6, and the read output from the line memory 104 is an even line E5. Become.

During this period, the switch 107 is connected to the TU terminal by the control signal of FIG. 7 (f). Therefore, the output of the line memory 104 is the image data L0, and the output of the line memory 102 is the image data L1. The output of the line memory 103 is image data L2, and the output of the line memory 101 is image data L3. further,
The input of the channel Ch1 becomes the image data L4 and L5. Therefore, during the period shown in FIG.
As L5, E5, O6, E6, O7, E7, (E7)
5 lines of image data are output.

In the period shown as the next period, the same operation as that in the period is performed, and the image data L0 to L5 are O6, E6, and
The image data of each line of O7, E7, O8, (O8) is output.

In the color processing section 90 and the aperture generator 89, the predetermined decoding processing is carried out from the image data thus inputted every five lines. In this case, the luminance signal Y as non-interlaced image data corresponding to the recording operation on the PC card,
Although it is necessary to obtain the color difference signals Cb and Cr, since the lines are alternately supplied to the color process unit 90 and the aperture generator 89 in a non-interlaced state, a non-interlaced image is used without using a field memory or the like. It is possible to obtain the luminance signal Y and the color difference signals Cb and Cr as data.

5. As described above, the CCD 4 and the DSP 18 are capable of switching the operation corresponding to the 1-channel reading / 2-channel reading. The switching control operation of the 1-channel reading / 2-channel reading during the photographing operation will be described below. This will be described with reference to FIG.

In this example, when the user is monitoring the image on the subject side with the electronic viewfinder 44 in the photographing operation, the CCD 4 and the DSP 18 operate in the 2-channel read mode, and the release switch 34 is pressed. When photographing is performed, the CCD 4 and the DSP 18 operate in the 1-channel read mode.

FIG. 8A shows a vertical synchronizing pulse which is a reference for operation processing at the time of photographing. For the sake of explanation, the processing period defined by each vertical synchronizing pulse will be referred to as V1 to V6. Before the period V1 (not shown), the user is monitoring the image on the subject side with the electronic viewfinder 44, and at this time, the operation is in the 2-channel reading mode. Therefore, the vertical synchronization period is 1/60
Seconds, image data is read from the CCD 4 and image data generation processing (Y / C generation processing) is performed by the DSP 18 in units of the vertical synchronization period. Then, the generated luminance signal Y and color difference signals Cb, Cr are supplied to the EVF block 40, and monitor output is executed by the electronic viewfinder 44.

FIG. 8E shows the exposure operation of the CCD 4.
Channels Ch1 in the CCD 4 are shown in FIGS.
Output and channel Ch2 output are schematically shown, but in the 2-channel read mode, image data (for example, P1) due to charges when exposed in a period of 1/60 second before is an odd number for each channel. Line data (P1 _OD ) and each even line data (P1 _EV ) are 1/60
It will be output in the period in seconds.

It is assumed that the user operates the release switch 34 at some point within the V1 period. When the camera controller 31 detects that the release switch 34 has been operated by the release pulse as shown in FIG. 8B, the camera controller 31 enters the control of the recording operation of the captured image.

First, as shown in FIG. 8C, in the V2 period which is the next control period in which the release pulse is detected, a signal for instructing switching to the 1-channel read mode is output to the timing generation unit 16. . In response to this, the timing generator 16 switches the operation of the CCD 4 to the 1-channel read mode. Therefore, the vertical synchronizing pulse has a period of 1/30 second from the next V3 period, which causes the CCD
In No. 4, the exposure is performed in the period of 1/30 second as shown in FIG. 8E, and the charge exposed in the next period of 1/30 second is read as image data in the 1-channel read mode described above. Switch. That is, as shown in FIGS. 8F and 8G, the image data of the odd line and the even line are read only in the channel Ch1.

Further, the timing generator 16 receives the instruction for the 1-channel reading mode, and then V is the next processing period.
During the three periods, as shown in FIG. 8D, the DSP 18 outputs a signal instructing switching to the 1-channel read mode. By such processing, considering the processing time for switching to the read mode, etc., it can be considered that the stable one-channel read mode can be executed from the V4 period.

Therefore, one frame of image data P4 (= all odd lines P4 _OD and all even lines P4 _EV ) which is exposed in the V4 period and is output from the CCD 4 in the next V5 period is used as the photographed image data. To do. In this case, the odd line and the even line in the image data P4 for one frame are alternately input to the DSP 18,
Therefore, by generating the Y signal / Cb, Cr signal in the operation in the above-described 1-channel read mode, it is possible to generate non-interlaced image data without interposing a field memory or the like.

When the image data processing in the V5 period is completed, the processing of the captured image, that is, the image data to be recorded in the PC card is completed. That is, after the non-interlaced image data is supplied to the memory block 50 to enable the recording operation process, the CCD4 to DSP1
Up to 8 may be returned to the 2-channel read mode. Therefore, the camera controller 31 instructs the timing generation section 16 to return to the 2-channel read mode within the V5 period as shown in FIG. 8C, and in response to this, the timing generation section 16 starts the CCD 4 from the next V6 period. The operation is switched to the 2-channel read mode. As a result, the charges exposed during the V5 period are read in the 2-channel read mode during the V6 period. Further, as shown in FIG.
The SP 18 is instructed to operate in the 2-channel read mode.

As described above, the CCD 4 and the photographing circuit block 10 operate in the 1-channel read mode only when processing the photographed image to be recorded on the PC card, and operate in the 2-channel read mode otherwise. I am trying to do. As a result, DSP1
Even if the field memory is not arranged in the input stage of 8, the interlaced image data is generated at the time of monitoring and displayed by the electronic viewfinder 44, and the non-interlaced image data is generated at the time of shooting operation to generate the memory block 50. To the PC card and perform the required processing to record it on the PC card.

Since non-interlaced image data is generated during the operation in the 1-channel read mode, if the image data is supplied to the EVF block 40 as it is, the displayed image is disturbed. Therefore, as shown in FIG. 8H, the camera controller 31 mutes the image display of the electronic viewfinder 44 during the V3 to V5 periods in which the 1-channel reading mode is set. That is, the camera controller 31 is the image processing controller 6
The image processing controller 61 makes a request for mute processing to 1, and executes image display mute control of the electronic viewfinder 44. As described above, the image display operation of the electronic viewfinder 44 is prevented from being disturbed by the muting of the image display of the electronic viewfinder 44, although it is a moment for the user during the photographing operation.

Although the digital still camera as the embodiment has been described above, even if the digital still camera has a circuit configuration different from that of this example, the technology which is the gist of the present invention is introduced according to the circuit configuration. By doing so, it is possible to perform image processing compatible with both interlace / non-interlace with a simple circuit configuration.

In the above example, a digital still camera using a PC card as a recording medium has been described, but the present invention is also applicable to a digital still camera using another writable recording medium such as an optical disk, a magneto-optical disk, or a magnetic disk. Can be adopted.

[0091]

As described above, in the photographing apparatus of the present invention, as photoelectric conversion means, an operation of reading image data for one exposed frame in n periods by output of two systems and one exposed frame. The one that can switch the operation of reading the minute image data in a 2n period by the output of one system is used. When performing monitor display on the monitor means, the photoelectric conversion means is caused to perform two-system image data output operation, and the captured image processing means is caused to perform monitor-image data generation operation in response to two-system image data input. When executing the recording operation in the recording means, the photoelectric conversion means is caused to execute the image data output operation of one system, and the photographed image processing means is operated to record the image data in accordance with the image data input of one system. Is configured to be executed. That is, the image data is read line-sequentially from the photoelectric conversion means at the time of photographing. That is, in the present invention, by adopting the photoelectric conversion means capable of frame reading without the need for a mechanical shutter, it is possible to improve durability and simplify the mechanism, and to realize high-quality full-frame shooting. In addition, there is an effect that image data for real-time monitoring and image data for recording can be generated by a circuit system that does not use a field memory, and the circuit configuration can be greatly simplified and the cost can be reduced.

Further, while the photoelectric conversion means is executing the one-system image data output operation, the display output of the monitor means is muted, so that the disturbed monitor image can be prevented from being displayed. .

[Brief description of drawings]

FIG. 1 is a front view, a right side view, a plan view, a left side view, a bottom view, and a rear view of a digital still camera according to an embodiment of the present invention.

FIG. 2 is a block diagram of a digital still camera according to an embodiment.

FIG. 3 is a block diagram of a DSP of the digital still camera according to the embodiment.

FIG. 4 is a block diagram of a line memory unit of the digital still camera according to the embodiment.

FIG. 5 is an explanatory diagram of a CCD reading operation according to the embodiment.

FIG. 6 is an explanatory diagram of an operation of the line memory unit in the 2-channel read mode according to the embodiment.

FIG. 7 is an explanatory diagram of the operation of the line memory unit in the 1-channel read mode according to the embodiment.

FIG. 8 is an explanatory diagram of a switching operation between the 2-channel read mode and the 1-channel read mode at the time of shooting according to the embodiment.

FIG. 9 is an explanatory diagram of an IT type CCD solid-state imaging device.

FIG. 10 is an explanatory diagram of the operation of the mechanical shutter.

FIG. 11 is an explanatory diagram of a PS-CCD solid-state image sensor.

[Explanation of symbols]

1 lens block, 2 lens system, 3 lens driver, 4 CCD, 10 photographing circuit block, 11A, 11
B sample hold / AGC circuit, 12A, 12B
A / D converter, 13 horizontal / vertical drivers, 14 pilot signal generator, 15 gain controller, 16 timing generator, 17 D / A converter, 18 DSP, 19, 5
2 signal generator, 30 camera control block, 31 camera controller, 32, 63 E
EP-ROM, 33 main switch, 34 release switch, 35 reset circuit, 36 strobe unit, 40 EFV block 40, 41 character generator, 42 D / A converter, 43 video encoder, 44 electronic viewfinder, 50 memory block, 51 Memory controller, 53, 54 D-R
AM, 55 compression / expansion circuit 60 image processing control block, 61 image processing controller, 62 R
AM, 64 interface section, 66 PC card driver, 70 LCD block, 71 LCD unit, 72 mode / playback key, 88 line memory section, 8
9 aperture generator, 90 color process unit, 101, 102, 103, 104 line memory,
105, 107 switch, 106 line memory control unit

Claims (2)

[Claims] 1. An operation for reading exposed image data for one frame in n periods by output of two systems, and an operation of reading exposed image data for one frame in 2n by output of one system.
A photoelectric conversion unit capable of switching the reading operation in a period, a recording process for performing a predetermined process on the image data output from the photoelectric conversion unit, outputting it as monitor image data, and further recording it on a recording medium. Photographed image processing means capable of outputting as image data, monitor means capable of performing display output operation by monitor image data supplied from the photographed image processing means, and recorded image supplied from the photographed image processing means A recording unit capable of recording data on a recording medium; and when performing monitor display on the monitor unit, the photoelectric conversion unit is caused to perform two-system image data output operation, and the photographed image processing unit is The monitor image data generation operation is executed in response to the two-system image data input, and the recording means When the recording operation is executed, the photoelectric conversion means is caused to perform one system of image data output operation, and the photographed image processing means is operated to generate recorded image data in response to one system of image data input. An image pickup apparatus, comprising: a control unit that performs control so as to execute. 2. The control means is provided to the photoelectric conversion means.
The imaging apparatus according to claim 1, wherein the display output of the monitor means is muted while the system image data output operation is being executed.