JPH09219510A - Reverse conduction semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a reverse conduction semiconductor device where an insulation failure is prevented from occurring on the surface of an isolator, and the isolator is enhanced in isolation resistance by a method wherein a first conductivity-type impurity layer is selectively diffused between second conductivity-type impurity layers which are selectively diffused. SOLUTION: A buried gate-type switching device (SI) is formed inside a semiconductor substrate 7, a diode is formed in reverse parallel with the buried gate-type switching device (SI), and first conductivity-type impurity layers 4 in contact with the gate electrode 10 of the buried gate-type switching device (SI) are selectively formed between the buried gate-type switching device (SI) and the diode. Then, the first conductivity-type impurity layers 4 are buried deep in a second conductivity-type epitaxial growth layer 6 of the same conductivity-type with the semiconductor substrate 7, and second conductivity- type impurity layers 2 are selectively diffused into the surface of the epitaxial growth layer 6 just above the first conductivity-type impurity layers 4, and a first conductivity-type impurity layer 3 is formed between the second conductivity-type impurity layers 2 by selective diffusion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device, and more particularly to a reverse conducting semiconductor device in which a switching device portion and a diode portion are formed in antiparallel on the same substrate.

[0002]

2. Description of the Related Art Conventionally, when a power semiconductor device is used to construct an applied device such as an inverter, a diode is often connected in antiparallel with a main switching device. For this reason, there is an example in which a GTO thyristor part and a diode part are formed in antiparallel on the same semiconductor substrate like a reverse conducting GTO thyristor and put into practical use to help miniaturize the device.

This reverse conducting GTO thyristor (hereinafter RC-
The case of GTO) will be described as an example. FIG. 9 shows a schematic cross-sectional structure diagram of a conventional RC-GTO. In FIG. 9, 1 is an oxide film, 7 is an n ⁻ substrate, 8 ′ is a depletion layer, and 10 ′.
Is a gate electrode, 11 'is a cathode electrode, 12' is an anode electrode, 13 'is a GTO p-emitter layer, and 14' is GT.
O n ⁺ short layer, 15 'is a diode n emitter layer, 16' is a diode p emitter layer and GTO
P base layer, 17 'cathode contact electrode, 18' anode contact electrode, 19 'GTO n emitter layer, 21
Is the mesa etch part, GTO is the GTO part, SA is the separator part,
D is a diode portion, K is a cathode terminal, and A is an anode terminal. The GTO portion (GTO) of the RC-GTO and the diode portion (D) are integrally formed via the separation band portion (SA) having the mesa etch portion 21 provided in the p base layer (diode p emitter layer) 16 'of the GTO. ing. The respective conduction forward directions are as shown by arrows (↑, ↓).

A p-emitter layer 13 'of GTO, an n ⁺ short layer 14' of GTO, and an n-emitter layer 15 'of a diode are formed on the anode electrode 12' side. An n emitter layer 19 'of GTO, a gate electrode 10', and a diode p emitter layer 16 'are formed on the cathode electrode 11' side, and are short-circuited by an external cathode pressure contact electrode 17 '. Since the diode p emitter layer 16 'and the GTO p base layer 16' are formed in common, the separation band portion (S
If the separation band resistance r _SEP is not set more than necessary in A), there is a possibility that the breakdown voltage between the gate electrode 10 'and the cathode electrode 11' required in the switching operation of the GTO may not be obtained. Therefore, the mesa-etched portion 21 is formed in the diode p emitter layer (GTO p base layer) 16 '.
To form a separator resistance r _SEP .

FIG. 10 shows a schematic circuit configuration diagram and a withstand voltage characteristic in the separation band portion through the separation band resistance r _SEP between the GTO portion and the diode portion used in the conventional RC-GTO. The separator resistance r _SEP in FIG 10, the gate (G) a cathode (K) between the withstand voltage characteristics, the breakdown voltage (v _bo) to reverse bias voltage (V _RGM)
The reverse current (I _RGM ) is linear to V / I = r
_It shows a tendency to maintain the slope of _SEP and rise. Therefore, when the gate and cathode of the GTO section are reverse-biased in the turn-off switching mode or the like, r _SEP -60 Ω
_Depending on the degree, useless power loss occurs in the gate portion corresponding to I ² × r _SEP . This is a major obstacle in forming a highly efficient semiconductor device. Further, it is very difficult to stably form the mesa-etched portion 21 in the separation band portion between the devices by the mesa-etching forming method as described in FIG. 9 and to make the mesa-etched portion 21 uniformly in the circumferential direction. This is a problem in terms of device reliability and manufacturing yield.

[0006]

The object of the present invention is to obtain uniform etching in the separation zone between the switching device section and the diode section, to prevent insulation failure on the surface of the separation zone, and to provide excellent isolation. It is to provide a reverse conducting semiconductor device having a resistance.

[0007]

FIG. 3 is an enlarged schematic sectional structural view of a separator structure portion of a reverse conducting semiconductor device of the present invention. In FIG. 3, 1 is an oxide film, 2 is a surface n ⁺
Layer 3, surface p layer, 4 buried p ⁺ layer, 5 n layer, 6 epitaxial growth layer, 7 n ⁻ substrate, 8 depletion layer. Further, v _a is the breakdown voltage of the p ⁺ (4) n (5) (n ⁻ (7)) junction, v _b is the breakdown voltage of the n ⁺ (2) p (3) junction, and d _p is the diffusion depth of the surface p layer 3. Where d _{n +} is the diffusion depth of the surface n ⁺ layer 2, d _epi is the thickness of the epitaxial growth layer 6, and d _pB is the thickness of the buried p ⁺ layer.

The basic structure of the present invention will be described with reference to FIG. Gate electrode of switching device (1
0) in contact with the first conductivity type impurity layer (4) is selectively provided, and the same second conductivity type epitaxial growth layer (6) as the n ⁻ substrate (7) is buried. A second conductivity type impurity layer (2) is selectively diffused from the surface of the epitaxial growth layer (6) directly above the buried first conductivity type impurity layer (4), and the second conductivity type impurity layer (2) is further formed. A first conductivity type impurity layer (3) is selectively diffused between the layers (2). This structure is called a buried separation area (BSA) structure. At least one buried type separator structure between the respective diode parts, which may be formed on the same semiconductor substrate at the same time as the buried gate type switching device part and in antiparallel, and in some cases, the bevel structure part. Have.

Therefore, the structure of the present invention is as follows. That is, between the embedded gate type switching device section (SI) formed in the semiconductor substrate (7) and the diode section (D) which is anti-parallel with the embedded gate type switching device section (SI). A second conductivity type identical to that of the semiconductor substrate (7) by selectively forming a first conductivity type impurity layer (4) in contact with the gate electrode (10) of the buried gate type switching device part (SI). The first conductivity type impurity layer (4) is buried in the epitaxial growth layer (6) of the second growth type, and the second conductivity type is formed right above the first conductivity type impurity layer (4) buried from the surface of the epitaxial growth layer (6). The impurity layer (2) is selectively diffused, and the first conductivity type impurity layer (3) is selectively diffused between the selectively diffused second conductivity type impurity layers (2). The embedded type separator structure Having the configuration as a reverse conducting semiconductor device.

Alternatively, in the reverse conducting semiconductor device, the buried portion is provided between the switching device portion (SI) or the diode portion (D) and the end portion (E) formed on the surface of the same semiconductor substrate (7). It has a structure as a reverse conducting semiconductor device characterized by having a mold separator structure.

Alternatively, the end portion (E) has a structure as a reverse conducting semiconductor device, which is a bevel structure portion.

[0012]

The electrical isolation characteristics of the switching device section (SI) and the diode section (D) are determined by the value of the separation band resistance r _SEP generated between the gate electrode (10) and the diode anode electrode (11). To be done.

The BSA section that generates the separation band resistance r _SEP is
Due to the electrostatic induction effect, the depletion layer is moved from end to end so that the blocking voltage applied to the switching device unit (SI) and the reverse blocking voltage applied to the diode unit (D) are approximately equal. It is characterized in that the transmitted electric field is relaxed and a junction breakdown voltage is generated by the repeated junction structure of the pnpn ... Junction.

In the BSA structure of the present invention having a depletion layer spreading as shown in FIG. 3, the electric field distribution is mainly the buried p ⁺ layer 4, and the n ⁻ substrate 7 and n layer 5 in contact with the buried p ⁺ layer 4.
Is formed so that a strong electric field is shared between and, and a weak electric field is supplementarily shared near the surface of the epitaxial growth layer 6. Further, by satisfying the relationship of v _a ≦ v _b, the electric field strength applied to the vicinity of the surface is relaxed, and the separation band resistance value varies due to the accumulation of charges in the surface protective film due to the high dv / dt application. The above problems are greatly improved.
A conventionally proposed structure for relaxing the electric field strength near the surface is a guard ring structure disclosed in Japanese Patent Laid-Open No. 59-76466. However, the BSA structure of the present invention has a much lower surface electric field strength. It

As described above, the BSA structure shown in the present invention is
Forming a separation band showing a resistance value of infinite resistance in terms of potential capacitive coupling between the switching device section, diode section, and bevel section, etc., formed on the same substrate. Is possible.

[0016]

FIG. 1 is a schematic sectional structural view of a reverse conducting semiconductor device as a first embodiment of the present invention. FIG. 1 shows an SI thyristor unit (S
1 shows a reverse conducting SI thyristor in which I) and a diode portion (D) are formed adjacent to each other.

FIG. 2 shows a schematic circuit configuration diagram of the reverse conducting semiconductor device of the present invention shown in FIG. 1 and withstand voltage characteristics in the separation band portion.

A buried separation band portion is formed between the SI thyristor portion (SI) and the diode portion (D). FIG.
In the inside of the SI thyristor (SI), 13 is the p emitter layer of the SI thyristor, and 14 is the n ⁺ of the SI thyristor.
Short layer, 7 is n ⁻ substrate, 8 is depletion layer, 4 is buried p ⁺
A layer, 19 is an n emitter layer of the SI thyristor, 9 is a cathode electrode of the SI thyristor portion, and 10 is a gate electrode.

In the diode portion (D), 1
6 is a diode p emitter layer consisting of two layers, 15 is a diode n emitter layer, and 11 is a diode anode electrode. Reference numeral 12 is a common anode electrode, which is in contact with an external anode pressure contact electrode 18. 17 is an anode pressure contact electrode 18
Is a cathode pressure contact electrode facing the. In addition, the separator (B
In SA), 1 is an oxide film, 2 is a surface n ⁺ layer, 3 is a surface p layer, and 4 is a buried p ⁺ layer.

An enlarged view of part A in FIG. 1 corresponds to FIG. The depletion layer 8 spreading from the SI thyristor (SI) side spreads widely in the n ⁻ substrate 7, while it is diffused from the surface into the n layer 5 of the epitaxial growth layer 6 having a relatively high n-type impurity density. The impurity density, the thickness, etc. of the n layer 5 are set so that the surface of the n ⁺ layer 2 just reaches the surface n ⁺ layer 2.

Even if an impurity density gradient is set in the n layer 5,
Alternatively, it may be formed as a layer having a uniform impurity density. Further, the value of the reverse breakdown voltage v _b at the n ⁺ p junction generated between the surface n ⁺ layer 2 and the surface p layer 3 which is also selectively formed is the value of the buried p ⁺ layer 4 and n ^−. The reverse breakdown voltage v _a between the substrate 7 and the n-layer 5 side is set to be higher than or about the same. That is, v _a ≦ v _b . In particular, the enlarged view of the portion a in FIG. 3 corresponds to FIG. That is, FIG. 4 is a further enlarged schematic cross-sectional structure diagram in the vicinity of the surface of the separation band portion of the reverse conducting semiconductor device of the present invention, an impurity density distribution diagram by diffusion from the surface, and a schematic diagram of breakdown voltage characteristics in the vicinity of the surface of the separation band portion. The figure is shown.

Surface n ⁺ layer 2 from silicon surface, surface p
The distribution of the impurity density N of the diffusion layer of the layer 3 and the n layer 5 in the depth d direction is shown in FIG. N ⁺ (2) generated here
reverse breakdown voltage v _b in p (3) junction is to have a hard v-i characteristic as shown in FIG.

The actual separation band resistance is a series characteristic in which the reverse breakdown voltage characteristics shown in FIG. 4 are continuous. Therefore, as a whole, as shown in the withstand voltage characteristic in the separation band portion of the RC-SI thyristor in FIG. 2, the gate-cathode withstand voltage characteristic of the reverse conduction switching device, that is, V _RGM -I _RGM characteristic is the separation band resistance r _SEP. Has a hard characteristic. In this case, n ⁺ (2) p shown in FIG. 4 is provided between the gate electrode 10 and the diode anode electrode 11 of the SI thyristor of FIG.
(3) If there are m junctions, theoretically the breakdown voltage is m × v
_b or more. As a result, the breakdown voltage of the separation band portion can be set to be equal to or higher than the reverse breakdown voltage value between the gate electrode 10 and the cathode electrode 9 of the original SI thyristor.

In FIG. 1, SI thyristor unit (SI)
Embedded p ⁺ layer 4 and the diode p of the diode section (D)
The emitter layer 16 is formed at the same time. The gate breakdown voltage of the SI thyristor (SI), which is a problem in each operation, is SI
When the thyristor unit (SI) and the diode unit (D) operate separately, they are designed so as not to adversely affect the operation of the other.

When the SI thyristor section (SI) and the diode section (D) are operated separately, the dimension of the separation band width M is usually set so that carriers generated on one side do not affect the other. Set 10 times or more of the diffusion length. For example, M = 2000 μm.

With reference to FIG. 3, design values will be further described with respect to dimensional examples of each part. The width of the surface n ⁺ layer 2 l _n = 70 μm,
The diffusion depth d _{n +} = 5 μm. Width of surface p layer 3 l _p = 1
0 μm, diffusion depth d _p = 2.5 μm. Resistivity is 3
Ω · cm thickness of epitaxial growth layer 6 d _epi = 16
μm. The thickness of the buried p ⁺ layer 4 was set to d _pB = 27 μm. By repeatedly forming such a basic BSA structure, the separation band resistance r _{SEP of the} BSA structure shown in FIG.
As a result, an almost infinite value can be obtained. This is approximately 700 between the gate electrode 10 and the diode anode electrode 11.
It is also clear from the fact that when V is applied, the leakage current is only 0.01 mA. That is, the separation band resistance r _SEP = 700 (V) /0.01×10
It can be seen that ^-3 (A) ≈ 7 x 10 ⁷ (Ω).

The resistance value of the separator is RC which has been practically used in the past.
In the case of -GTO, r _SEP ≅60Ω, which is an order of magnitude higher in the examples of the present invention.

Since the resistance value of the separation band is similar to the insulation resistance value, when the RC-SI thyristor is assembled and pressure-welded, the cathode pressure-contact electrode 17 is used to form the cathode electrode 9 of the SI thyristor.
Even if the diode anode electrode 11 is short-circuited, the leak current between the gate electrode 10 of the SI thyristor and the cathode electrode 9 of the SI thyristor is extremely low. The leakage current is kept extremely low at least up to the voltage applied to the separation band resistance, for example, 700V. Therefore, the SI thyristor (S
The withstand voltage between the gate and the cathode of I) becomes a value close to the value originally possessed as a single device of SI thyristor, and RC-SI
Even after assembled as a thyristor, the same breakdown voltage can be obtained.

Regarding the problem that when the forward blocking characteristic of the SI thyristor is a normally-on type and the value of the separation band resistance r _SEP is low, the original withstand voltage of the SI thyristor cannot be obtained. It has already been pointed out in "Reverse Conduction Static Induction Thyristor". In the BSA structure shown in the embodiment of the present invention shown in FIG. 1, the separation band resistance r _SEP ≉7 × 10 ⁷ (Ω) can be set, so that when the SI thyristor portion which is a switching device is a normally-on type. Can also be applied sufficiently.

FIG. 5 is a schematic sectional structural view of a reverse conducting semiconductor device as a second embodiment of the present invention. Figure 5 is B
In this example, the SA structure is set between the diode part (D) and the edge part (E) having the bevel structure. Although the switching device section (SI) is not particularly shown in FIG. 5, it is needless to say that it is formed in antiparallel as in FIG.

In FIG. 5, areas corresponding to those in FIG. 1 are designated by the same reference numerals. 20 is the n ⁺ guard layer of the bevel part, 2
3 is a p-guard layer. x _E represents the junction depth of the diode p emitter layer 16, and x _B represents the junction depth of the p guard layer 23.

In FIG. 5, since the BSA structure is formed between the diode portion (D) and the edge portion (E), carriers generated in the strong electric field region of the bevel portion flow into the diode portion (D). To prevent it.

In the diode section (D) in FIG.
The buried p ⁺ layers in the diode p emitter layer 16 are formed in parallel in the lateral direction of the p guard layer 23 at the edge portion (E) having the bevel structure.

As is well known, the reverse recovery characteristic is one of the important characteristics of the diode part. However, in order to set the forward voltage drop to be small and to obtain a fast reverse switching characteristic with a small amount of reverse recovery charge, It is necessary that unnecessary carrier injection into the n ⁻ substrate 7 is not performed in both the vertical and horizontal directions. That is, the emitter injection efficiency γ from the diode p emitter layer
Is required to be small.

Generally, in a device having a bevel structure, the p-guard layer 23 at the bevel portion is formed deeply so as to prevent local concentration of the electric field. On the other hand, this p-guard layer 23
When is used as a p-emitter layer, an increase in carrier injection efficiency can be expected. Here, p guard layer 23
The emitter injection efficiency γ when used as the emitter layer can be approximately represented by Expression 1. That is,

[0036]

[Equation 1]

Here, D _P is the diffusion coefficient of holes in the n ⁻ substrate 7, D _E is the diffusion coefficient of electrons in the p-gate layer 23 as the p emitter layer, and N _B is the impurity concentration of the n ⁻ substrate 7. , N _E
Is the impurity concentration of the p guard layer 23 as the p emitter layer,
W is the thickness of the n ⁻ substrate 7, L _E is p as the p emitter layer
This is the diffusion length of electrons in the guard layer 23.

The emitter injection efficiency γ associated with the hole injection from the p-guard layer 23 to the n ⁻ substrate 7 is such that N _B / N _E is made small, that is, the concentration of the n ⁻ substrate 7 is lowered and the p-guard layer 2 is reduced.
It can be increased by increasing the concentration of 3. In addition, the relative relationship between the p guard layer 23 and the n ⁻ substrate 7 is p
The emitter injection efficiency γ can also be increased by forming the guard layer 23 deep and setting the impurity density distribution in the p-guard layer 23 to have a gentle gradient distribution so that a drift electric field for holes is generated. You can

Therefore, the bevel portion is reverse-biased p ⁺
(23) To alleviate the electric field in the n ⁻ (7) junction, the concentration of the n ⁻ substrate 7 is decreased, the concentration of the p guard layer 23 is increased, and N _B / N _E is set small, and the p guard layer is reduced. It is necessary to have a structure in which the emitter injection efficiency γ from the p-guard layer 23 is set large, for example, by forming 23 deep. That is, the p-emitter (1) of the diode part that requires high-speed performance compatible with the high-speed switching performance of the SI thyristor, etc.
6) -n - ⁽⁷⁾ as compared to being required to set small emitter injection efficiency for junction of the bevel portion ^{p + (23) n - (} 7) with respect to the junction, the electric field On the contrary, a design policy in the direction of setting the emitter injection efficiency high is required as a configuration for relaxation.

Therefore, the diode part (D) and the bevel part are preferably separated from each other in terms of operating characteristics. Therefore, in the embodiment of FIG. 5, the relationship between the junction depth x _E of the diode p emitter layer 16 and the junction depth x _B of the p guard layer 23 at the bevel portion is set to be x _E <x _B. BSA
The effect of the structure can be further enhanced.

FIG. 6 is a schematic sectional structural view of a reverse conducting semiconductor device as a third embodiment of the present invention. The BSA structure has a structure in which the reverse conduction semiconductor device is arranged from the center toward the outer periphery between the SI thyristor part (SI) and the diode part (D) (BSA1) and between the diode part (D) and the bevel part (E) (BSA2). ) Shows a structure provided in two places.

In FIG. 6, regions corresponding to those in FIGS. 1 and 5 are designated by the same reference numerals. The oxide film 1 is omitted in FIG.

Among them, as the diode part (D), Japanese Patent Application No. 7-245201 (filed on Aug. 31, 1995)
The electrostatic induction p-emitter structure disclosed in "Diode" is adopted. By adopting this structure, it is possible to realize an RC-SI thyristor having excellent withstand voltage stability at the end portion and the bevel portion without impairing the withstand voltage of the SI thyristor.

FIG. 7 is a schematic sectional structural view of a reverse conducting semiconductor device as a fourth embodiment of the present invention. FIG.
In the separation zone (BSA), the buried p ⁺ layer 4, surface n
An example is shown in which the pitches of the ⁺ layer 2 and the surface p layer 3 are not uniform.
Such a non-uniform pitch is determined by appropriately calculating the electric field distribution.

In the embodiment of FIG. 7, an i substrate 7'having a particularly high resistance is used in order to adopt a non-uniform pitch in the BSA structure. For example, the resistivity is several hundred Ω · cm to several tens of k
Use a substrate of Ω · cm.

In FIG. 7, regions corresponding to those in FIGS. 1, 5 and 6 are designated by the same reference numerals. 22 denotes an n buffer layer (n _bu ).

FIG. 8 is a schematic sectional structural view of a reverse conducting semiconductor device as a fifth embodiment of the present invention.

FIG. 8 shows an example of the same reverse conducting SI thyristor which does not have a bevel structure but has a field limiting ring (FLR) structure formed on the outer peripheral portion. SI thyristor part (SI), separation band part (BS
A), a diode part (D), and a field limiting ring (FLR) are formed in this order.

8, FIG. 5, FIG. 6 and FIG.
The areas corresponding to are designated with the same reference numerals. Reference numeral 24 represents an outer peripheral electrode of the FLR, and 25 represents a surface n ⁺ layer of the FLR.

Further, when the reverse conduction switching device and the diode portion are formed in the same semiconductor substrate, the reverse conduction switching device is not fixedly formed from the central portion to the outer peripheral portion, but the outermost peripheral portion is a switching device such as the SI thyristor portion. It may be a department. Needless to say, a buried gate type device such as an SI transistor is applied as the switching device in addition to the SI thyristor.

[0051]

According to the present invention, since the etching uniformity can be obtained on the separation band portion, a reverse conducting semiconductor device having excellent separation resistance in which insulation failure on the surface of the separation band hardly occurs can be obtained. Further, since there is little mutual interference in the dynamic characteristics of the switching device section and the diode section, there is also an advantage that the respective device structures can be optimized.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional structure diagram of a reverse conducting semiconductor device as a first embodiment of the invention.

FIG. 2 is a schematic circuit configuration diagram of a reverse conducting semiconductor device of the present invention and a schematic diagram of breakdown voltage characteristics in a separation band portion.

FIG. 3 is an enlarged schematic cross-sectional structure diagram of a separator structure portion of the reverse conducting semiconductor device of the present invention.

FIG. 4 is a further enlarged schematic cross-sectional structure diagram in the vicinity of the surface of the separation band portion of the reverse conducting semiconductor device of the present invention, an impurity density distribution diagram by diffusion from the surface, and a schematic diagram of breakdown voltage characteristics in the vicinity of the surface of the separation band portion.

FIG. 5 is a schematic cross-sectional structure diagram of a separator structure of a reverse conducting semiconductor device as a second embodiment of the present invention.

FIG. 6 is an SI thyristor section, a separator section, a diode section of a reverse conducting semiconductor device according to a third embodiment of the present invention;
Schematic cross-sectional structure diagram of the edge part

FIG. 7 is a schematic cross-sectional structure diagram of a reverse conducting semiconductor device as a fourth embodiment of the present invention.

FIG. 8 is a schematic cross-sectional structure diagram of a reverse conducting semiconductor device as a fifth embodiment of the invention.

FIG. 9 is a schematic cross-sectional structure diagram of a conventional reverse conducting GTO.

FIG. 10 is a schematic circuit configuration diagram of a conventional RC-GTO and a schematic diagram of withstand voltage characteristics in a separator.

[Explanation of symbols]

1 oxide film 2 surface n ⁺ layer 3 surface p layer 4 buried p base layer 5 n layer 6 epitaxial layer 7 n ^- cathode electrodes 10 and 10 'the gate electrode of the substrate 7' i substrates 8, 8 'depletion 9 SI thyristor 11 diode anode electrode 11 'cathode electrodes 12 and 12' anode electrode 13 p emitter layer of p-emitter layer 13'GTO the SI thyristor 14 SI thyristor of the n ⁺ short layer 14'GTO n ⁺ short layer 15, 15 'diodes n Emitter layer 16, 16 'Diode p emitter layer 17, 17' Cathode pressure contact electrode 18, 18 'Anode pressure contact electrode 19 SI thyristor n emitter layer 19' GTO n emitter layer 20 n ⁺ guard layer 21 Mesa etch part 22 n buffer layer 23 p surface of the guard layer 24 FLR peripheral electrode 25 FLR of n ⁺ r _SEP separator resistance ^{_{v a p + (4) n}} (5) (n - (7)) breakdown voltage ^{_{v b n + (2) p}} (3) diffusion depth of the pressure d _p surface p layer 3 of bonding the bonding d _{n +} surface n ⁺ layer 2 diffusion depth d _epi epitaxial growth layer d _pB buried p ⁺ layer thickness l _p surface p layer 3 width l _n surface n ⁺ layer 2 width x _E diode p emitter layer 16 Junction depth x _B p Junction depth of guard layer 23

Claims (3)

[Claims] 1. The embedded gate type switching device unit is provided between an embedded gate type switching device unit formed in a semiconductor substrate and a diode unit arranged in antiparallel with the embedded gate type switching device unit. Selectively forming a first conductivity type impurity layer in contact with the gate electrode of
The first-conductivity-type impurity layer is buried in the same second-conductivity-type epitaxial growth layer as the semiconductor substrate, and the second-conductivity-type impurity layer is provided right above the first-conductivity-type impurity layer buried from the surface of the epitaxial growth layer. And a first conductivity type impurity layer is selectively diffused between the selectively diffused second conductivity type impurity layers. A reverse conducting semiconductor device having. 2. The buried type separation band structure is provided between an end portion and a switching device portion or a diode portion formed on the surface of the same semiconductor substrate in the reverse conducting semiconductor device. 1. The reverse conducting semiconductor device according to 1. 3. The reverse conducting semiconductor device according to claim 2, wherein the end portion is a bevel structure portion.