JPH09218781A - Remote maintenance system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a remote maintenance system which can collectively maintain/manage internal circuit program data of FPGA(field programmable gate array) and which can easily rewrite the internal circuit program of FPGA in a field. SOLUTION: A device 2 having FPGA 7a, 7b, 8a and 8b is connected with a host 1 at a remote place through a communication network 3. The device 2 transmits a program request to the host 1 when it desires to program the internal circuits of FPGA 7a, 7b, 8a and 8b. The host 1 has internal circuit program data of FPGA 7a, 7b, 8a and 8b and transmits internal circuit program data to the device in accordance with the program request from the device 2. The device 2 programs FPGA 8a, 8b, 8a and 8b based on internal circuit program data received from the host 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a remote maintenance system, and more particularly to a field programmable gate array (FIELD PROGRAMMABLE GATE).
ARRAY, hereinafter referred to as "FPGA") to a remote maintenance system for performing maintenance such as programming from a remote location.

[0002]

2. Description of the Related Art An FPGA is a type of LSI, and is a gate array in which a user can freely change (program) an internal circuit at a site of use (field).

Conventionally, programming to FPGA is performed by F
The ROM is mounted on the printed board on which the PGA is mounted and the FPGA program is written in advance in this ROM, or the FPGA program is written in the internal ROM of the FPGA using a dedicated ROM writer. Was going by.

That is, conventionally, the user manually writes the data in the ROM in the field while considering the operation sequence of the device having the FPGA.

[0005]

The first problem is that, conventionally, the maintainability was poor because the internal circuit program data of the FPGA was rewritten in the field for each printed circuit board on which the FPGA was mounted. The reason is that there is no interface control function and database for the network.

The second problem is that in the prior art, the operability is poor or a redundant device is mounted. The reason is that the ROM had to be removed or a circuit corresponding to the ROM writer had to be mounted.

The present invention has been conceived in view of the above points. The maintenance and management of FPGA internal circuit program data can be collectively performed, and the FPGA internal circuit program can be easily rewritten in the field. It aims at providing the remote maintenance system which can be performed.

[0008]

In order to achieve the above object, the present invention connects a device having an FPGA and a host at a remote place via a communication network, and the device is the FP.
When programming the internal circuit of the GA, a program request is transmitted to the host, and the host has the internal circuit program data of the FPGA, and the internal circuit program data is sent in response to the program request from the device. Sending to the device, the device programs the FPGA based on internal circuit program data received from the host.

[0009]

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a remote maintenance system according to the present invention.

A host 1 such as a workstation or a personal computer has a storage unit 1a, a control unit 1b, and an interface unit 1c. The storage unit 1a has a network address of the device 2 and FPGAs 7a, 7b, 8 in the device 2.
Addresses for each of the hardware 7 and 8 equipped with a and 8b and internal circuit program data of the FPGAs 7a, 7b, 8a and 8b are stored as a database. Also,
The host 1 and the device 2 are connected via the communication network 3.

When the control unit 1b receives program transfer request data, which will be described later, from the device 2 via the communication network 3 and the interface unit 1c, the hardware 7,
The internal circuit program data of the hardware indicated by the address incorporated in the received program transfer request data out of 8 is read from the storage unit 1a. The control unit 1b incorporates the network address of the device 2 into the read internal circuit program data, and sends it to the device 2 via the interface unit 1c communication network 3.

The device 2 has one or more pieces of hardware equipped with a plurality of FPGAs, and the addresses stored in the database in the storage unit 1a are assigned to each. In the embodiment shown in FIG. 1, the device 2 is F
Hardware 7 equipped with PGA 7a and 7b and FP
The hardware 8 has the GAs 8a and 8b.

The FPGAs 7a, 7b, 8a, 8b have a normal operation mode and a programming mode, and the mode is switched by the normal operation mode signal and the programming mode signal from the control unit 5. The normal operation mode is a mode for operating based on the programmed internal circuit, and the programming mode is a mode for receiving internal circuit program data from the outside and changing the internal circuit based on the program data.

Active when a program is requested from the hardware 7 or 8 (others are inactive)
Is output, and this program request signal is input to the program request detector 9. The program request detection unit 9 determines which of the hardware 7 and 8 has activated the program request signal when the program request signal becomes active.
And the address generator 10 is notified.

Upon receiving the notification from the program request detection unit 9, the control unit 5 outputs a reset signal and activates the programming mode signal to the one of the hardware 7 and 8 which has activated the program request signal. To At this time, the normal operation mode signal for the hardware that activated the program request signal is kept inactive. As a result, the hardware that has activated the program request signal enters the programming mode and enters the waiting state for the internal circuit program data to be written.

Further, the address generation unit 10 which has received the notification from the program request detection unit 9 generates an address assigned to one of the hardware 7 and 8 that activates the program request signal, and the assemble / segment unit. 1
Output to 1.

In the assemble / segment unit 11 which receives the address of the hardware 7 or 8 that activates the program request signal, the assemble / segment unit 11 takes out the network address of the host 1 stored in the destination register 12 and converts it into a predetermined data format. By assembling, the program transfer request data addressed to the host 1 incorporating the network address of the host 1 is created. At this time, in the assemble / segment unit 11, the address generation unit 10
The address from is also incorporated into the program transfer request data and passed to the control unit 5.

Upon receiving the program transfer request data from the assemble / segment unit 11, the control unit 5 transmits the program transfer request data to the host 1 via the interface unit 4 and the communication network 3.

FIG. 2 is a flow chart for explaining the operation of the embodiment of the remote maintenance system according to the present invention shown in FIG.

Here, the F mounted on the hardware 7
The case of programming the internal circuits of the PGAs 7a and 7b will be described.
The same applies when programming the internal circuits of the GAs 8a and 8b.

If there is no internal circuit program inside the FPGA 7a, 7b or if the operation of the hardware 7 incorporating the FPGA 7a, 7b is not normal (F-1), the hardware 7 activates the program request signal.
Upon detecting this, the program request detection unit 9 notifies the control unit 5 to that effect. Upon receiving the notification from the program request detection unit 9, the control unit 5 outputs a reset signal to the hardware 7 and resets the abnormal block (F-2).
At the same time, the programming mode signal is activated and the normal operation mode signal is deactivated, and
Set A7a and 7b to programming mode (F-
3).

As described above, the control unit 5 sends the program transfer request data incorporating the address of the hardware 7 to the host 1. After that, the control unit 5 monitors the received data from the host 1 (F-4) and fetches the received data addressed to the device 2 (F-5), and the internal circuit of the FPGA 7a, 7b mounted on the hardware 7 is included therein. Program data is extracted and stored in the storage unit 6 (F-
6).

Next, the control unit 5 controls the F stored in the storage unit 6.
The internal circuit program data of the PGAs 7a and 7b are read (F-7), and the FPGAs 7a and 7b are programmed (F-8). When the programming is completed, the control unit 5 releases the reset to the hardware 7, activates the normal operation mode signal and inactivates the programming mode signal, and activates the FPGA 7
Set a and 7b to the normal operation mode (F-9).

[0025]

As described above, since the present invention does not require manual ROM allocation of internal circuit program data to FPGA in the field, operability of the apparatus is improved and connection with a general-purpose database is possible. Therefore, the maintainability is improved, and further, there is an effect that the device is simplified by a hardware configuration having general versatility.

That is, in the conventional method, a control circuit corresponding to a unique ROM writer has to be prepared for each printed board on which each FPGA is mounted, so that the circuit scale is large. According to the present invention, an FPG is assigned by assigning an address to each hardware equipped with each FPGA.
Since the program sequence control to A is performed, there is versatility and the device configuration is simplified.

Further, in the conventional method, since the internal circuit program of the FPGA is written in the ROM and mounted on the printed board, the operability is poor because it is carried out manually in the field. According to the present invention, since the database can be brought online via a network, the operability is significantly improved without manual operation in the field.

Further, in the conventional method, since the writing operation to the ROM is manually performed, the maintainability of the device is poor. According to the present invention, since it is an online system, the internal circuit program data of the FPGA can be managed by a database or the like, and the maintainability is greatly improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a remote maintenance system according to the present invention.

FIG. 2 is a flowchart for explaining the operation of the embodiment of the remote maintenance system according to the present invention shown in FIG.

[Explanation of symbols]

 1 host 1a storage unit 1b control unit 1c interface unit 2 device 3 communication network 4 interface unit 5 control unit 6 storage unit 7, 8 hardware 7a, 7b, 8a, 8b FPGA 9 program request detection unit 10 address generation unit 11 assembly / Segment 12 Destination register

Claims (3)

[Claims] 1. A device having an FPGA and a remote host are connected via a communication network, and the device sends a program request to the host when the internal circuit of the FPGA is desired to be programmed, The host has internal circuit program data of the FPGA, and transmits the internal circuit program data to the device in response to a program request from the device, and the device receives the internal circuit program received from the host. A remote maintenance system characterized by programming the FPGA based on data. 2. A communication unit for communicating with a device having an FPGA, a storage unit for storing internal circuit program data of the FPGA, and an internal circuit program stored in the storage unit in response to a request from the device. A remote maintenance system host, comprising: a transmission means for transmitting data to the device. 3. A communication means for communicating with a host, and an FP.
A GA, a transmission means for transmitting a program request to the host when it is desired to program the internal circuit of the FPGA, and a programming means for programming the FPGA based on the internal circuit program data received from the host. A device for a remote maintenance system characterized in that