JPH09213066A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily change the bank configuration. SOLUTION: A bank register 17 stores bank activation data BA for setting the number of banks, and subrow decoders 141 -14n connected to the selected word lines, WL1 to WLn, select a first- and a second subword line, SWL1 to SWl2 , to which memory cells MC of different numbers are connected in accordance with the bank activation data BA. Hence, by changing the bank activation data BA, the number of banks is easily changed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a plurality of banks, for example.

[0002]

2. Description of the Related Art In recent years, many semiconductor memory devices such as general-purpose DRAMs use a page mode for accessing while storing data in an amplifier or an amplifier as a cache memory. In this type of semiconductor memory device, data read from a memory cell is held in an amplifier. Therefore, the time from the access request to the data reading (data access time) can be significantly shortened compared to the method of selecting the memory cell and reading the data after the access request as in a normal memory. You can
Further, by introducing the concept of a bank into such a semiconductor memory device, the amplifiers included in each bank can hold data read from a plurality of memory cells corresponding to different row addresses. Therefore, the probability (hit rate) that an access request arrives at the row address in the selected state can be improved.

FIG. 5 shows an example of a conventional semiconductor memory device having a plurality of banks. This device comprises two banks 101, 102 of the same construction, each bank 101,
102 includes a memory cell array MCA. Each memory cell array MCA has a plurality of memory cells MC arranged in a matrix, and each memory cell M of the bank 101.
C is a bit line BL1A to BLnA and a word line WL1A
To WLnA, each memory cell M of the bank 102
C is a bit line BL1B to BLnB and a word line WL1B
~ WLnB. The bit lines BL1A to
BLnA is connected to the column decoder 105A via a plurality of amplifiers (AMPs) forming an amplifier group 107A, and the word lines WL1A to WLnA are row decoders 1
It is connected to 11A. Also, the bit line BL1B
To BLnB are connected to a column decoder 105B via a plurality of amplifiers AMP constituting an amplifier group 107B, and the word lines WL1B to WLnB are row decoders 111B.
It is connected to the. Each of the column decoders 105A, 1
05B is an input / output terminal 106 for inputting / outputting data.
A and 106B are provided.

Of the address signals included in the access request supplied separately for each bank, the upper bits are column addresses 103A and 103B, and the lower bits are row addresses 104A and 104B. The column addresses 103A and 103B are each column decoder 105A,
105B. Also, the row address 104
A and 104B are registers 108A and 108 of each bank.
B and the comparators 109A and 109B. Each of the registers 108A and 108B stores a row address corresponding to a memory cell in which data is held in the amplifier (AMP). When an access request is supplied to this semiconductor memory device, each comparator 109A, 109B compares the row address 104A, 104B included in the access request with the row address stored in the register 108A, 108B, and these are compared. If they match, a hit signal is output, and if they do not match, a mishit signal is output. When a hit signal is output, each register 108
The row addresses stored in A and 108B are not changed,
Each of the row decoders 111A and 111B has a register 108
The word line is selected according to the row address stored in A and 108B, and the required data is output only by selecting the bit line by the column address. In addition, each comparator 109A,
When the mishit signal is output from 109B, the row address stored in the registers 108A and 108B is rewritten to the row address included in the access request, and the word line is selected by the rewritten row address, and the column in this state is selected. The bit line is selected by the address.

The amplifiers forming the amplifier groups 107A and 107B of the banks 101 and 102 hold data of memory cells corresponding to different row addresses. That is, in the case shown in FIG. 5, in the bank 101, the word line WL2A is in the selected state, and the amplifier group 107A
Each amplifier holds the data of the memory cells connected by the word line WL2A. Also, bank 10
2, the word line WL1B is in the selected state, and the amplifier group 10
The data of the memory cells connected by the word line WL1B is held in each amplifier 7B. in this way,
The hit rate can be improved by setting a plurality of word lines in the selected state and selecting word lines corresponding to addresses different from each other.

[0006]

In the semiconductor memory device described above, the hit rate can be increased by increasing the number of banks. When the hit rate is increased, the number of times of reselecting the word line and reactivating the amplifier is reduced, so that the current consumption can be reduced. Further, when the hit rate is increased, the number of times to reselect the word line is reduced, and therefore, naturally, the time required for reading or writing data, that is, the latency can be improved as compared with the case of a miss hit.

However, if the number of banks is too large, the number of amplifiers for setting data increases, resulting in excessive power consumption, which may not satisfy the user's request.
In addition, when the number of banks is changed according to the user's request, it is possible to change the mask of the wiring layer or change the bonding wire when assembling. However, such a measure has a problem that it takes time to design and manufacture and causes a cost increase.

The present invention is intended to solve the above problems, and an object of the present invention is to provide a low cost semiconductor memory device in which the bank configuration can be easily changed. .

[0009]

In a semiconductor memory device of the present invention, a plurality of memory cells are arranged in rows and columns, and a plurality of memory cells arranged in a plurality of columns form a first bank. A memory cell array in which a second bank is formed by a plurality of memory cells arranged in the remaining columns, a plurality of bit lines arranged in the columns and connected to the plurality of memory cells, and arranged in the rows. A plurality of word lines and a first selection circuit that selects one bit line from the plurality of bit lines according to an address signal,
1 out of the plurality of word lines according to the address signal
A second selection circuit for selecting one word line; setting means for setting activation information of a bank to be activated in the memory cell array; and a first selection circuit connected to a plurality of memory cells forming the first bank. Sub word line, a second sub word line connected to a plurality of memory cells forming the second bank, and each word, and one word line is selected by the second selection circuit. Then, the third selection circuit for selecting the first and second sub-word lines according to the word line and the activation information set in the setting means is provided.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, the memory cell array MCA is composed of a plurality of memory cells MC arranged in a matrix in the row and column directions. Each memory cell MC has bit lines BL ₁ , BL _2, ... BL _n-1 ,
These bit lines BL ₁ , BL ₂ ... B are connected to BL _n .
L _n-1 and BL _n are amplifiers (AMP) 11 ₁ and 1 respectively.
The column decoder 12 is connected via 1 ₂ ... 11 _n-1 and 11 _n . The column address CLA is supplied to the column decoder 12, and the column decoder 12 selects a bit line in accordance with the column address CLA when reading data, and the bit line is held in the amplifiers 11 ₁ , 11 _2, ... 11 _n-1 , 11 _n. Output data.

The semiconductor memory device shown in FIG. 1 has two banks, and the number of banks of this memory device can be switched according to the bank activation data BA set in the bank register 17. There is. That is, the memory cells connected to the bit lines BL ₁ and BL _{2 form} the first bank BK1, and the memory cells connected to the other bit lines BL ₃ (not shown) ... BL _n-1 and BL _n. Cell is second
Of the bank BK2.

On the other hand, the word lines WL ₁ , WL ₂ ... WL _n are connected to the row decoder 13. Each word line WL
₁ , WL ₂ ... WL _n are sub-row decoders 14 ₁ and 14 ₂
... 14 _n are connected. Each sub row decoder 14 ₁ ,
14 ₂ ... 14 _n include first and second sub-word lines SWL ₁ ,
SWL ₂ is connected. Each sub row decoder 14 ₁ ,
14 ₂ ... 14 _n are in the state where the word line is selected,
The first and second sub-word lines SWL ₁ and SWL ₂ are selected according to the contents of the bank register 17. Each memory cell forming the first bank BK1 has a first sub word line S.
Each memory cell connected to WL ₁ and forming the second bank BK2 is connected to the _second sub word line SWL ₂ .

The row decoder 13 has a row address R.
A register 15 for storing OA is connected. The row address is supplied to the register 15 and the comparator 16.
The register 15 includes amplifiers 11 ₁ , 11 _2, ... 11 _n-1 , 11
_The row address corresponding to the memory cell holding the data is stored in _n . When an access request is supplied to this semiconductor memory device, the comparator 16 compares the row address included in the access request with the row address stored in the register 15, and if they match, a hit signal. Is output, and if they do not match, a mishit signal is output. When the hit signal is output, the row address stored in the register 15 is not changed and the required data is output only by selecting the bit line by the column address. When the mishit signal is output from the comparator 16, the row address stored in the register 15 is rewritten to the row address included in the access request, and the word line is selected by the rewritten row address. The bit line is selected by the column address.

The bank register 17 includes the first and second banks.
The bank register 17 holds bank activation data BA for selecting the banks BK1 and BK2. The bank register 17 is connected to the sub row decoders 14 ₁ , 14 ₂ ... 14 _n . The bank register 17 is provided with bank activation data BA for setting a bank by the user.
Is set, and the first and second banks BK1 and BK are set in accordance with the data set in the bank register 17.
2 is selected. As shown in FIG. 2, the bank register 17 is composed of, for example, 2 bits. When the upper bit is “1”, the first bank BK1 is activated, and when the lower bit is “1”, the first bank BK1 is activated. It is configured to activate BK2.

FIG. 3 shows the sub row decoders 14 ₁ and 14 _2.
... 14 _n . Sub row decoder 14 ₁ , 1
Since all 4 ₂ ... 14 _n have the same configuration, the configuration will be described using the sub row decoder 14 ₁ . The bank selection data BA1 output from the upper bit of the bank register 17 is supplied to one end of the current path of the P-channel transistor 31, and the lower bit of the bank register 18 is output to one end of the current path of the P-channel transistor 32. Bank activation data BA2 is supplied.
These transistors 31 and 32 are controlled by a refresh control signal RF that controls the refresh operation of the memory. The other ends of the current paths of these transistors 31 and 32 are connected to one input ends of NAND circuits 35 and 36 via inverter circuits 33 and 34, respectively. The word line W is connected to one input terminal of the NAND circuits 37 and 38.
L1 is connected, and the lower row address signal ROAL of "1" or "0" is supplied to the other input ends of the NAND circuits 37 and 38, respectively. The output terminals of the NAND circuits 37 and 38 are connected to the other input terminals of the NAND circuits 35 and 36, and the output terminals of the NAND circuits 35 and 36 are connected to the sub word lines SWL1 and SWL2.

In the above structure, as shown in FIG. 2, when the upper bit of the bank register 17 is set to "1" and the lower bit is set to "0", the first bank BK1 is selected. That is, when the refresh control signal RF becomes low level and the transistors 31 and 32 are rendered conductive, one input end of the NAND circuit 35 is set to the “0” level via the inverter circuit 33 and the inverter circuit 34. One input end of the NAND circuit 36 is set to the "1" level. In this state, when the word line WL1 is selected, the output end of the NAND circuit 37 is set to "0" level and the output end of the NAND circuit 38 is set to "1" level. Therefore, only the output terminal of the NAND circuit 35 becomes the "1" level, the sub word line SWL1 is selected,
Data is read from the memory cell connected to the sub word line SWL1. That is, in this case, only the first bank BK1 is selected.

When "1" is set in the upper and lower bits of the bank register 17, the word line W
When L1 is selected, the output terminals of the NAND circuits 35 and 36 both become "1" level, and the sub word lines SWL1 and SWL
2 is selected. That is, in this case, the first and second banks BK1 and BK2 are selected.

When the number of banks is increased in this way, the refresh cycle of the memory cell may be lengthened. However, when the refresh control signal RF becomes high level at the time of refresh, the transistors 31 and 32 become non-conductive and the bank activation data is cut off, so that a normal refresh operation can be performed according to the row address. .

According to the above embodiment, the sub row decoder 14
_1, 14 ₂ ... 14 _n is the bank selection data set in the bank register 17, and in accordance with the output signal of the row decoder 13, selects the sub-word lines SWL1, SWL2. Therefore, since the number of banks can be set according to the bank selection data set in the bank register 17, the mask layout of the wiring layer can be changed as in the conventional case, or the bonding wire connection position can be changed during assembly. Therefore, it is possible to prevent the manufacturing cost from rising and the number of manufacturing steps to increase. Moreover, since the number of banks can be set on the user side in response to the user's request, a highly versatile semiconductor memory device can be realized.

The bank register 17 is initialized once before the power is turned on, and then given a value commensurate with the desired number of banks. As a result, the bank activation data BA is changed and the number of banks is changed. In the case of this embodiment, the number of banks is two, but the number of banks is not limited to this and can be changed as appropriate. When the number of banks is increased, the number of memory cells in each bank is reduced, and when the number of banks is reduced, the number of memory cells in each bank can be increased. Further, the number of bits of the bank register 17 may be changed according to the maximum number of banks.

Further, the bank number setting means is not limited to the bank register, and a well-known antifuse, PROM or the like may be used. FIG.
It is a figure which shows the other Example of this invention, The same code | symbol is attached | subjected to the same part as FIG. 1, and only different part is demonstrated.

In this embodiment, the first and second memory cell arrays 21 and 22 share an Nch amplifier group 23 formed of N channel transistors.
The configurations of the second memory cell arrays 21 and 22 are the same as in FIG. N-channel transistors 24 are connected between the amplifiers constituting the Nch amplifier group 23 and one ends of the bit lines BL1 to BLn provided in the first and second memory cell arrays 21 and 22, respectively. The conduction of these transistors 24 is controlled by timing signals φ _TM and / φ _TM supplied to their gates. The first,
At the other ends of the bit lines BL1 to BLn provided in the second memory cell arrays 21 and 22, Pch amplifier groups 25a and 25b configured by P channel transistors are provided, respectively.
Are connected to the amplifiers.

As described above, by applying the present invention to a circuit in which the Nch amplifier group 23 is shared by the first and second memory cell arrays 21 and 22, a plurality of first and second memory cell arrays 21 and 22 are provided. Bank can be set. Such a configuration is advantageous because it can prevent an increase in chip area.

In both of the above embodiments, the memory cell array is divided in the row direction to set the banks, but the present invention is not limited to this, and the memory cell array is divided in the column direction to set the banks. It is also possible. Of course, various modifications can be made without departing from the scope of the present invention.

[0025]

As described above, according to the present invention,
It is possible to provide a semiconductor memory device in which the user can easily change the bank configuration without increasing the manufacturing cost and the number of manufacturing steps.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing an essential part of FIG.

FIG. 3 is a circuit diagram showing an essential part of FIG.

FIG. 4 is a configuration diagram showing another embodiment of the present invention.

FIG. 5 is a configuration diagram showing an example of a conventional semiconductor memory device.

[Explanation of symbols]

11 ₁ to 11 _n ... amplifier, 12 ... column decoder, 13 ... row decoder, 14 ₁ to 14 _n ... sub row decoder, 17 ... bank register, BA ... bank activation data, MC ... memory cells, BK1, BK2 ... first 1, the second bank, BL1 to BLn ... bit lines, WL1 to WLn ... word lines, SWL _1, SWL ₂ ... first, second sub-word lines.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroyuki Noji 25-1 Ekimaehonmachi, Kawasaki-ku, Kawasaki-shi, Kanagawa 1 Toshiba Microelectronics Corporation

Claims (6)

[Claims] 1. A plurality of memory cells are arranged in rows and columns, a first bank is constituted by a plurality of memory cells arranged in a plurality of columns, and a plurality of memory cells arranged in a remaining column. A memory cell array having a second bank, a plurality of bit lines arranged in the column and connected to a plurality of memory cells, a plurality of word lines arranged in the row, and a plurality of word lines arranged in response to an address signal. 1 out of multiple bit lines
A first selection circuit for selecting one bit line and one of the plurality of word lines in response to an address signal.
A second selection circuit for selecting one word line; setting means for setting activation information of a bank to be activated in the memory cell array; and a first connection connected to a plurality of memory cells forming the first bank. Sub word line, a second sub word line connected to a plurality of memory cells forming the second bank, and one word line connected to each word and selected by the second selection circuit. Then, depending on the word line and the activation information set in the setting means, the first and second
And a third selection circuit for selecting the sub-word line of the semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein the setting means is composed of a register for storing the activation information. 3. The semiconductor memory device according to claim 1, wherein the setting means is composed of an antifuse that stores the activation information. 4. The semiconductor memory device according to claim 1, wherein the setting means is constituted by a read-only memory that stores the activation information. 5. The third selection circuit includes a transistor whose conduction is controlled according to a refresh control signal, and the transistor allows the activation information to pass therethrough when the refresh control signal indicates non-refresh and refresh control is performed. 2. The semiconductor memory device according to claim 1, wherein when the signal indicates refresh, the activation information is cut off. 6. Each of the bit lines comprises a first amplifier composed of a transistor of a first conductivity type connected to the central portion thereof, and a transistor of a second conductivity type connected to both ends thereof. A second amplifier, and a first connecting the first amplifier to one side or the other side of the bit line,
2. The semiconductor memory device according to claim 1, further comprising a second transistor, wherein the first amplifier is shared by one side and the other side of the bit line.