JPH09212254A - Clock margin control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability by stabilizing a clock margin even when the peripheral temperature or impressed voltage of a semiconductor is changed and securing the stability and operation speed of the whole circuit. SOLUTION: A temperature detection means 1 detects the temperature of a semiconductor element in a semiconductor circuit 8 and sends a temperature detection signal. A temperature comparing means 3 compares the temperature detection signal sent from the means 1 with a prescribed reference temperature signal, detects a difference including the level relation of both the signals and sends a tempeature difference signal correspondingly to the detected result. A clock frequency control means 7 reduces the clock frequency of a clock signal so as to extend the generation period of the clock signal when the temperature detection signal is larger than the reference temperature signal based upon the temperature difference signal sent from the means 3 and increases the clock frequency when the temperature detection signal is smaller than the reference temperature signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock margin control device used in a clock synchronous semiconductor circuit, and more particularly, it can stabilize the clock margin even if any of voltage, temperature and clock frequency changes. The present invention relates to a clock margin control device that can improve reliability.

[0002]

2. Description of the Related Art At present, in semiconductor circuits used in various fields, the junction temperature of the semiconductor rises in proportion to the rise of the ambient temperature to generate thermal noise, which lowers the operating speed. It is known to end up. It is also known that as the applied voltage to the semiconductor increases, the electric field strength at the junction surface increases and the operating speed increases.

This type of semiconductor circuit is mounted on, for example, an industrial computer, and is composed of a plurality of flip-flops (hereinafter referred to as F / Fs) and logic circuits.
A clock synchronous semiconductor circuit that synchronizes F with a common clock signal is widely used.

In such a clock synchronous semiconductor circuit, a clock signal generated at a constant clock frequency is applied to each F / F. At this time, each F / F is propagated through various logic circuits. The respective digital signals have different propagation times. Therefore, the clock frequency is set so as to have a clock generation cycle (= 1 / clock frequency) longer than the propagation time of the most delayed digital signal. The time difference between the propagation time of the most delayed digital signal and the clock generation period is called a clock margin and is an index for stable operation.

Here, the clock margin tends to decrease in proportion to an increase in ambient temperature and increase in proportion to an increase in applied voltage. This tendency is explained in detail by taking the ambient temperature as an example. When the operating speed decreases due to the increase in the ambient temperature, the propagation time of the digital signal increases and the time difference from the clock generation cycle decreases. .

Further, the clock margin has a property of decreasing the operation speed of the entire semiconductor circuit in proportion to the magnitude of the value. For example, the clock margin increases in proportion to the clock generation period, but the clock generation period indicates the operating speed of the entire semiconductor circuit.

Such a clock margin needs to be set large in accordance with the deterioration of the ambient temperature or the environment of the applied voltage in order to show the stable operation of the circuit in proportion to the magnitude of the value, but it should be set large. If too much, the processing speed will be significantly reduced. Therefore, it is desired to set it to an appropriate value.

[0008]

However, in the clock synchronous semiconductor circuit as described above, the increase of the ambient temperature of the semiconductor and the decrease of the applied voltage increase the propagation time of the digital signal to decrease the clock margin, It reduces the stability of operation.

Similarly, a decrease in the ambient temperature of the semiconductor and an increase in the applied voltage increase the clock margin and reduce the operating speed of the entire circuit. That is, there is a problem that the clock margin is changed due to fluctuations in the ambient temperature of the semiconductor and the applied voltage, and the reliability of the entire circuit is reduced.

The present invention has been made in consideration of the above-mentioned circumstances, and stabilizes the clock margin even when the ambient temperature of the semiconductor or the applied voltage fluctuates to ensure the stability and operation speed of the entire circuit, thereby ensuring reliability. It is to provide a clock margin control device capable of improving performance.

[0011]

The invention according to claim 1 is for controlling a clock margin, which is a difference between a generation period of a clock signal and a maximum propagation time of a digital signal in a clock synchronous semiconductor circuit, to be constant. And a temperature detection means for detecting the temperature of a semiconductor element of the semiconductor circuit and transmitting a temperature detection signal corresponding to the detection result, and a temperature detection signal transmitted from the temperature detection means. And a predetermined reference temperature signal are compared with each other to detect a difference including a magnitude relationship between the two signals, and a temperature comparison means for transmitting a temperature difference signal corresponding to the detection result, and a temperature transmitted from the temperature comparison means. When the temperature detection signal is larger than the reference temperature signal based on the differential signal, the clock of the clock signal is set so as to lengthen the generation cycle of the clock signal. Reduce the wave number, when said temperature detection signal is smaller than said reference temperature signal is a clock margin controller having a clock frequency control means for increasing the clock frequency.

According to a second aspect of the invention, in the clock margin control device according to the first aspect, instead of the clock frequency control means, based on a temperature difference signal sent from the temperature comparison means, When the temperature detection signal is larger than the reference temperature signal, the applied voltage of the semiconductor circuit is increased so as to shorten the maximum propagation time of the digital signal, and the temperature detection signal is smaller than the reference temperature signal. At this time, the clock margin control device is provided with an applied voltage control means for decreasing the applied voltage.

The applied voltage control means may be added to the invention corresponding to claim 1. Further, the invention according to claim 3 is a clock margin control device for controlling a clock margin, which is a difference between a generation period of a clock signal and a maximum propagation time of a digital signal in a clock synchronous semiconductor circuit, to be constant. The voltage detection means for detecting the voltage applied to the semiconductor circuit and transmitting a voltage detection signal corresponding to the detection result, and comparing the voltage detection signal transmitted from the voltage detection means with a predetermined reference voltage signal. Then, the difference including the magnitude relationship between the two signals is detected, and based on the voltage difference signal sent from the voltage comparison means and the voltage comparison means for sending out the voltage difference signal corresponding to the detection result,
When the voltage detection signal is larger than the reference voltage signal,
Clock frequency control means for increasing the clock frequency of the clock signal so as to shorten the generation cycle of the clock signal and decreasing the clock frequency when the voltage detection signal is smaller than the reference voltage signal. It is a clock margin control device.

According to a fourth aspect of the invention, in the clock margin control device according to the third aspect, instead of the clock frequency control means, based on a voltage difference signal sent from the voltage comparison means, When the voltage detection signal is larger than the reference voltage signal, the cooling temperature is raised while cooling the semiconductor circuit so as to lengthen the maximum propagation time of the digital signal, and the voltage detection signal is the reference voltage signal. Is smaller than the above, the clock margin control device is provided with a cooling temperature control means for lowering the cooling temperature.

The cooling temperature control means may be added to the invention corresponding to claim 3. Further, the invention according to claim 5 is a clock margin control device for controlling a clock margin, which is a difference between a generation period of a clock signal and a maximum propagation time of a digital signal in a clock synchronous semiconductor circuit, to be constant. A frequency detection means for detecting a clock frequency which is the reciprocal of the generation cycle of the clock signal and transmitting a frequency detection signal corresponding to the detection result, a frequency detection signal transmitted from the frequency detection means and a predetermined frequency detection signal. A frequency comparison means for detecting a difference including a magnitude relationship between the two signals by comparing with a reference frequency signal, and transmitting a frequency difference signal corresponding to the detection result, and a frequency difference signal transmitted from the frequency comparison means. On the basis of the above, when the frequency detection signal is larger than the reference frequency signal,
An applied voltage control means for increasing the applied voltage of the semiconductor circuit so as to shorten the maximum propagation time of the digital signal, and for decreasing the applied voltage when the clock frequency detection signal is smaller than the reference frequency signal. It is a clock margin control device provided.

According to a sixth aspect of the invention, in the clock margin control device according to the fifth aspect, instead of the applied voltage control means, based on a frequency difference signal sent from the frequency comparison means, When the frequency detection signal is larger than the reference frequency signal, the cooling temperature is lowered while cooling the semiconductor circuit so as to shorten the maximum propagation time of the digital signal, and the frequency detection signal is the reference frequency signal. When it is smaller than the above, the clock margin control device is provided with a cooling temperature control means for increasing the cooling temperature.

The cooling temperature control means may be added to the invention corresponding to claim 5. Further, the invention according to claim 7 is a clock margin control device for controlling a clock margin, which is a difference between a generation period of a clock signal and a maximum propagation time of a digital signal in a clock synchronous semiconductor circuit, to be constant. Based on the difference between the applied voltage of the semiconductor circuit and a predetermined voltage target value, the applied voltage control means for controlling the applied voltage so as to eliminate this difference, and the temperature of the semiconductor element of the semiconductor circuit and the predetermined value. Based on the difference with the temperature target value of, temperature control means for controlling the temperature of the semiconductor element so as to eliminate this difference,
Frequency control means for controlling the clock frequency so as to eliminate this difference based on the difference between the clock frequency that is the reciprocal of the generation period of the clock signal and a predetermined frequency target value, the applied voltage, and the semiconductor element. When at least one of the three elements of the temperature and the clock frequency fluctuates beyond the reference value, the target value corresponding to the remaining elements is changed so as to stabilize the clock margin. And a target value changing means to be given to the control means.

Therefore, in the invention according to claim 1, the temperature detecting means detects the temperature of the semiconductor element of the semiconductor circuit by taking the above-mentioned means, and the temperature detection signal corresponding to the detection result. And the temperature comparison means compares the temperature detection signal sent from the temperature detection means with a predetermined reference temperature signal to detect a difference including a magnitude relationship between the two signals,
The temperature difference signal is transmitted in response to this detection result, and the clock frequency control means, based on the temperature difference signal transmitted from the temperature comparison means, when the temperature detection signal is larger than the reference temperature signal, The clock frequency of the clock signal is lowered so as to lengthen the generation cycle, and when the temperature detection signal is smaller than the reference temperature signal, the clock frequency is raised, so the clock margin is stabilized even if the ambient temperature of the semiconductor fluctuates. Thus, the stability and operating speed of the entire circuit can be secured, and thus the reliability can be improved.

Further, in the invention according to claim 2, the applied voltage control means makes the temperature detection signal larger than the reference temperature signal based on the temperature difference signal sent from the temperature comparison means according to claim 1. At this time, the applied voltage of the semiconductor circuit is increased so as to shorten the maximum propagation time of the digital signal, and when the temperature detection signal is smaller than the reference temperature signal, the applied voltage is decreased. Similarly, even if the ambient temperature of the semiconductor fluctuates, the clock margin can be stabilized, the stability of the entire circuit and the operating speed can be secured, and the reliability can be improved.

Further, in the invention according to claim 3, the voltage detecting means detects the applied voltage of the semiconductor circuit and sends out a voltage detection signal corresponding to the detection result, and the voltage comparing means causes the voltage detecting means. The voltage detection signal transmitted from the predetermined reference voltage signal is compared to detect a difference including the magnitude relationship between the two signals, and the voltage difference signal is transmitted corresponding to the detection result, and the clock frequency control means, Based on the voltage difference signal sent from the voltage comparison means, when the voltage detection signal is larger than the reference voltage signal, the clock frequency of the clock signal is increased so as to shorten the generation period of the clock signal,
When the voltage detection signal is smaller than the reference voltage signal, the clock frequency is lowered, so the clock margin is stabilized even if the voltage applied to the semiconductor fluctuates, and the stability and operating speed of the entire circuit are secured, thus ensuring reliability. It is possible to improve the sex.

Further, in the invention according to claim 4, the cooling temperature control means makes the voltage detection signal larger than the reference voltage signal based on the voltage difference signal sent from the voltage comparison means according to claim 3. At this time, the cooling temperature is raised while cooling the semiconductor circuit so as to lengthen the maximum propagation time of the digital signal, and the cooling temperature is lowered when the voltage detection signal is smaller than the reference voltage signal. Similar to the action corresponding to, the clock margin can be stabilized even if the voltage applied to the semiconductor fluctuates, the stability of the entire circuit and the operation speed can be secured, and thus the reliability can be improved.

Further, in the invention according to claim 5, the frequency detecting means detects the clock frequency which is the reciprocal of the generation period of the clock signal, and outputs the frequency detection signal corresponding to the detection result to compare the frequencies. The means compares the frequency detection signal sent from the frequency detection means with a predetermined reference frequency signal to detect a difference including a magnitude relationship between the two signals, and sends a frequency difference signal corresponding to the detection result, The applied voltage control means, based on the frequency difference signal sent from the frequency comparison means, changes the applied voltage of the semiconductor circuit so as to shorten the maximum propagation time of the digital signal when the frequency detection signal is larger than the reference frequency signal. When the clock frequency detection signal is increased and the clock frequency detection signal is smaller than the reference frequency signal, the applied voltage is reduced. Jin stabilize and to ensure stability and operation speed of the entire circuit, with, it is possible to improve the reliability.

Further, in the invention according to claim 6, the cooling temperature control means makes the frequency detection signal larger than the reference frequency signal based on the frequency difference signal sent from the frequency comparison means according to claim 5. At this time, the cooling temperature is lowered while cooling the semiconductor circuit so as to shorten the maximum propagation time of the digital signal, and the cooling temperature is raised when the frequency detection signal is smaller than the reference frequency signal. Similar to the action corresponding to (1), it is possible to stabilize the clock margin even when the clock frequency of the semiconductor circuit fluctuates, secure the stability of the entire circuit and the operating speed, and thus improve the reliability.

Further, in the invention according to claim 7, the applied voltage control means controls the applied voltage so as to eliminate the difference based on the difference between the applied voltage of the semiconductor circuit and a predetermined voltage target value. The temperature control means controls the temperature of the semiconductor element so as to eliminate this difference based on the difference between the temperature of the semiconductor element of the semiconductor circuit and a predetermined temperature target value, and the frequency control means generates the clock signal. Based on the difference between the clock frequency, which is the reciprocal of the cycle, and the predetermined frequency target value, the clock frequency is controlled so as to eliminate this difference, and the target value changing means applies the applied voltage, the temperature of the semiconductor element,
When at least one of the three elements of the clock frequency fluctuates beyond the reference value, the target values corresponding to the remaining elements are changed and given to the corresponding control means so as to stabilize the clock margin. Therefore, even if the applied voltage of the semiconductor circuit, the temperature of the semiconductor element, or the clock frequency changes, the clock margin can be stabilized, the stability and operation speed of the entire circuit can be secured, and the reliability can be further improved. .

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing a schematic configuration of a clock margin control device according to a first embodiment of the present invention and a clock synchronous semiconductor circuit to which the same is applied. This clock margin control device includes a temperature detection unit 1, a reference temperature holding unit 2, a temperature comparison unit 3, a voltage detection unit 4, a reference voltage holding unit 5, a voltage comparison unit 6, and a clock frequency control unit 7. The control unit 7 is mounted on a clock-synchronous semiconductor circuit 8.

Here, the temperature detection unit 1 has a function of detecting the junction temperature of the semiconductor in the semiconductor circuit 8 and giving a temperature detection signal to the temperature comparison unit 3, and for example, a thermocouple or the like can be used. .

The reference temperature holding unit 2 has a function of giving a reference temperature signal corresponding to the standard temperature during operation of the semiconductor circuit 8 to the temperature comparison unit 3. For example, when the reference temperature signal is a voltage value, the power supply voltage It is possible to use a voltage dividing resistor or the like that divides the voltage to create a reference temperature signal.

The temperature comparison unit 3 compares the temperature detection signal received from the temperature detection unit 1 with the reference temperature signal received from the reference temperature holding unit 2 and, based on the difference between the two signals, determines the junction temperature from the standard temperature. It has a function of giving a temperature difference signal indicating whether it is high or low to the clock frequency control unit 7, and for example, an operational amplifier circuit can be used.

The voltage detector 4 has a function of detecting the voltage applied to the semiconductor used in the semiconductor circuit 8 and supplying a voltage detection signal to the voltage comparator 6. Reference voltage holding unit 5
Has a function of giving a reference voltage signal corresponding to the standard voltage during operation of the semiconductor circuit 8 to the voltage comparison unit 6, and, for example, a power supply voltage dividing resistor or the like can be used.

The voltage comparison unit 6 compares the voltage detection signal received from the voltage detection unit 4 with the reference voltage signal received from the reference voltage holding unit 2, and determines the applied voltage from the reference voltage based on the difference between the two signals. It has a function of giving a voltage difference signal indicating whether it is high or low to the clock frequency control unit 7, and for example, an operational amplifier can be used.

The clock frequency control unit 7 includes a temperature comparison unit 3
Has a function of controlling the clock frequency of the semiconductor circuit 7 on the basis of the temperature difference signal received from the voltage difference signal and the voltage difference signal received from the voltage comparison unit 6, and for example, a PLL circuit can be used.

Next, the operation of such a clock margin control device will be described. The temperature detection unit 1 detects the junction temperature of the semiconductor in the semiconductor circuit 8 and gives a temperature detection signal to the temperature comparison unit 3.

The reference temperature holding unit 2 gives a reference temperature signal to the temperature comparison unit 3. The temperature comparison unit 3 receives the temperature detection signal,
The temperature difference signal is compared with the reference temperature signal, and the temperature difference signal is given to the clock frequency control unit 7 based on the difference between the two signals.

On the other hand, in parallel with this, the voltage detector 4 detects the voltage applied to the semiconductor element used in the semiconductor circuit 8 and supplies a voltage detection signal to the voltage comparator 6. The reference voltage holding unit 5 gives a reference voltage signal to the voltage comparison unit 6.

The voltage comparison unit 6 compares the voltage detection signal with the reference voltage signal, and supplies the voltage difference signal to the clock frequency control unit 7 based on the difference between the two signals. The clock frequency control unit 7 controls the clock frequency of the semiconductor circuit 8 based on the temperature difference signal received from the temperature comparison unit 3 and the voltage difference signal received from the voltage comparison unit 6.

That is, the clock frequency controller 7 lowers the clock frequency in proportion to the junction temperature when the temperature difference signal is large, and raises the clock frequency when the temperature difference signal is small.

Further, the clock frequency control section 7 increases the clock frequency in proportion to the applied voltage when the voltage difference signal is large, and lowers the clock frequency when the voltage difference signal is small.

As a result, it is possible to improve the performance by reducing the extra clock margin and increase the clock frequency, and improve the reliability by stabilizing the clock margin.

As described above, according to the first embodiment, the temperature detector 1 detects the temperature of the semiconductor element of the semiconductor circuit 8 and sends a temperature detection signal corresponding to the detection result, The comparison unit 3 compares the temperature detection signal with a predetermined reference temperature signal and outputs a temperature difference signal including the magnitude relationship between the two signals, and the clock frequency control unit 7 detects the temperature based on the temperature difference signal. When the signal is larger than the reference temperature signal, the clock frequency of the clock signal is lowered so as to lengthen the generation period of the clock signal, and when the temperature detection signal is smaller than the reference temperature signal, the clock frequency is raised. Even if the ambient temperature of the semiconductor fluctuates, the clock margin can be stabilized, the stability and operation speed of the entire circuit can be secured, and the reliability can be improved.

The voltage detector 4 detects the voltage applied to the semiconductor circuit 8 and sends out a voltage detection signal.
Compares the voltage detection signal with a predetermined reference voltage signal and sends out a voltage difference signal including the magnitude relationship between the two signals, and the clock frequency control unit 7 determines that the voltage detection signal is the reference voltage based on the voltage difference signal. When the voltage is larger than the signal, the clock frequency of the clock signal is increased so as to shorten the generation period of the clock signal, and when the voltage detection signal is smaller than the reference voltage signal, the clock frequency is decreased. It is possible to stabilize the clock margin even when fluctuates and to secure the stability and operating speed of the entire circuit, thereby improving the reliability. (Second Embodiment) Next, a clock margin control device according to a second embodiment of the present invention will be described. FIG. 2 is a block diagram showing a schematic configuration of this clock margin control device and a clock-synchronous semiconductor circuit to which the clock margin control device is applied. The same parts as those in FIG. Subscripts are attached and detailed explanations thereof are omitted, and only different parts are described here.

That is, the device of this embodiment is a modification of the first embodiment, and specifically, as shown in FIG. 2, the voltage detection unit 4, the reference voltage holding unit 5, and the voltage comparison unit 6 are provided. In place of the clock frequency control unit 7, the frequency detection unit 1
1, a reference frequency holding unit 12, a frequency comparison unit 13, and an applied voltage control unit 14.

Here, the frequency detection section 11 has a function of detecting the clock frequency during operation of the semiconductor circuit 8 and giving a frequency detection signal to the frequency comparison section 13. The reference frequency holding unit 12 has a function of giving a reference frequency signal corresponding to the standard clock frequency of the semiconductor circuit 8 to the frequency comparison unit 13.

The frequency comparison unit 13 compares the frequency detection signal received from the frequency detection unit 11 with the reference frequency signal received from the reference frequency holding unit 12, and operates from the standard clock frequency based on the difference between the two signals. Has a function of giving the applied voltage control unit 14 a frequency difference signal indicating how high or low the clock frequency is.

The temperature comparison section 3a compares the temperature detection signal received from the temperature detection section with the reference temperature signal received from the reference temperature holding section, and outputs the temperature difference signal to the applied voltage control section 14 based on the difference between the two signals. It has a function to give.

The applied voltage control unit 14 includes a frequency comparison unit 13
It has a function of controlling the voltage applied to the semiconductor circuit 8 based on the frequency difference signal received from the circuit and the voltage difference signal received from the temperature comparison unit 3a.

Next, the operation of such a clock margin control device will be described. The frequency detection unit 11 detects a clock frequency during operation of the semiconductor circuit 8 and supplies a frequency detection signal to the frequency comparison unit 13.

The reference frequency holding unit 12 supplies the reference frequency signal corresponding to the standard clock frequency of the semiconductor circuit 8 to the frequency comparison unit 13. The frequency comparison unit 13 compares the frequency detection signal with the reference frequency signal, and gives a frequency difference signal to the applied voltage control unit 14 based on the difference between the two signals.

On the other hand, in parallel with this, the temperature comparison unit 3a
The temperature detection signal received from the temperature detection unit 1 is compared with the reference temperature signal received from the reference temperature holding unit 2, and the temperature difference signal is given to the applied voltage control unit 14 based on the difference between the two signals.

The applied voltage control unit 14 includes a frequency comparison unit 13
The voltage applied to the semiconductor circuit 8 is controlled on the basis of the frequency difference signal received from and the voltage difference signal received from the temperature comparison unit 3a.

That is, the applied voltage controller 14 increases the applied voltage in proportion to the operating clock frequency when the frequency difference signal is large, and decreases the applied voltage when the frequency difference signal is small. As a result, even if the clock frequency fluctuates, the reduction of the clock margin can be prevented.

Further, the clock frequency controller 14 increases the applied voltage in proportion to the ambient temperature when the temperature difference signal is large, and lowers the applied voltage when the temperature difference signal is small. As a result, the clock margin can be kept constant even if the ambient temperature changes.

As described above, according to the second embodiment, the applied voltage control section 14 determines, based on the temperature difference signal,
When the temperature detection signal is larger than the reference temperature signal, the applied voltage of the semiconductor circuit 8 is increased so as to shorten the maximum propagation time of the digital signal, and when the temperature detection signal is smaller than the reference temperature signal, the applied voltage is increased. Since it is lowered, as in the first embodiment, the clock margin can be stabilized even if the ambient temperature of the semiconductor fluctuates, the stability and operation speed of the entire circuit can be secured, and the reliability can be improved. .

Further, the frequency detection unit 11 detects the clock frequency which is the reciprocal of the generation period of the clock signal and sends out the frequency detection signal, and the frequency comparison unit 13 outputs the frequency detection signal and the predetermined reference frequency signal. In comparison, the frequency difference signal including the magnitude relationship between the two signals is transmitted, and the applied voltage control unit 1
4, when the frequency detection signal is larger than the reference frequency signal based on the frequency difference signal, the voltage applied to the semiconductor circuit is increased so as to shorten the maximum propagation time of the digital signal, and the clock frequency detection signal is When the voltage is smaller than the signal, the applied voltage is lowered, so that the clock margin is stabilized even if the clock frequency of the semiconductor circuit 8 fluctuates, the stability and operating speed of the entire circuit are secured, and thus the reliability is improved. be able to. (Third Embodiment) Next, a clock margin control device according to a third embodiment of the present invention will be described. FIG. 3 is a block diagram showing a schematic configuration of the clock margin control device and a clock synchronous semiconductor circuit to which the clock margin control device is applied. The same parts as those in FIGS. Is affixed with a subscript and its detailed description is omitted, and only different parts will be described here.

That is, the apparatus of the present embodiment is a modified configuration of the first embodiment, and specifically, as shown in FIG. 3, the temperature detecting unit 1, the reference temperature holding unit 2, and the temperature comparing unit 3 are provided. In place of the clock frequency control unit 7, the frequency detection unit 1
1, a reference frequency holding unit 12, a frequency comparison unit 13a, and a cooling temperature control unit 21.

Here, the frequency comparison unit 13a compares the frequency detection signal received from the frequency detection unit 11 with the reference frequency signal received from the reference frequency holding unit 12, and based on the difference between the two signals, the standard clock frequency. To a cooling temperature control unit 21 with a frequency difference signal indicating how high or low the operating clock frequency is.

The voltage comparison unit 6a compares the voltage detection signal received from the voltage detection unit 4 with the reference voltage signal received from the reference voltage holding unit 5, and the applied voltage from the reference voltage is determined based on the difference between the two signals. It has a function of giving a voltage difference signal indicating whether the voltage is high or low to the cooling temperature control unit 21.

The cooling temperature control unit 21 includes a frequency comparison unit 13
It has a function of controlling the cooling temperature of the semiconductor circuit 21 while cooling the semiconductor circuit 21 based on the frequency difference signal received from a and the voltage difference signal received from the voltage comparison unit 6a. For example, a Peltier element or a cooling fin can be used. ing.

Next, the operation of such a clock margin control device will be described. The frequency comparison unit 13a compares the frequency detection signal received from the frequency detection unit 11 with the reference frequency signal received from the reference frequency holding unit 12, and gives a frequency difference signal to the cooling temperature control unit 21 based on the difference between the two signals. .

The voltage comparison unit 6a compares the voltage detection signal received from the voltage detection unit 4 and the reference voltage signal received from the reference voltage holding unit 5, and based on the difference between the two signals, the voltage difference signal is given to the cooling temperature control unit. Give to 21.

The cooling temperature control unit 21 controls the cooling temperature of the semiconductor circuit 8 based on the frequency difference signal and the voltage difference signal. That is, the cooling temperature control unit 21 controls the cooling temperature to a high value when the frequency difference signal is large in proportion to the operating clock frequency to weaken the degree of cooling, and when the frequency difference signal is small, the cooling temperature is controlled. Control to a low value to increase the degree of cooling.

Further, the cooling temperature control section 21 controls the cooling temperature to a high value when the voltage difference signal is large in proportion to the applied voltage to weaken the degree of cooling, and when the voltage difference signal is small, the cooling temperature is adjusted. Control to a low value to increase the degree of cooling.

As a result, the clock margin can be stabilized and the reliability can be improved. As described above, according to the third embodiment, when the cooling temperature control unit 21 determines that the frequency detection signal is larger than the reference frequency signal based on the frequency difference signal sent from the frequency comparison unit 13a, it outputs a digital signal. Since the cooling temperature is lowered while cooling the semiconductor circuit 8 so as to shorten the maximum propagation time of the signal, and the cooling temperature is raised when the frequency detection signal is smaller than the reference frequency signal, the second embodiment Similarly, even if the clock frequency of the semiconductor circuit fluctuates, the clock margin can be stabilized, the stability of the entire circuit and the operation speed can be ensured, and the reliability can be improved.

Further, the cooling temperature control unit 21 lengthens the maximum propagation time of the digital signal based on the voltage difference signal sent from the voltage comparison unit 6a when the voltage detection signal is larger than the reference voltage signal. While cooling the semiconductor circuit 8, the cooling temperature is raised, and when the voltage detection signal is smaller than the reference voltage signal, the cooling temperature is lowered. Therefore, as in the first embodiment, the voltage applied to the semiconductor is Even if it fluctuates, the clock margin can be stabilized, the stability of the entire circuit and the operating speed can be secured, and the reliability can be improved. (Fourth Embodiment) Next, a clock margin control device according to a fourth embodiment of the present invention will be described. FIG. 4 is a block diagram showing a schematic configuration of this clock margin control device. The clock margin control device includes a control target setting unit 60 that is individually connected to the applied voltage control unit 30, the cooling temperature control unit 40, and the clock frequency control unit 50.
It has.

Here, the applied voltage control unit 30 has a voltage detection unit 31, a voltage comparison unit 32 and a voltage change unit 33, and based on the voltage target value received from the control target setting unit 60, the applied voltage of the semiconductor circuit. Has the function of controlling.

The voltage detection unit 31 detects the voltage applied to the semiconductor circuit from the voltage change unit 33 and gives a voltage detection signal to the control target setting unit 60 and the voltage comparison unit 32. The voltage comparison unit 32 compares the voltage detection signal received from the voltage detection unit 31 and the voltage target value received from the control target setting unit 60, and outputs the voltage difference signal indicating the difference between the two signals to the voltage change unit 3.
3

The voltage changing section 33 has a function of changing the voltage applied to the semiconductor circuit so that the voltage difference signal received from the voltage comparing section 32 becomes zero. Cooling temperature controller 4
0 has a temperature detection unit 41, a temperature comparison unit 42, and a temperature change unit 43, and has a function of controlling the ambient temperature of the semiconductor circuit based on the temperature target value received from the control target setting unit 60.

The temperature detecting section 41 detects the ambient temperature of the semiconductor circuit from the temperature changing section 33 and gives a temperature detection signal to the control target setting section 60 and the temperature comparing section 42. The temperature comparison unit 42 compares the temperature detection signal received from the temperature detection unit 41 with the temperature target value received from the control target setting unit 60, and outputs the temperature difference signal indicating the difference between the two signals to the temperature change unit 4.
3

The temperature changing section 43 has a function of changing the ambient temperature of the semiconductor circuit so that the temperature difference signal received from the temperature comparing section 42 becomes zero. The clock frequency control unit 50 has a frequency detection unit 51, a frequency comparison unit 52, and a frequency change unit 53, and has a function of controlling the clock frequency of the semiconductor circuit based on the frequency target value received from the control target setting unit 60. .

The frequency detecting section 51 detects the clock frequency of the semiconductor circuit from the frequency changing section 53 and supplies the frequency detection signal to the control target setting section 60 and the frequency comparing section 52.

The frequency comparison unit 52 compares the frequency detection signal received from the frequency detection unit 51 with the frequency target value received from the control target setting unit 60, and outputs the frequency difference signal indicating the difference between the two signals to the frequency changing unit 53. To give.

The frequency changing section 53 has a function of changing the clock frequency of the semiconductor circuit so that the frequency difference signal received from the frequency comparing section 52 becomes zero. The control target setting unit 60 individually controls the voltage comparison unit 32, the temperature comparison unit 42, and the frequency comparison unit 52 based on the detection signals individually received from the voltage detection unit 31, the temperature detection unit 41, and the frequency detection unit 51. It has a function to give each target value.

In addition, the control target setting section 60 controls the applied voltage,
When the difference between the detection signal of at least one of the three detection signals of the ambient temperature and the clock frequency (voltage detection signal, temperature detection signal, frequency detection signal) and its target value is large, the clock margin It has the function of changing the target values of the remaining elements to stabilize them and giving them to the comparison section. It is preferable to change the setting of the target value according to the priority order of the ambient temperature, the applied voltage, and the clock frequency from the viewpoint of stabilizing the operation of the circuit. Whether or not the difference is large can be determined by comparison with a predetermined reference value.

Further, when the element having a large difference between the detection signal and the target value functions normally and the difference becomes small, the control target setting section 60 returns the target values of the remaining elements to the standard. It has the function of changing the setting and giving it to the comparison section.

Next, the operation of such a clock margin control device will be described. The applied voltage control unit 30, the cooling temperature control unit 40, and the clock frequency control unit 50, based on the target values individually given from the control target setting unit 60,
It controls the corresponding elements among the applied voltage, ambient temperature and clock frequency.

At this time, for example, it is assumed that the ambient temperature of the semiconductor element rises so much that the cooling temperature control section 40 cannot control it. The control target setting unit 60 includes a cooling temperature control unit 40.
It is detected that the difference between the temperature detection signal and the temperature target value is large based on the temperature detection signal received from the controller and the temperature target value given by itself, and the clock margin is increased corresponding to the difference. As described above, the voltage target value is increased and applied to the voltage comparison unit 32 in the applied voltage control unit 30, and the frequency target value is increased and the clock frequency control unit 50.
It is given to the frequency comparison unit 525 inside.

As a result, the clock margin can be stabilized. Further, when the difference between the temperature detection signal and the temperature target value returns to a small value, the control target setting unit 60 lowers the voltage target value toward the standard so as to reduce the clock margin corresponding to this difference. The voltage target value is given to the voltage comparison section 32 in the applied voltage control section 30 and the frequency target value is lowered toward the standard and given to the frequency comparison section 52 in the clock frequency control section 50.

As a result, the semiconductor circuit can be returned to the normal operating state while stabilizing the clock margin. As described above, according to the fourth embodiment, the applied voltage controller 30 controls the applied voltage based on the difference between the applied voltage of the semiconductor circuit and the predetermined voltage target value so as to eliminate this difference. Then, the cooling temperature control section 40 controls the temperature of the semiconductor element based on the difference between the temperature of the semiconductor element of the semiconductor circuit and the predetermined temperature target value so as to eliminate this difference, and the clock frequency control section 50 , The clock frequency is controlled so as to eliminate this difference based on the difference between the clock frequency, which is the reciprocal of the clock signal generation period, and the predetermined frequency target value, and the control target setting unit 60 controls the applied voltage, the semiconductor element Change the target value corresponding to the remaining elements to stabilize the clock margin when at least one of the three elements of temperature and clock frequency fluctuates beyond the reference value. Appropriate because it gives to the control unit Te, the applied voltage of the semiconductor circuit, the temperature of the semiconductor element,
Even if any of the clock frequencies changes, the clock margin can be stabilized, the stability and operation speed of the entire circuit can be secured, and the reliability can be further improved. (Other Embodiments) In the above fourth embodiment,
The case has been described in which the fluctuating element is the ambient temperature and the remaining controlled elements are the applied voltage and the clock frequency. However, even if the combination of the elements is changed, the present invention is similarly implemented and the same effect is obtained. be able to. In addition, the present invention can be modified in various ways without departing from the scope of the invention.

[0078]

As described above, according to the invention of claim 1, the temperature detecting means detects the temperature of the semiconductor element of the semiconductor circuit, and sends a temperature detection signal in response to the detection result. The comparing means compares the temperature detection signal sent from the temperature detecting means with a predetermined reference temperature signal to detect a difference including a magnitude relationship between the two signals, and sends a temperature difference signal corresponding to the detection result. The clock frequency control means, based on the temperature difference signal sent from the temperature comparison means, adjusts the clock frequency of the clock signal so as to lengthen the generation cycle of the clock signal when the temperature detection signal is larger than the reference temperature signal. When the temperature detection signal is lower than the reference temperature signal, the clock frequency is increased, which stabilizes the clock margin even if the ambient temperature of the semiconductor fluctuates, and stabilizes and stabilizes the entire circuit. Ensuring speed, it has been possible to provide a clock margin control device capable of improving reliability.

Further, according to the invention of claim 2, the applied voltage control means determines that the temperature detection signal is larger than the reference temperature signal based on the temperature difference signal sent from the temperature comparison means of claim 1. , The applied voltage of the semiconductor circuit is increased so as to shorten the maximum propagation time of the digital signal, and the applied voltage is decreased when the temperature detection signal is smaller than the reference temperature signal. It is possible to provide a clock margin control device that stabilizes the clock margin even when the ambient temperature fluctuates, secures stability and operating speed of the entire circuit, and thus can improve reliability.

Further, according to the invention of claim 3, the voltage detecting means detects the applied voltage of the semiconductor circuit, sends out the voltage detection signal corresponding to the detection result, and the voltage comparing means,
The voltage detection signal sent from the voltage detection means is compared with a predetermined reference voltage signal to detect a difference including the magnitude relationship between the two signals, and a voltage difference signal is sent corresponding to the detection result,
The clock frequency control means raises the clock frequency of the clock signal so as to shorten the generation cycle of the clock signal when the voltage detection signal is larger than the reference voltage signal based on the voltage difference signal sent from the voltage comparison means. When the voltage detection signal is smaller than the reference voltage signal, the clock frequency is lowered, so that the clock margin is stabilized even if the voltage applied to the semiconductor fluctuates, and the stability and operating speed of the entire circuit are secured. It is possible to provide a clock margin control device that can improve reliability.

According to the invention of claim 4, the cooling temperature control means determines that the voltage detection signal is larger than the reference voltage signal based on the voltage difference signal sent from the voltage comparison means of claim 3. , The cooling temperature is raised while cooling the semiconductor circuit so as to lengthen the maximum propagation time of the digital signal, and when the voltage detection signal is smaller than the reference voltage signal, the cooling temperature is lowered. In addition, it is possible to provide a clock margin control device that stabilizes the clock margin even when the voltage applied to the semiconductor fluctuates, ensures the stability and operating speed of the entire circuit, and thus improves the reliability.

Further, according to the invention of claim 5, the frequency detecting means detects the clock frequency which is the reciprocal of the generation period of the clock signal, and outputs the frequency detection signal corresponding to the detection result to compare the frequencies. The means compares the frequency detection signal sent from the frequency detection means with a predetermined reference frequency signal to detect a difference including a magnitude relationship between the two signals, and sends a frequency difference signal corresponding to the detection result, The applied voltage control means, based on the frequency difference signal sent from the frequency comparison means, changes the applied voltage of the semiconductor circuit so as to shorten the maximum propagation time of the digital signal when the frequency detection signal is larger than the reference frequency signal. When the clock frequency detection signal is raised and the applied voltage is lowered when the clock frequency detection signal is smaller than the reference frequency signal, even if the clock frequency of the semiconductor circuit fluctuates Down to stabilize the to ensure stability and operation speed of the entire circuit, has been possible to provide a clock margin control device capable of improving reliability.

According to the invention of claim 6, the cooling temperature control means determines that the frequency detection signal is larger than the reference frequency signal based on the frequency difference signal sent from the frequency comparison means of claim 5. , The cooling temperature is lowered while cooling the semiconductor circuit so as to shorten the maximum propagation time of the digital signal, and the cooling temperature is raised when the frequency detection signal is smaller than the reference frequency signal. Further, it is possible to provide a clock margin control device that stabilizes the clock margin even when the clock frequency of the semiconductor circuit fluctuates, secures the stability and operating speed of the entire circuit, and can improve the reliability.

Further, according to the invention of claim 7, the applied voltage control means controls the applied voltage so as to eliminate this difference based on the difference between the applied voltage of the semiconductor circuit and the predetermined voltage target value. The temperature control means controls the temperature of the semiconductor element so as to eliminate this difference based on the difference between the temperature of the semiconductor element of the semiconductor circuit and a predetermined temperature target value, and the frequency control means generates the clock signal. Based on the difference between the clock frequency, which is the reciprocal of the cycle, and the predetermined frequency target value, the clock frequency is controlled so as to eliminate this difference, and the target value changing means applies the applied voltage, the temperature of the semiconductor element,
When at least one of the three elements of the clock frequency fluctuates beyond the reference value, the target values corresponding to the remaining elements are changed and given to the corresponding control means so as to stabilize the clock margin. Therefore, the clock margin control stabilizes the clock margin even when the applied voltage of the semiconductor circuit, the temperature of the semiconductor element, and the clock frequency fluctuates, thereby ensuring the stability and operating speed of the entire circuit and further improving the reliability. A device can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a clock margin control device according to a first embodiment of the present invention and a clock synchronous semiconductor circuit to which the clock margin control device is applied.

FIG. 2 is a block diagram showing a schematic configuration of a clock margin control device according to a second embodiment of the present invention and a clock synchronous semiconductor circuit to which the same is applied.

FIG. 3 is a block diagram showing a schematic configuration of a clock margin control device according to a third embodiment of the present invention and a clock synchronous semiconductor circuit to which the same is applied.

FIG. 4 is a block diagram showing a schematic configuration of a clock margin control device according to a fourth embodiment of the present invention.

[Explanation of symbols]

 1, 41 ... Temperature detection unit, 2 ... Reference temperature holding unit, 3, 3a, 42 ... Temperature comparison unit, 4, 31 ... Voltage detection unit, 5 ... Reference voltage holding unit, 6, 6a, 32 ... Voltage comparison unit, 7, 50 ... Clock frequency control unit, 8 ... Semiconductor circuit, 11, 51 ... Frequency detection unit, 12 ... Reference frequency holding unit, 13, 13a, 52 ... Frequency comparison unit, 14, 30 ... Applied voltage control unit, 21, 40 ... Cooling temperature control unit, 33 ... Voltage changing unit, 43 ... Temperature changing unit, 53 ... Frequency changing unit, 60 ... Control target setting unit.

Claims (7)

[Claims] 1. A clock margin control device for controlling a clock margin, which is a difference between a generation period of a clock signal and a maximum propagation time of a digital signal in a clock synchronous semiconductor circuit, to a constant value. Temperature detection means for detecting the temperature of the semiconductor element and sending out a temperature detection signal corresponding to the detection result, and comparing both the temperature detection signal sent from the temperature detection means with a predetermined reference temperature signal Of the temperature detection signal based on the temperature difference signal sent from the temperature comparison means and the temperature difference signal sent from the temperature comparison means. When the temperature detection signal is larger than the temperature signal, the clock frequency of the clock signal is lowered so as to lengthen the generation period of the clock signal, and the temperature detection signal is A clock margin control device comprising: a clock frequency control means for increasing the clock frequency when it is smaller than a reference temperature signal. 2. The clock margin control device according to claim 1, wherein the temperature detection signal is the reference temperature signal based on a temperature difference signal sent from the temperature comparison means instead of the clock frequency control means. Is larger than the reference temperature signal, the applied voltage of the semiconductor circuit is increased so as to shorten the maximum propagation time of the digital signal, and when the temperature detection signal is smaller than the reference temperature signal, the applied voltage is decreased. A clock margin control device comprising a voltage control means. 3. A clock margin control device for controlling a clock margin, which is a difference between a generation period of a clock signal and a maximum propagation time of a digital signal in a clock-synchronized semiconductor circuit, to be constant, the semiconductor circuit comprising: The voltage detection means that detects the applied voltage and sends out a voltage detection signal corresponding to the detection result, and the voltage detection signal sent from the voltage detection means and a predetermined reference voltage signal are compared to determine the magnitude of both signals. A voltage comparison unit that detects a difference including a relationship and sends a voltage difference signal corresponding to the detection result, and the voltage detection signal is the reference voltage signal based on the voltage difference signal sent from the voltage comparison unit. Is higher than the reference voltage, the clock frequency of the clock signal is increased so that the generation cycle of the clock signal is shortened. And a clock frequency control means for lowering the clock frequency when the signal is smaller than the signal. 4. The clock margin control device according to claim 3, wherein the voltage detection signal is based on a voltage difference signal sent from the voltage comparison means instead of the clock frequency control means. When the voltage detection signal is smaller than the reference voltage signal, the cooling temperature is increased while cooling the semiconductor circuit so as to lengthen the maximum propagation time of the digital signal when the voltage detection signal is smaller than the reference voltage signal. A clock margin control device comprising a cooling temperature control means for reducing the temperature. 5. A clock margin control device for controlling a clock margin, which is a difference between a generation period of a clock signal and a maximum propagation time of a digital signal in a clock synchronous semiconductor circuit, to a constant value, the clock margin control device comprising: A frequency detection unit that detects a clock frequency that is the reciprocal of the generation period and sends a frequency detection signal corresponding to the detection result, and compares the frequency detection signal sent from the frequency detection unit with a predetermined reference frequency signal. A frequency comparison means for transmitting a frequency difference signal corresponding to the detection result and a frequency difference signal transmitted from the frequency comparison means. Application of the semiconductor circuit to shorten the maximum propagation time of the digital signal when the signal is greater than the reference frequency signal. A clock margin control device comprising: an applied voltage control means for increasing the voltage and for decreasing the applied voltage when the clock frequency detection signal is smaller than the reference frequency signal. 6. The clock margin control device according to claim 5, wherein the frequency detection signal is the reference frequency signal based on a frequency difference signal sent from the frequency comparison means instead of the applied voltage control means. When the frequency detection signal is smaller than the reference frequency signal, the cooling temperature is lowered while cooling the semiconductor circuit so as to shorten the maximum propagation time of the digital signal. A clock margin control device comprising a cooling temperature control means for increasing the temperature. 7. A clock margin control device for controlling a clock margin, which is a difference between a generation period of a clock signal and a maximum propagation time of a digital signal in a clock-synchronized semiconductor circuit, to be constant. Based on the difference between the applied voltage and the predetermined voltage target value, the applied voltage control means for controlling the applied voltage so as to eliminate this difference, the temperature of the semiconductor element of the semiconductor circuit and the predetermined temperature target value Based on the difference, based on the difference between the temperature control means for controlling the temperature of the semiconductor element so as to eliminate this difference, the clock frequency is a reciprocal of the generation cycle of the clock signal and a predetermined frequency target value, Frequency control means for controlling the clock frequency so as to eliminate this difference, the applied voltage, the temperature of the semiconductor element, the clock frequency When at least one element of the three elements of No. 3 changes above the reference value, the target value corresponding to the remaining elements is changed and given to the corresponding control means so as to stabilize the clock margin. A clock margin control device comprising a target value changing means.