JPH09207389A - Full-color image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve color reproduction which looks faithful, by dispersing an error to pixels around its pixel when an image based on image data is printed by means of a recording part whose gradation expression is inferior to full-color image data to be input. SOLUTION: Full-color image data to be input is RGB color indication signals read by a color scanner, and they are converted into L*a*b* color indication data, which is uniform yardstick to the human perception of printed colors. The color data after the conversion is processed for each pixel in such a way that an error value based on a difference between color data which is considered to be printed originally and color data which is actually printed by a recording part 13 is so distributed as to be dispersed to pixels around it at specific distribution ratio. Thereafter YMCK data for printing is output to the recording part 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a full-color image processing device for color copying, color printers, color facsimiles and the like.

[0002]

2. Description of the Related Art Input signals of a color copy or color printer are RGB (red, green, blue) type signals, and YMCK (yellow, magenta, cyan, etc.) are used for color printing.
Conversion to black) signals is required. Traditionally,
If both input device and output device are 8-bit signal system, R
From (red), G (green), and B (blue) signals, Y (yellow), M (magenta) C (cyan), and K (black)
There are linear masking method, non-linear masking method, table reference interpolation method and the like as the color conversion method for obtaining the ink control amount of the above.

Generally, for correct color reproduction, three color signals R, G, B of an input system read by a color scanner are used.
From the density value of the color printer, the area ratio signal, Y, M,
It suffices that three values of C or four values of Y, M, C and K can be output. To achieve this, the input space (R,
G, B) to output space (Y, M, C) or (Y, M,
A table of three-dimensional input, three-dimensional output or four-dimensional output to C, K) may be created. However, in the 8-bit color signal system, the total number of input colors (R, G, B) is 256 × 256 × 256 =
There are a large number of 16,777,216, and all three
Storing the dimensional color conversion values (Y, M, C) requires a memory of 16 Mbytes per color and a memory of 48 Mbytes for three colors, which is difficult to realize. Therefore, for color conversion, there is a method of obtaining only on discrete grid points and applying an interpolation method to this. According to the document (Journal of the Institute of Image Electronics Engineers of Japan, Vol. 22, No. 4, “High-speed multimedia-compatible processor using prism interpolation method”), (a) cubic interpolation method, (b) tetrahedral interpolation method, (c) pyramid interpolation method , (D) prism interpolation method, etc. have been proposed.

[0004]

The conventional full-color image processing apparatus as described above has the following problems to be solved. According to the conventional method, if the output side uses an 8-bit signal system, that is, an output device capable of expressing an image of 256 gradations, color reproduction and gradation are excellent.
An output device with 56 gradations is very expensive. on the other hand,
The input signal system is 8 bits, that is, 256 gradations, but 16
If you use an inexpensive output device with gradation (4 bits) or less,
There is a problem that color reproducibility and gradation are poor. That is,
Although the input signal system has 8 bits, that is, 256 gradations, for example, when the output device has the ability to represent only 16 gradations (4 bits), the above method can be used to output 4 bits from an 8-bit input space of 256 gradations. If color conversion is performed in the bit output space, some color reproduction is possible, but since the gradation is still 16 gradations (4 bits) representation, it becomes an unnatural image as an output image. .

Further, in general, the output device continuously prints without stopping the recording paper in the middle of recording. Therefore, when carrying out the above color conversion, all the input signals of R, G and B are temporarily transmitted before the printing is started. It is necessary to store it in the memory and then perform color conversion to output signals. This is because the printing speed and the calculation speed cannot be matched due to the complicated calculation. Therefore, it requires a huge memory capacity and is expensive. According to the present invention, even in an output device in which gradation expression is inferior to the input digital full-color image data, color reproducibility is maintained, gradation characteristics are not deteriorated, and the minimum necessary memory size is used. An object is to provide a full-color image processing device that expresses a full-color image.

[0006]

The present invention employs the following structure to solve the above problems. <Structure 1> An image based on the image data is printed by a recording unit that is inferior in gradation expression to the input full color image data, and the input full color image data is perceived by a human as a printed color. A color conversion unit for converting color data of a predetermined color system that is an even scale to
Focusing on each pixel forming the image, for each pixel,
An error diffusion unit that distributes an error value based on the difference between the color data to be originally printed and the color data actually printed by the recording unit so as to be diffused to peripheral pixels at a predetermined distribution ratio,
A YMCK conversion unit that converts the color data of a predetermined color system after the error diffusion processing into color data for printing of yellow (Y), magenta (M), cyan (C), and black (K), and And a recording unit that performs printing with color data for printing.

<Explanation> The full-color image data to be inputted is data for color expression in an arbitrary color space, and is, for example, an RGB color system signal read by a color scanner. The color data of a predetermined color system, which is a uniform scale for human perception of printed colors, is, for example, JIS, Z8.
The color data of the L * a * b * color system defined by 730. Converting to color data of a predetermined color system, which is an even scale for human perception of printed color, is to obtain color data indicating the value of the printable color expression area in the recording unit. Is.

For each pixel, an error value based on the difference between the color data to be originally printed and the color data actually printed by the recording unit is distributed so as to be diffused to peripheral pixels at a predetermined distribution ratio. This is because an image based on the image data is printed by the recording unit that is inferior in gradation expression to the input full-color image data, so that an error always occurs for each pixel. By diffusing this error to the pixels around the pixel, apparently faithful color reproduction can be performed.

<Structure 2> In Structure 1, the error diffusion unit is provided with a conversion unit for inputting the color data actually printed by the recording unit together with the output of the color conversion unit. <Explanation> As shown in FIG. 1, the color data that is actually printed by the recording unit 13 and that should be input to the error diffusion units 3, 4, and 5 is color data for three colors corresponding to YMC. . These are separate conversion units 10, 11, 12 respectively.
And is supplied to the error diffusion units 3, 4, and 5.
With such a configuration, the error is appropriately diffused to the peripheral pixels of each pixel, and printing with a good color tone is performed.

<Structure 3> In Structure 1 or 2, the color conversion unit converts the input full-color image data into L * a * b.
* Color system, L * u * v * color system, tristimulus values X, Y,
The color data is converted into color data of one of the Z color systems. <Explanation> Converting to any of the L * a * b * color system, the L * u * v * color system, and the tristimulus value X, Y, Z color system This is because it is suitable for conversion into yellow (Y), magenta (M), cyan (C), and black (K) color data for printing on a uniform scale with respect to the perception of printed colors.

<Structure 4> In Structure 1 or 2, the color conversion unit converts the input full-color image data of three primary colors of red (R), green (G), and blue (B) into L * a *.
b * color system, L * u * v * color system, tristimulus value X,
The color data is converted to color data of one of the Y and Z color systems. <Explanation> When the input full-color image data is of three primary colors of red (R), green (G), and blue (B), yellow (Y), magenta (M), and cyan ( When the color data for printing in C) and black (K) are to be converted, once the color data is converted into the color data of a predetermined color system, the configuration of the present invention functions particularly effectively.

<Structure 5> An image based on the image data is printed by a recording unit whose gradation expression is inferior to the input full color image data, and the input full color image data is L * a * b. * Color system and L * u *
v * color system and tristimulus values X, Y, and Z color system, the color data of one of the color systems is used. An error diffusion unit that distributes an error value based on the difference between the color data that should be printed originally and the color data that is actually printed by the recording unit so that it is diffused to peripheral pixels at a predetermined distribution ratio; A YMCK conversion unit that converts the color data of a predetermined color system to yellow (Y), magenta (M), cyan (C), and black (K) color data for printing, and a YMCK conversion unit for this printing. A recording unit that prints based on color data.

<Explanation> The full-color image data to be input is selected from the L * a * b * color system, the L * u * v * color system, and the tristimulus value X, Y, Z color system. If the color data is composed of color data of any color system, these are color data of a predetermined color system which is a uniform scale for human's perception of the printed color. , A color conversion unit for converting color data of a predetermined color system is unnecessary. Therefore, the input signal can be immediately subjected to error diffusion processing to generate color data for printing.

<Structure 6> In Structure 1 or 2, the input full-color image data is a signal obtained by combining three types of N-bit color data, where N is a multiple of 8, and the recording section Y, M, each of N / 2 bits or less
C, K is used for printing by combining four types of color data, a memory for storing any two types of color data included in the full color image data, and the full color image data for the Y, M, A color conversion unit for converting into four types of color data for printing C and K is provided, and this color conversion unit, for each of the memories, stores any two types of color data included in the full color image data. After being stored in order by a predetermined unit amount, the color data for each one pixel and the color data for one pixel of the third type, which is subsequently input, are collectively received from each memory, and the color for printing is received. The data is converted into data, the color data for printing thus obtained is concatenated for each two types, and temporarily stored in the same storage area where the color data before conversion is read from each of the above memories, and all Of full-color image data After the treatment, the printing by the recording unit from each memory reads out the printing data.

<Explanation> When the calculation processing time for generating the print data is longer than the print processing next cancer, the calculation processing is performed in advance to generate the print data. A large-capacity memory is required to store this print data, and this storage uses a memory for storing any two types of color data included in the input full-color image data. Since the color signal of the input full-color image data has a data width that is at least twice as large as the color signal for printing, the memory area for storing this color data for two pixels can store exactly four pixels for printing color data. . As a result, the buffer memory on the input side can be minimized, and the memory for temporarily storing the printing color data can be saved. Each memory has a capacity capable of storing color data corresponding to a unit amount of pixels such as one line or one raster, which is one unit of print processing.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to specific examples. <Specific Example 1> FIG. 1 is a block diagram showing a configuration of a specific example 1 of the image processing apparatus. This specific example receives a digital full-color input signal system of R (red), G (green), and B (blue), each of which is composed of binary 8 bits, and receives binary 4 bits of Y, M, C, and K. An output signal system color printer, that is, a case of printing with 16 gradations of Y (yellow), M (magenta), C (cyan), and K (black) will be described as an example. Generally, when numerically expressing the color of an image on a display such as a scanner or CRT,
8 bits for each primary color of R, G, B, "0" to "25"
Allocating a numerical value of 5 "as the color intensity, and combining these numerical values of 3 bytes, approximately 16.7 million colors can be expressed. This is 1 byte which is the basic unit of calculation by the computer to express the intensity of each primary color. This is because it is easy to calculate and handle since it uses a printing device, and some recording devices can print 16.7 million colors by using 3 bytes for each of Y, M and C. Printing with 4096 colors of 16 gradations makes it possible to easily realize a recording apparatus with high reliability and low cost.

The feature of the first embodiment of the present invention is that even for a recording section with poor gradation expression, the gradation and color information of the recording section itself is used for error diffusion known as a pseudo halftone expression method. By combining with the processing, the color reproducibility and gradation of the input image signal can be maintained.

<Device Block Configuration> In FIG. 1, a control circuit 1 is composed of a microprocessor or the like and controls all the configuration blocks in the figure. The color conversion units 2 are respectively R
The image data R, G, and B sent from the memory 14, the G memory 15, and the B memory 16 are color-converted into color data in another color space. R memory 14, G memory 15, B
The memory 16 outputs the image data R, G, and B to the color conversion unit 2 in units of 1 byte at the timing of the read signal RDs from the control circuit 1. As described above, in this example, all the R, G, and B image data that have already been read by a scanner or the like are classified by color into the R memory 14 and the G memory 1 respectively.
5, B memory 16 is assumed to be stored.

The color conversion section 2 divides the R, G, and B spaces into a plurality of unit cubes, and divides the R, G, and B spaces into eight unit cubes into eight lattice points, as in the well-known conventional cube interpolation method. The color conversion value calculated in advance is stored, and R, G,
The color conversion values in the grid points corresponding to the input signals of B and
L by linearly interpolating from the color conversion values of the individual grid points
Each color data of *, a *, b * is calculated and input to the next error diffusion unit 3. It should be noted that L *, a *, and b * are CIE1976 L *, which is a substantially uniform scale for human color perception.
Color data of a * b * color system (color system defined by JIS Z8730).

That is, the color conversion section 2 prints the input signal system of R, G, B on the L * a * b printed by the recording section 13 described later.
* It is converted into color data of color system. This conversion is executed at the timing of the control signal RDo from the control circuit 1. The error diffusion units 3, 4, and 5 have the same configuration. The error diffusion units 3, 4, and 5 perform error diffusion processing on the input data L *, a *, and b *.
Details will be described later. In addition, these error diffusion units 3,
Reference numerals 4 and 5 are connected to the control circuit 1 and controlled by the control circuit 1.

YMCK conversion LUT composed of ROM
The (look-up table) 6 includes color data L * + ΔL *, a * + Δa from the error diffusion units 3, 4, and 5, respectively.
Direct the Y, M, C, and K color signals stored at the address designated by *, b * + Δb * to the latches 8 and 9 in synchronization with the read signal RD output from the OR gate 7. Output. The OR gate 7 performs a logical sum operation of the read signals RDym and RDck from the control circuit 1 and outputs the read signal RD to the YMCK conversion LUT 6 and the L * conversion unit 1.
0, a * converter 11, b * converter 12. The read signal RDym is also connected to the YMCK conversion LUT 6, and when the read signal RDym is output,
The Y and M color signals are output from the YMCK conversion LUT 6 and are latched by the latch 8. When the read signal RDck is output, the Y and MCK conversion LUT 6 outputs C and K color signals, which are latched by the latch 9.

Here, the Y and M color signals output from the YMCK conversion LUT 6 have a binary 8-bit structure, and the upper 4 bits represent the Y value and the lower 4 bits represent the M value. Similarly, the C and K color signals have a binary 8-bit structure, and the upper 4 bits are C.
Value, the lower 4 bits represent the K value. In addition, Y, M, C, K
Are color control signals of yellow, magenta, cyan, and black, which are supplied to the recording unit 13 described later.

The L * converter 10 composed of, for example, a ROM
Are the color data L * from the error diffusion units 3, 4, and 5, respectively.
The color data L * ′ stored at the address designated by + ΔL *, a * + Δa *, b * + Δb * is output to the error diffusion unit 3 in synchronization with the read signal RD. To do. R
The a * conversion unit 11 composed of OM has color data L * + ΔL * and a * + Δa from the error diffusion units 3, 4, and 5, respectively.
The color data a * ′ stored at the address designated by *, b * + Δb * are synchronized with the read signal RD,
Output to the error diffusion unit 4. B * composed of ROM
The conversion unit 12 stores the color data stored in the address address designated by the color data L * + ΔL *, a * + Δa *, b * + Δb * from the error diffusion units 3, 4, and 5, respectively. b
* 'Is output to the error diffusion unit 5 in synchronization with the read signal RD.

These L * converter 10, a * converter 11,
The b * conversion unit 12 actually uses the Y, M, C, and K color signals output from the YMCK conversion LUT 6 to actually perform the recording unit 13.
The color data L * ', a *', and b * 'to be printed in (1) are output. The recording unit 13 prints a color image on a recording medium in accordance with 4-bit Y, M, C, and K signals latched by the latches 8 and 9. The recording unit 13 uses the print signal PRC from the control circuit 1.
Is controlled by The print signal PRC controls all of the recording medium such as running of the recording medium, printing drive, and printing density.

<Color conversion value> Here, the color data L *, a *, b * printed by the recording unit 13 for the input values R, G, B signals at the lattice points of each unit cube of the color conversion unit 2.
The color conversion value to the will be described. Input value R, G, B
If the signal is a signal read by a scanner, hundreds of color chips are read by R, G, and B signals by the scanner, and color data L *, a *, b * of these color chips are measured. , Scanner R, G, B signals and color data L *, a *,
The relationship of b * is obtained. If the input values R, G, B signals are display signals of a display such as a CRT, color data L * of the color displayed on the display by each R, G, B signal,
The relationship between the two can be obtained by measuring the color of a * and b *. Further, by measuring the color chart printed in the recording unit 32 by the Y, M, C, K signals, the relationship between the Y, M, C, K signals and the color data L *, a *, b * can be obtained. .

By the way, as described in various documents, the range of reproducible colors is different between a fluorescent substance such as a scanner or CRT and a printing ink. Scanners and CRTs have a wide color gamut of green and blue with high saturation, and printed matter has a wide color gamut of cyan and yellow. Since the reproduction areas themselves are different, it is difficult to reproduce the green and blue phosphors on the printed matter, and the yellow on the printed matter may not be represented by a CRT, no matter how skillfully the color conversion is performed. Generally, the gamut of printed matter is narrower than the gamut of scanners and CRTs. Therefore, various color management methods have been proposed in which the input image data and the color expression range of the recording unit are associated with each other depending on the application.

For example, (A) a common area saving method in which a common area of the color gamut of the scanner and the printing is saved, and the protruding part is mapped to the outer edge of the color gamut of the printing while maintaining the brightness. Saturation saving method that compresses the color gamut so as not to change the saturation for colors that exceed the color gamut of printing, (C) The maximum brightness and the minimum brightness of the scanner and printing are relatively matched. Then, there is a relative lightness preservation method that rearranges all colors in a similar manner. The various color management methods described above are incorporated in the color conversion unit 2, and the input R, G,
Color data L printed by the recording unit 13 in response to the B signal
Color conversion values of *, a *, and b * are output. This is to find the relationship between the two using the color chart, etc.
Furthermore, a value calculated in advance by the least square method is used.
The calculated color conversion values may be given to the lattice points of the unit cube. Therefore, the color data L *, a *, and b * output from the color conversion unit 2 are values in the area where the recording unit 13 can reproduce colors. The R, G, B signals and the color data L *, a *, b * signals are composed of 8 bits.

Further, the YMCK conversion LUT 6 has the color data L * + ΔL *, a * + Δa after the error diffusion processing.
The Y, M, C, and K values of the color closest to *, b * + Δb * are obtained. Color data L * + ΔL *, a * + Δa
Each of *, b * + Δb * is an 8-bit value, and since the 1-bit read signal RDym is connected to the most significant address, a total of 25 bits are used for the address. Therefore, the ROM of YMCK conversion LUT6 is 32MB each.
It requires a huge capacity of yte. Therefore, the color data L
The lower 3 bits of * + ΔL *, a * + Δa *, b * + Δb * are discarded, and the upper 5 bits are connected to the addresses of the Y / M conversion LUT 24 and the C / K conversion LUT 25. As a result, the address becomes 16 bits and a ROM having a capacity of 64 KBytes is sufficient. Thus, the color closest to the color specification values L * + ΔL *, a * + Δa *, b * + Δb * designated by the upper 5 bits, that is, Y for which the color difference ΔE is the smallest, M, C, K
The color signal of is stored in the ROM of the YMCK conversion LUT6. Color difference ΔE is CIE1976L
*, A *, b * color system, that is, defined by JIS Z8730.

Since each of Y, M, and C has a value of 4 bits, that is, 16 gradations, the number of colors that can be expressed is 16 × 16.
× 16 = 4096 colors. However, the under color removal of the gray component in the Y, M, and C color signals (UCR: Under Color
Removal) and black signal K by skeleton black method
Is commonly done. Also in the present invention, U
In order to perform CR, four-color printing in which black ink K is added to Y, M, and C is performed. Therefore, the YMCK conversion LUT6
The K value output from is the one used for UCR.
Since UCR is well known, its details are omitted.

By recording hundreds of types of color chips and measuring the colors, the relationship between the Y, M, C signals and the color data L *, a *, b * can be obtained. From this relationship, the ROM contents of the YMCK conversion LUT 6 are determined. Also, L *
ROM of conversion unit 10, a * conversion unit 11, and b * conversion unit 12
The content is also determined from the above relationship. L * converter 1
The 0, a * conversion unit 11, and b * conversion unit 12 store the color data of the colors actually printed by the 4-bit Y, M, C, and K color signals.

<Error Distribution> FIG. 2 shows the error diffusion units 3, 4,
5 shows a detailed block diagram. Since the error diffusion units 3, 4, and 5 have the same configuration, the error diffusion unit 3 will be described as an example. First, the distribution ratio of the error value between the color data (L * + ΔL *) that should be printed originally and the color data L * ′ that is actually printed will be described. FIG. 3 shows neighboring pixels (i-1, j-1) for the pixel of interest (i, j),
(I, j-1), (i + 1, j-1), (i-1, j)
And the error distribution rate. The error distribution rate of the pixel (i-1, j-1) is 1/8, the error distribution rate of the pixel (i, j-1) is 1/4, and the error distribution rate of the pixel (i + 1, j-1) is 1. /
8. The error distribution ratio of pixel (i-1, j) is set to 1/2, and the sum of the error distribution ratios is set to 1.

The error value corresponding to each pixel is e (i
-1, j-1), e (i, j-1), e (i + 1, j-
1) and e (i-1, j), the pixel of interest (i, j)
The sum ΔL * of the error components is as shown in (1). ΔL * = e (i-1, j-1) / 8 + e (i, j-1) / 4 + e (i + 1, j-1) / 8 + e (i-1, j) / 2 (1) FIG. The equation (1) is realized.

<Error Diffusion Unit> Returning to FIG.
Is the color information (L * + ΔL) that should originally be printed.
The color information L * ′ actually printed is subtracted from *). That is, assuming that the subtracted value is e, the equation (2) is executed. e = (L * + ΔL *) − L * ′ (2) The selector 22 selects either the data “0” (NULL) set to the ground or the subtraction result e from the subtractor 21. And outputs to the 1/2 circuit 23. This selection is made by the selection signal Se from the control circuit 1 shown in FIG. 1. When Se = “L” (Low: false signal), NULL data is selected and Se =
When it is "H" (High: true signal), the subtraction value e is selected.

The halving circuit 23 divides the data sent from the selector 22 into halves. That is, in the 1/2 circuit 23, the error data e is 1 /
It is set to 2 and the error data of 1/2 e is transferred to the next latch 2
Send to 4. The latch 24 latches and outputs the error data from the 1/2 circuit 23 in synchronization with the control clock CL1 from the control circuit 1. 1 output from the latch 24
The / 2e error data is input to one terminal of the bus gate 25 and the adder 36. The ½e error data is the error data of the pixel (i−1, j) shown in FIG. 3 and has a value of e (i−1, j) / 2 in the equation (1).

The bus gate 25 sends the error data output from the latch 24 to the error memory 26 at the timing of the write control signal WRe from the control circuit 1. Error memory 26
Stores the 1 / 2e error data sent from the bus gate 25 by the write control signal WRe from the control circuit 1. The 1 / 2e error data stored in the error memory 26 is read by the read control signal RDe from the control circuit 1 and sent to the latch 30. The error memory 26 has at least 2 bytes more than the capacity of one line of image data,
That is, the capacity is n + 2 bytes. The writing counter 27
This is a counter that counts the storage destination address that stores the 1 / 2e error data sent from the bus gate 25 in the error memory 26 and outputs the address to the selector 29. The write counter 27 can raise and lower address addresses 0, 1, ... N.

The read counter 28 is a counter that counts the storage address address from which the error data stored in the error memory 26 is read and outputs the address address to the selector 29. The read counter 28 has 0, 1, ...
The address addresses up to n + 1 can be counted up. The write counter 27 and the read counter 28 can set the initial address, that is, the address 0, which is the top address of the error memory 26, by the Load signal from the control circuit 1.

The selector 29 is provided with the address address output from the write counter 27 or the read counter 28.
One of the address addresses output from the above is selected and sent to the address bus of the error memory 26. This selection is made by the read control signal RDe from the control circuit 1. When RDe = "L" (Low: false signal), the address address output from the read counter 28 is selected and RDe = "H" (High: When the signal is a true signal, the address address output from the write counter 27 is selected. That is, when the error data is read from the error memory 26, the address on the read counter 28 side is selected.

The latch 30 outputs the error data read from the error memory 26 to the control clock CL from the control circuit 1.
Latch output at the timing of 2. The latch 31 latches and outputs the error data sent from the latch 30 at the timing of the control clock CL2 from the control circuit 1. The latch 32 latches and outputs the error data sent from the latch 31 at the timing of the control clock CL2 from the control circuit 1. The latches 30, 31, and 32 simultaneously perform latch output at the timing of the control clock CL2, and the latch output shifts one by one to the right in FIG. The 1/4 circuit 33 divides the error data sent from the latch 30 into 1 /
Divide by 4. The error data divided into 1/4 is input to the other side of the adder 36.

Since the error data is first halved by the halving circuit 23 and further quartile by the quartering circuit 33, it is eventually halved as a whole. 1/4
The output value of the digitization circuit 33 is the pixel (i + 1, j−) shown in FIG.
It is the error data of 1), and e (i + 1, j- of the equation (1)
1) / 8. The halving circuit 34 includes the latch 31.
It divides the error data sent from the device by half. This halved error data is input to the other side of the adder 37. This error data is 1/2
Since it has been halved by the halving circuit 23 and further halved by the halving circuit 34, in the end it is ¼
I was told that. The output value of the halving circuit 34 is shown in FIG.
Error data of the pixel (i, j−1) shown in
This corresponds to e (i, j-1) / 4 in the equation (1).

The 1/4 conversion circuit 35 divides the error data sent from the latch 32 into 1/4. The error data divided into 1/4 is input to the other side of the adder 38. This error data is first halved circuit 2
Since it is halved by 3 and is made ¼ by the ¼ circuit 35, it is eventually ⅛ as a whole. The output value of the quarter circuit 35 is the error data of the pixel (i-1, j-1) shown in FIG. 3, and corresponds to e (i-1, j-1) / 8 in the equation (1). To do.

The adder 36 adds the respective error data from the 1/4 circuit 33 and the latch 24 and sends it to the next adder 37. By this addition, e (i + 1, j-1) in the equation (1) is obtained.
/ 8 + e (i-1, j) / 2 will be executed.
The adder 37 adds the error data from the halving circuit 34 and the adder 36, and sends it to the next adder 38. By this addition, e (i, j-1) / 4 + e (i + of the equation (1) is obtained.
1, j-1) / 8 + e (i-1, j) / 2 will be executed. The adder 38 adds the respective error data from the quarter-wave circuit 35 and the adder 37 and sends the result to the next adder 39. By this addition, e (i-1, j- in the equation (1) is obtained.
1) / 8 + e (i, j-1) / 4 + e (i + 1, j-
1) / 8 + e (i-1, j) / 2 full addition is performed.

In the adder 39, the addition result ΔL * of the equation (1) and the color specification value L * output from the color conversion unit 2 are added, and the addition result L * + ΔL * Is the subtractor 21 and the YMCK conversion LUT 6 and the L * conversion unit 1 shown in FIG.
0, a * conversion unit 11, and b * conversion unit 12. FIG.
The error diffusing unit 4 and the error diffusing unit 5 shown in FIG. 6 have exactly the same configuration as the error diffusing unit 3, and the error diffusing unit 4 performs the operation on the color data a * and the error diffusing unit 5 performs the operation on the color data b *. There is only a difference. The 1/2 circuit and the 1/4 circuit are described for convenience of explanation, and the division by 1/2 can be easily realized by ignoring without connecting the LSB least significant bit of the data output line. 1
The division of / 4 can be easily realized by ignoring the lower 2 bits on the LSB side of the data output line without connecting them.

The operation of the first specific example having the above configuration will be described. <Initial Settings> In this example, it is assumed that the R, G, and B image data are composed of n pixels in the main scanning direction and m lines in the sub scanning direction. As an initial setting, the control circuit 1 is previously set in FIG.
“0” is written as error data of the 0th line to the error memory 26 shown in (1) and all are cleared. This is done as follows.

In FIG. 2, according to an instruction from the control circuit 1,
Select Se = “L” for the selector 22 and
The data is output to the latch 24 via the halving circuit 23. Then, the control clock CL1 is output to the latch 24, and this NULL data is latched and output. In this state, the write control signal WRe is issued and the control clock CL
By writing NULL data to the error memory 26 through the bus gate 25 one after another while counting up the write counter 27 with w, the error memory 26 can be completely cleared.

<First Pixel on First Line> FIG.
6 is an operation time chart of the device of the first specific example. The operation of the present invention will be described below using this time chart. First, the control circuit 1 sets Lo at the timing shown in FIG.
The ad signal is issued to set the initial addresses of the write counter 27 and the read counter 28 shown in FIG. Next, the control circuit 1 outputs the read signal RDs, and the R memory 14, G of FIG.
The image data R, G, and B are read from the memory 15 and the B memory 16 by 1 byte, respectively, and output to the color conversion unit 2. (FIG. 4 (b)). As a result, the three-color image data R, G, and B are input to the color conversion unit 2. Here, the control circuit 1 outputs the control signal RDo to the color conversion unit 2 (see FIG. 4).
(C)). As a result, from the color conversion unit 2, the color data L *, a *, and b * to be printed by the recording unit 13 for the three-color image data R, G, and B are respectively transferred to the error diffusion units 3, 4, and.
Send to 5.

In the case of the image data of the first pixel on the line, the control circuit 1 outputs the read control signal RDe to the error memory 26 of FIG. 2 and the control clock CL2 to the latches 30, 31, 32 three times respectively. The error data at addresses 0, 1, and 2 are successively output and latched in the order of the latches 32, 31, and 30, respectively. (FIGS. 4 (e) and (f)). After the read control signal RDe is issued, the control clock CLd is issued at the timing shown in FIG. 4 (g) to increase the address value of the read counter 28 by one. become.

FIG. 5 shows a diagram for explaining the arithmetic operation. Generally, when the error diffusion processing is performed on the j-th line, the error data e of the pixel (1, j) is initially displayed as shown in FIG.
(1, j) is calculated. That is, the following equation is calculated. e (1, j) = e (0, j-1) / 8 + e (1, j-1) / 4 + e (2, j-1) / 8 + e (0, j) / 2 (3) In the latch 32, Error data e (0, j-1), error data e (1, j-1) in the latch 31, error data e (2, j-1) in the latch 30, error data e in the latch 24. If (0, j) / 2 is output as a latch, the adder 3
The addition result of 8 is the expression (3).

Now, since it is the first line, j = 1. In the above-mentioned latch 32, the error data e (0,0),
The latch 31 outputs the error data e (1,0) and the latch 30 outputs the error data e (2,0). Since the first line has no error in the previous line, the error memory 26 is set to 0 by default. Therefore,
The error data e (0, 0 stored in the error memory 26
0), e (1,0) ... e (n + 1,0) are all 0.

When outputting the first image data R, G, B of the line, the selection signal Se of the selector 22 is set to "Lo.
Set to w "level to output NULL data (Fig. 4
(D)). In this state, issue the control clock CL1
The latch 24 latches and outputs NULL data (see FIG. 4).
(H)). This data corresponds to the error data e (0,1) / 2. In this way, NULL data is always selected for the image data of the first pixel of the line, and as shown in FIG.
The write control signal WRe is issued at the timing shown in (i), the NULL data latched in the latch 24 is stored in the address 0 of the error memory 26, and then FIG.
The control clock CLw is issued at the timing shown in (1) to up-count the write counter 27 to the first address.

This stored data corresponds to the error data e (0,1) / 2 = 0 of the next line, that is, the second line. The error data stored before address 0 has already been output to the latch 32 and has already been used, so the data may be rewritten. From the above, the first calculation of the above formula (3) (individual color data error ΔL *, Δ
a *, Δb *) is performed. Further, this error data and the color data L *, a *, output from the color conversion unit 2,
b * is added by the adder 39 to obtain color data L *.
+ ΔL *, a * + Δa *, b * + Δb * are output to the YMCK conversion LUT 6, the L * conversion unit 10, the a * conversion unit 11, and the b * conversion unit 12.

Here, the read signal RDym is issued at the timing shown in FIG. 4 (k). This read signal RDym is YMC
It is also connected to the highest address of the K conversion LUT6,
While the read signal RDym is at the low level, the read signal RD which is the output from the OR gate 7 is at the low level, which holds the output of the Y and M color signals from the YMCK conversion LUT 6, respectively. While this signal is being output, the control clock CL is generated at the timing shown in FIG.
ym is output and the Y and M color signals are latched in the latch 8. Next, at the timing shown in FIG.
issue ck. At this time, the read signal RDym is at the high level, and the read signal RD output from the OR gate 7 is at the low level while the read signal RDck is at the low level.

As a result, the outputs of the C and K color signals from the YMCK conversion LUT 6 are held. While this is being output, the control clock CLck is output at the timing shown in FIG.
Latched. The YMCK conversion LUT 6 outputs the read signal RD.
When ym is Low, Y and M color signals are selected, and Hi
At the gh level, C and K color signals are selected and output. The read signal RD is also connected to the L * converter 10, the a * converter 11, and the b * converter 12, and is output from the L * converter 10, the a * converter 11, and the b * converter 12. The output color data L *, a *, b * of these color data are also sent to the error diffusion units 3, 4, and 5 while the read signal RD is at the Low level.

During this output, the subtracter 21 of the error diffusion unit 3 shown in FIG.
* + ΔL * and the difference between the printed color data L * ′ (L *
+ ΔL *) − L * ′ subtraction, subtracter 2 of error diffusion unit 4
1 subtraction of difference (a * + Δa *) − a * ′ between color data a * + Δa * to be printed and color data a * ′ to be printed, printed by subtracter 21 of error diffusion unit 5. The difference (b * + Δb *) − b * ′ between the color data b * + Δb * to be printed and the color data b * ′ to be printed is subtracted. These values are the color error data e (1,1).

At this time, since the selection signal Se is set to the High level at the timing shown in FIG. 4D, the control clock CL1 is set at the timing shown in FIG.
The error data e (1,1) / 2 that has been halved is latched in the latch 24 via the halving circuit 23. After latching, the write control signal WRe is issued as shown in FIG.
(1, 1) / 2 is stored in the error memory 26 at the address of address 1. It will be used for error diffusion processing of the next line of these stored error data. Thus, the processing for the first pixel is completed.

<Second Pixel on First Line> Next, the control circuit 1 outputs the second read signal RDs and the R memory 1
The image data R, G, and B are read from the 4, G memory 15, and B memory 16 by 1 byte, respectively, and output to the color conversion unit 2 (FIG. 4B). As a result, the three-color image data R, G, and B are input to the color conversion unit 2. Here, the control circuit 1 outputs the control signal RDo to the color conversion unit 2 (see FIG. 4).
(C)). As a result, from the color conversion unit 2, the color data L *, a *, and b * to be printed by the recording unit 13 for the three-color image data R, G, and B are respectively transferred to the error diffusion units 3, 4, and.
Send to 5.

Here, the control circuit 1 issues the read control signal RDe and the control clock CL2 to the error memory 26 shown in FIG. 2 and outputs the error data at the address 3 to the latch 30 respectively. By this operation, the error data at the address 3 is stored in the latch 30, the error data at the address 2 previously latched by the latch 30 is stored in the latch 31, and the error data at the latch 32 is stored in the latch 32.
The error data at the first address that was previously latched by the latch 31 will be latched. After issuing the read control signal RDe, the control clock CLd is issued at the timing shown in FIG. 4 (i) to increment the address value of the read counter 28 by one. become.

As shown in FIG. 5B, the error data e (2, j) of the pixel (2, j) is calculated. That is, the following equation (4) is calculated. e (2, j) = e (1, j-1) / 8 + e (2, j-1) / 4 + e (3, j-1) / 8 + e (1, j) / 2 (4) In the latch 32 Is the error data e (1, j-1), the latch 31 is the error data e (2, j-1), the latch 30 is the error data e (3, j-1), and the latch 24 is the error data e (3, j-1). If e (1, j) is latched and output, the addition result of the adder 38 becomes the expression (4).

Now, since it is the first line, j = 1. The error data e (1,0),
The latch 31 outputs the error data e (2,0) and the latch 30 outputs the error data e (3,0). Since the first line has no error in the previous line, the error memory 36 is initially set to 0. The latch 24 stores the error data e generated by the calculation of FIG.
Latch output of (1, 1) / 2.

As described above, the second operation of the equation (4) (individually, the error amount ΔL *, Δa *, Δb * of the color data) is performed. Further, this error data and the color conversion unit 2
The L *, a *, and b * output from each are added by the adder 39, and the color data L * + ΔL *, a * + Δa, b
* + Δb * is YMCK conversion LUT 6 and L * conversion unit 1
0, a * conversion unit 11, and b * conversion unit 12. Here, the read signal Dym is issued at the timing shown in FIG. The read signal Dym is also connected to the highest address of the YMCK conversion LUT, and the read signal Dym is Low.
During the level, the read signal R which is the output from the OR gate 7
D is a low level, which allows YMCK conversion LU
The outputs of the Y and M color signals from T6 are held.

While this signal is being output, as shown in FIG.
The control clock CLym is output at the timing shown in (l), and the Y and M color signals are latched in the latch 8. Next, the read signal RDck is issued at the timing shown in FIG. At this time, the read signal RDym is at the high level, and while the read signal RDck is at the low level, the read signal RD which is the output from the OR gate 7 is at the low level.
The outputs of the color signals of K and K are held. While this signal is being output, the control clock CLck is output at the timing shown in FIG. 4 (n), and the color signals C and K are latched by the latch 9. The YMCK conversion LUT 6 is designed so that the Y and M color signals are selected when the read signal Dym is Low, and the C and K color signals are selected and output when the read signal Dym is High.

The read signal RD is sent to the L * converter 1
0, a * conversion unit 11, b * conversion unit 12, and L * conversion unit 10, a * conversion unit 11, b * conversion unit 12
The color data L *, a *, b * output from the read signal R
While D is Low level, these outputs are sent to the error diffusion units 3, 4, and 5, respectively. While this is being output, the difference (L * + ΔL *) − L between the color data L * + ΔL * to be printed and the color data L * ′ to be printed by the subtracter 21 of the error diffusion unit 3 The difference between the color data a * + Δa * to be printed by the subtracter 21 of the error diffusion unit 4 and the color data a * ′ to be printed (a * + Δa *)-
a * ′ subtraction, color data b * + Δb * to be printed by the subtracter 21 of the error diffusion unit 5 and color data b to be printed
Subtraction of the difference (b * + Δ (b * + Δb *) − b * ′) from * 'is performed. These values are color error data e (2,
1). At this time, since the selection signal Se is set to the high level at the timing shown in FIG. 4D, the control clock CL1 is made at the timing shown in FIG.
Then, the error data e (2,1) / 2 that has been halved is latched in the latch 24 via the halving circuit 23. After latching, the write control signal WRe is issued as shown in FIG.
(2,1) / 2 is stored in the error memory 26 at the address of address 2. The stored error data will be used for the error diffusion process of the next line. Thus, the process of the second pixel is completed.

As shown in FIG. 5, i = 3 to n, that is, the same process as the second pixel is performed from the third pixel to the nth pixel. After the error data e (n, 1) / 2 of the n-th pixel is stored in the error memory 26 at the address of the n-th address, the process for the second line is started. The processing for the second line is performed in exactly the same way as for the first line. At this time, the error data generated in the processing of the first line and stored in the error memory 56 is used. By performing the same process up to the m-th line, the input image data R, G, B are Y,
Latch 8 and latch 9 converted into M, C, K color signals
It is sent one after another to the recording unit 13 via. In the recording unit 13, a full-color image is recorded on the recording medium according to the color signals having the gradation information of Y, M, C, K sent.

<Embodiment 2> FIG. 6 and FIG. 7 are block diagrams showing a construction according to Embodiment 2 of the present invention. The characteristic of the second specific example is that R, G, and
B image data, Y, M, C output to the recording unit 13,
This is in the use of a memory that stores K print image data. A second embodiment of the present invention will be described below with reference to the drawings. The components having the same functions as those in the first embodiment are designated by the same reference numerals and names, and the description thereof will be omitted.

In FIG. 6 and FIG. 7, the control circuit 41 is composed of a microprocessor and the like, and the interface section 42 for controlling all the constituent blocks in the figure is supplied from an external device (not shown) (for example, a host computer or a scanner) by R. ,
This is an interface circuit for inputting G and B input image data. The interface unit 42 is connected to receive the interface control signal I / FC of the control circuit 41. This interface control signal I / FC
Is a sampling clock signal for sampling input image data, a request signal for requesting image data from an external device, a line valid signal indicating the effective length of one line of image data sent from the external device, etc. Become.

The memory R43 and the memory G44 are memories for storing the input image data received by the interface section 42 and output to the data bus Do. Here, the memory R43 stores the input image data regarding R (red), and the memory G44 stores the input image data regarding G (green), and each has a storage capacity of one page (n pixels × m lines). is there. The storage of the input image data is performed by the write control signals WRr and WRg from the control circuit 41, respectively. Also, the memory R4
3. Reading of image data from the memory G44 is performed by reading control signals RDr and RDg from the control circuit 41, respectively.
Done by

The address counters 45 and 46 are counters for designating the memory addresses of the memory R43 and the memory G44, respectively. The address counters 45 and 46 are controlled by the control clocks CLr and CLg from the control circuit 41.
The memory address is up-counted.
Further, the address counters 45 and 46 can load the address AD set by the control circuit 41 at the timing of the LD signal from the control circuit 41 and start counting up from the address AD. Latch 4
Reference numerals 7, 48, 49 are latch circuits for latching the image data R, G, B respectively by the edge trigger of the control clock CLo. The image data R, G, B latched via the latches 47, 48, 49 are input to the color conversion unit 2, respectively.

The color conversion section 2 has exactly the same construction as that of the first embodiment, and therefore its explanation is omitted. The same applies to conversion of the R, G, and B input signal systems into the L * a * b * color system printed by the recording unit 13 at the timing of the control signal RDo from the control circuit 1. The error diffusion units 3, 4, and 5 have the same configuration as that of the first embodiment. In addition, these error diffusion units 3,
4 and 5 are connected to the control circuit 41,
Is controlled by The Y / M conversion LUT (look-up table) 50 is specifically configured by a ROM, and color data L * from the error diffusion units 3, 4, and 5, respectively.
The control circuit 41 determines the Y / M value stored at the address designated by + ΔL *, a * + Δa *, b * + Δb *.
L * converter 52 and a * converter 5 in synchronization with the signal RD1 of
3, and outputs to the b * converter 54 and the bus gate 55.
Similarly, a C / K conversion LUT (look-up table) 5
Specifically, reference numeral 1 is a ROM, and color data L * + ΔL *, a from the error diffusion units 3, 4, and 5, respectively.
The CK value stored in the address specified by * + Δa *, b * + Δb * is converted into the signal RDI of the control circuit 41.
And outputs to the L * converter 52, the a * converter 53, the b * converter 54, and the bus gate 55.

Here, the Y · M value has a binary 8-bit structure,
The upper 4 bits represent the C color signal, and the lower 4 bits represent the M color signal. The C and K values also have a binary 8-bit structure, with the upper 4 bits representing the C color signal and the lower 4 bits representing the K color signal.
Note that Y, M, C, and K are ink control amount signals for yellow, magenta, cyan, and black, respectively, which are supplied to the recording unit 13 as in the first embodiment. L * converter 5
Reference numeral 2 is for outputting color data L * 'corresponding to the Y / M value and the C / K value respectively output from the Y / M conversion LUT 50 and the C / K conversion LUT 51. Specifically, it is composed of a ROM. There is. The a * conversion unit 53 uses the Y / M conversion LUT5.
0 and Y / M values output from the C / K conversion LUT 51,
The color data a * ′ corresponding to the C / K value is output.
Specifically, it is composed of a ROM. The b * conversion unit 54 outputs color data b * ′ corresponding to the Y / M and C / K values output from the Y / M conversion LUT 50 and the C / K conversion LUT 51.
Is output, and is specifically configured by a ROM.

These L * converter 52, a * converter 53,
The b * converter 54 synchronizes with the control clock RDI,
The color data L * ', a *', and b * 'to be printed by the recording unit 13 are output according to the Y, M, C, and K signals.
The bus gate 55 synchronizes with the write control signal WRr from the control circuit 41, and the output of the Y / M conversion LUT 50 is Y / M.
It is a driver for outputting on the M value JWO data bus Do. This Y · M value output on the data bus Do is written to the memory R43 at the same address where the image data R latched by the latch 47 described above was stored. The bus gate 56 outputs the output C / K value of the C / K conversion LUT 51 to the data bus D in synchronization with the read signal WRg from the control circuit 41.
It is a driver that outputs to the above.

This C · K output on the data bus Do
The value is the memory G4 of the same address where the image data G latched by the latch 48 described above was stored.
4 is written. The latch 57 reads the Y / M values stored in the memory R43 and the C / K values stored in the memory G44, and latches and outputs them to the recording unit 13 in synchronization with the control clock CLp from the control circuit 41. Is. The recording unit 13 has the Y latched by the latch 57,
A color image is printed on a recording medium in accordance with M, C, and K signals. The recording unit 13 is controlled by the print signal PRC from the control circuit 41. The print signal PRC controls all of the recording, such as running of the recording medium, printing drive, and printing density. This recording unit 13
Is the same as that described in the first embodiment.

The R, G, B signals and the color data L *, a *, b * signals used in the second embodiment are composed of 8 bits as in the first embodiment. The Y / M conversion LUT 50 and the C / K conversion LUT 51 are color data L * + ΔL *, a * + Δa *, b * after the error diffusion processing.
The Y, M, C, and K values of the color closest to + Δb * are obtained. Color data L * + ΔL *, a * + Δa *, b **
Each Δb * is an 8-bit value, but if a total of 24 bits are used for the address as it is, the ROMs of the Y / M conversion LUT 50 and the C / K conversion LUT 51 are 16 MBy each.
A huge capacity of te is required. Therefore, the color data L *
The lower 3 bits of + ΔL *, a * + Δa *, b * + Δb * are discarded, and the upper 5 bits are Y / M conversion LUT 50 and C
-Connect to the address of the K conversion LUT 51.

As a result, the address becomes 15 bits, and a ROM having a capacity of 32 KBytes is sufficient. In this way, the color specification values L * + ΔL *, a * + Δa specified by the upper 5 bits
Colors closest to *, b * + Δb *, that is, Y, M, C, and K values that minimize the color difference ΔE are Y / M conversion LUT 50 and C / K.
It may be stored in the ROM of the conversion LUT 51. The color difference ΔE is defined by CIE1976L * a * b * color system, that is, JIS Z8730.

Since each of Y, M, and C has a value of 4 bits, that is, 16 gradations, the number of colors that can be expressed is 16 × 16.
× 16 = 4096 colors. However, the under color removal of the gray component in the Y, M, and C color signals (UCR: Under C
It is a common practice to replace the black signal K by the skeleton black method after the color removal. In the present invention, since this UCR is performed, four-color printing in which black ink is added to Y, M, and C is performed. Therefore, the above C
The K value output from the K conversion LUT 51 is used for UCR. Since UCR is well known, its details are omitted.

Y, M, C signals and color data L *, a *, b
The relationship with * can be obtained by recording hundreds of color charts and measuring the colors. From this relationship, the ROM contents of the Y / M conversion LUT 50 and the C / K conversion LUT 51 are determined. In addition, the L * conversion unit 52 and the a * conversion unit 5
3, the ROM content of the b * converter 54 is also determined from the above relationship. The L * conversion unit 52, the a * conversion unit 53, and the b * conversion unit 54 store color data of the colors actually printed by the 4-bit Y, M, C, and K signals. Become.

FIG. 8 shows a storage arrangement of image data in the memory R43 and the memory G44. As shown in the figure, the memory addresses of n pixel columns in the main scanning direction and m lines in the sub scanning direction are addressed. As described above, the memory R43 and the memory G44 store the image data D1.1 to Dn.m in 8-bit units for m lines × n pixel columns in pixel units. The m lines in the main scanning direction and the n pixel columns in the sub scanning direction in FIG. 8 correspond to the image arrangement printed by the recording unit 13. D1 ・ 1, D2 ・ for both writing and reading
1, D3 · 1 ... Dn−1 · 1Dn · 1, D1 · 2, D2
・ 2 ... Dn ・ 2 ... D1 ・ ∼Dn ・ m are stored or read in this order. Therefore, the control clocks CLr, CLg from the control circuit 41 operate the address counters 45, 46 to set the address, and the write control signals WRr, WRg, the read control signal RDr,
Storage and reading are performed by RDg, respectively.

The operation of the second embodiment having the above configuration will be described. <Initial setting> As an initial setting, the control circuit 41 preliminarily sets the address A to the address counters 45 and 46 so that the address address designated by D1.1 of FIG. 8 is set.
Issue D and LD signals. Further, the control circuit 41 writes "0" as error data of the 0th line to the error memory 56 shown in FIG. 2 and clears all. Since this operation has been described in the first embodiment, it will be omitted. <Storage of R and G Image Data> First, input image data R,
A case where G and B are sent to the interface unit 42 in the frame order will be described. Line-sequential and dot-sequential will be described later.

The interface section 42 inputs the input image data R
When the image data R is received, the image data R is sequentially stored in the memory R43.
To be stored. The control circuit 41 has an interface section 42.
It is known that the image data R is received by the interface control signal IFC with the writing control signal WRr.
The image data R is stored in the memory R43, and the address counter 45 outputs the control clock CLr to count up the address. As a result, the image data R received by the interface unit 42 one after another is stored in the memory R43. When the image data R for m lines × n pixel columns shown in FIG. 8 are all stored, the image data G is received next.

When the interface section 42 receives the image data G, the image data G is stored in the memory G44 one after another. The control circuit 41 knows that the image data R is received by the interface control signal IFC with the interface section 42, outputs the write control signal WRg each time, stores the image data G in the memory G44, and then the address counter 46. Then, the control clock CLg is issued to count up the address. As a result, the image data G received by the interface unit 42 is successively stored in the memory G4.
It is stored in 4. When all the image data G for m lines × n pixel columns shown in FIG. 8 are stored, the image data B is received next.

<Reception of B image data> First image data B
When the control signal 41 is received, the control circuit 41 outputs the address AD and LD signals and sets the address addresses designated by D1.1 of FIG. 8 in the address counters 45 and 46.

<First Pixel on First Line> FIGS. 9 and 10 are operation time charts of the second specific example. The operation of the present invention will be described below with reference to this figure. 1 on the first line
The image data B of the pixel eye (i = 1) is transferred to the interface unit 4
When 2 is received, the control circuit 41 outputs a Load signal at the timing shown in FIG. 9A to set initial addresses of the write counter 27 and the read counter 28. Then, the received image data B is output from the interface unit 42 to the data bus Do, the control clock CLo is output, and the image data B is latched and output by the latch 47 (FIGS. 9B and 9E). Next, the read control signal RDg is issued and the memory G
The image data G at the address D1.1 of the first line is read from 44 and the control clock CLo is issued at the same time (FIG. 9 (c)).
And (f)).

As a result, the image data B is transferred to the latch 4
8 and the image data G is latched and output by the latch 47. Further, the read control signal RDr is issued and D1 of the first line from the memory R43 is output.
-The image data R at the first address is read out, and at the same time, the control clock CLo is output (FIGS. 9D and 9E). As a result, the image data B is latched and output by the latch 49,
The image data G is latched and output by the latch 48, and the image data R is latched and output by the latch 47. The image data R, G, B of these three colors are input to the color conversion unit 2. Here, the control circuit 41 outputs the control signal RDo to the color conversion unit 2 (FIG. 9 (f)), whereby the color conversion unit 2 prints the image data R, G, B of the three colors on the recording unit 13. Color data L *, a *, which should be
B * is sent to the error diffusion units 3, 4, and 5, respectively.

In the case of the image data of the first pixel on the line, the control circuit 41 causes the error memory 26 to read the read control signal RD.
e and control clock CL2 are output three times in succession, and 0, 1,
Error data at address 2 is latched 32, 31, 30 respectively.
Latch output in order. After issuing the read control signal RDe, the control clock CLd is issued at the timing shown in FIG.
Since it is designed to be incremented, the read counter 28
Will be number 3.

Generally, when the error diffusion processing is performed on the j-th line, the error data e (1, j) of the pixel (1, j) is first calculated as shown in FIG. That is, the above (3)
The expression is calculated. The latch 32 stores the error data e (0, j
-1), and the latch 31 stores the error data e (1, j-1)
If the latch 30 outputs the error data e (2, j-1) and the latch 24 outputs the error data e (0, j) / 2, the addition result of the adder 38 is the above (3). It becomes an expression.

Now, since it is the first line, j = 1. In the above-mentioned latch 32, the error data e (0,0),
The latch 31 outputs the error data e (1,0) and the latch 30 outputs the error data e (2,0). Since the first line has no error in the previous line, the error memory 26 is set to 0 by default. Therefore,
The error data e (0, 0 stored in the error memory 26
0), e (1,0) ... e (n + 1,0) are all 0.

When the first image data B of the line is received, the selection signal Se of the selector 22 is set to "Low" level to output NULL data (FIG. 9 (g)).
In this state, the control clock CL1 is output and the latch 24
Latches and outputs NULL data (FIG. 10 (k)).
This data corresponds to the error data e (0,1). In this way, when the image data of the first pixel of the line
The ULL data is selected, and the write control signal WRe is issued at the timing shown in FIG.
The NULL data latched in is stored in the address 0 of the error memory 26, the control clock CLw is subsequently issued at the timing shown in FIG. 10 (m), and the write counter 27 is counted up to the address 1.

The stored data corresponds to the error data e (0,1) / 2 = 0 of the next line, that is, the second line. The error data stored before address 0 has already been output to the latch 32 and has already been used, so the data may be rewritten. From the above, the first operation of the equation (3) (the error amount ΔL *, Δ
a *, Δb *) is performed. Further, this error data and the color data L *, a * output from the color conversion unit 2 are
b * is added by the adder 39 to obtain color data L *.
+ ΔL *, a * + Δa *, b * + Δb * for Y / M conversion L
Output to the UT 50 and C / K conversion LUT 51.

Here, the control clock RD is issued at the timing shown in FIG. While the control clock RD is at the low level, the Y / M conversion LUT 50 and the C / K conversion LUT
Outputs of Y and M values and C and K values from 51 are held, respectively. The control clock RD is also connected to the L * converter 52, the a * converter 53, and the b * converter 54, and the L * converter 52, the a * converter 53, and the b * converter 5 are connected.
The color data L *, a *, and b * output from No. 4 also hold their output while the control clock RD is at the Low level. While this signal is being output, the write control signal WRr is output to the memory R43 and the bus gate 55 at the timing shown in FIG. 10 (o), and the Y output from the Y / M conversion LUT 50 is output.
Store the M value in memory R43.

The address address to be stored is the same address where the image data R latched and output to the latch 47 was stored. After the storage, the control clock CLr of FIG. 10 (p) is issued and the address counter 45 is counted up by one. Further, as shown in FIG. 10 (q), the write control signal WRg is output to the memory G44 and the bus gate 56,
The C / K value output from the C / K conversion LUT 51 is stored in the memory G44. The address to be stored is latch 4
8 is the same address where the image data G latched and output was stored. After the storage, the control clock CLg of FIG. 10 (r) is issued and the address counter 46 is incremented by 1.

During this storage, the subtracter 2 of the error diffusion unit 3
1 subtraction of difference (L * + ΔL *)-L * ′ between color data L * + ΔL * to be printed and color data L * ′ to be printed, and printing by subtracter 21 of error diffusion unit 4. The subtraction of the difference (a * + Δa *) − a * ′ between the color data a * + Δa * to be printed and the color data a * ′ to be printed, the error diffusion unit 5
Color data b * + Δb * to be printed by the subtractor 21
And the difference between the printed color data b * 'and (b * + Δb *)
Subtraction of -b * 'is performed. These values are the color error data e (1,1). At this time, FIG. 9 (g)
Since the selection signal Se is set to the high level at the timing shown in FIG. 10, the control clock CL1 is issued at the timing shown in FIG. The error data e (1,1)
Latch / 2 in the latch 24. Figure 10 after latching
As shown in (l), the write control signal WRe is issued and these error data e (1,1) / 2 are stored in the error memory 26 at the address of address 1. The stored error data will be used for the error diffusion process of the next line. Thus, the processing for the first pixel is completed.

<Processing of Second Pixel> Next, the control circuit 41 outputs the received image data B of the second pixel (i = 2) from the interface section 42 to the data bus Do, and outputs the control clock CLo. The image data B is latched and output by the latch 17. (FIGS. 9B and 9E). Next, the read control signal RDg is issued, and the first line D
The image data G at address 2.1 is read out, and at the same time, the control clock CLo is issued. (FIGS. 9 (c) and (e)). As a result, the image data b is latched and output by the latch 48, and the image data G is latched and output by the latch 47.

Further, the read control signal RDr is issued, and the image data R at the address D2.1 at the first line from the memory R43.
At the same time, and outputs the control clock CLo (see FIG. 9).
(D) and (e)). As a result, the image data B is latched and output by the latch 49, the image data G is latched and output by the latch 48, and the image data R is latched and output by the latch 47. The image data R, G, B of these three colors are input to the color conversion unit 2. Here, the control circuit 41 sends the control signal RDo to the color conversion unit 2.
(FIG. 9 (f)). As a result, the color conversion units 2 to 3
Color data L *, a *, and b * to be printed by the recording unit 13 for the color image data R, G, and B are sent to the error diffusion units 3, 4, and 5, respectively.

Here, the control circuit 41 outputs the read control signal RDe and the control clock CL2 to the error memory 26, and outputs the read control signal RDe and the control clock CL2.
The error data of the address is latched and output to the latch 30. By this operation, the error data at the address 3 is latched in the latch 30, the error data at the address 2 previously latched in the latch 30 is latched in the latch 31, and the latch 32 is latched in the latch 31 first. The error data at address 1 will be latched.

After issuing the read control signal RDe, FIG.
Since the control clock CLd is issued at the timing shown in (i) to increment the address value of the read counter 28 by one, the read counter 28 has the following four addresses. As shown in FIG. 5B, the error data e (2, j) of the pixel (2, j) is calculated. That is, the equation (4) is calculated. Error data e (1, j-1) is stored in the latch 32.
However, the error data e (2, j-1) is stored in the latch 31, the error data e (3, j-1) is stored in the latch 30,
If the error data e (1, j) / 2 is latched and output to 4, the addition result of the adder 38 becomes the expression (4).

Now, since it is the first line, j = 1. The error data e (1,0) is output to the latch 32, the error data e (2,0) is output to the latch 30, and the error data e (3,0) is output to the latch 30. Since the first line has no error in the previous line, the error memory 26 is set to 0 by default. Therefore, the error data e (0,0), e stored in the error memory 26
All of (1,0) ... e (n + 1,0) are 0.
Error data e (1,1) / 2 generated by the operation of FIG. 5A is latched and output to the latch 24.

As described above, the second operation of the equation (4) (individually, the error amount ΔL *, Δa *, Δb * of the color data) is performed. Further, this error data and the color conversion unit 2
The L *, a *, and b * output from each are added by the adder 39, and color data L * + ΔL *, a * + Δa *,
b * + Δb * for Y / M conversion LUT50 and C / K conversion L
Output to UT51. Here, the control clock RD is issued as shown in FIG. Control clock RD is Low
Between levels, Y / M conversion LUT 50 and C / K conversion LU
Outputs of Y and M values and C and K values from T51 are held. The control clock RD is also connected to the L * converter 52, the a * converter 53, and the b * converter 54, and the L * converter 52, the a * converter 53, and the b * converter 5 are connected.
The color data L *, a *, b * output from No. 4 also hold their output while the control clock RD is at the Low level.

While this signal is being output,
The write control signal WRr is output to the memory R43 and the bus gate 55 at the timing shown in FIG.
The Y / M value output from is stored in the memory R43. The address address to be stored is the same address where the image data R latched and output to the latch 47 was stored. After the storage, the control clock CLr of FIG. 10 (p) is issued, and the address counter 45 is incremented by 1. Further, the write control signal WRg is output to the memory G44 and the bus gate 56 at the timing shown in FIG.
The C / K value output from the C / K conversion LUT 51 is stored in the memory G44. The address to be stored is latch 4
8 is the same address where the image data G latched and output was stored.

After storing, the control clock CL of FIG.
g is issued and the address counter 46 is incremented by 1. During this storage, the subtracter 21 of the error diffusion unit 3 subtracts the difference (L * + ΔL *) − L * ′ between the color data L * + ΔL * to be printed and the color data L * ′ to be printed. ,
The difference (a between the color data a * + Δa * to be printed by the subtracter 21 of the error diffusion unit 4 and the color data a * ′ to be printed (a
* + Δa *)-a * ′ subtraction, the difference (b * + Δ) between the color data b * + Δb * to be printed and the color data b * ′ to be printed by the subtracter 21 of the error diffusion unit 5. b *)-b * ′
Is subtracted. These values are the color error data e
(2,1).

At this time, since the selection signal Se is set to the high level as shown in FIG. 9 (g), the control clock CL1 is issued and this error data is set to 1 as shown in FIG. 10 (k). 1/2 via the conversion circuit 23
And the error data e (2,1) / 2 latch 24 which has been halved is latched. After latching, the write control signal WRe is issued as shown in FIG.
(2,1) / 2 is stored in the error memory 26 at the address of address 2. The stored error data will be used for the error diffusion process of the next line. Thus, the process of the second pixel is completed.

I = 3 to n, that is, the same process as the second pixel is performed from the third pixel to the nth pixel. After the error data e (n, 1) / 2 of the n-th pixel is stored in the error memory 26 at the address of the n-th address, the process for the second line is started.
The processing of the second line is performed in exactly the same way as the processing of the first line. At this time, the error data generated in the processing of the first line and stored in the error memory 26 is used. By performing the same processing up to the m-th line, the input image data R, G, B are converted into Y, M, C, K signals printed by the recording unit 13 and stored in the memory R43 and the memory G44 one after another. To be done. Further, the stored Y, M, C, and K signals are full-color signals obtained by error diffusion processing of color information.

<Record> Next, the stored Y, M, C, K
The signal is initialized by the address AD and LD signals from the control circuit 41 and then read control signals WRr and W.
Rg is read out, read from the memory R43 and the memory G44 one after another, latched by the latch 57, and the recording unit 13
Will be sent to and printed. This sent Y,
The data formats of the M, C, and K signals are converted into a format suitable for the recording unit 13 and sent.

<Dot Sequential> In the case of dot sequential, since the image data R, G, B are sent in pixel units, the image data R, G, B received by the interface unit 42 are stored in the memory R4.
3 and memory G44 directly, B, G, directly
It may be sent to the latches 47, 48, 49 in the order of R and latched. Since the subsequent operation is as described above, the description will be omitted.

<Line Sequential> In the case of line sequential, image data R, G and B are sent line by line. Therefore, the image data received by the interface unit 42 may be processed line by line. First, the control circuit 41 specifies the start address of the first line by the address AD and LD signals,
The image data R of the first line is stored in the memory R43.
Next, the image data G of the first line is stored in the memory G44. Then, when the image data B is received, the received image data B and the memory G44 are received in the same manner as described above.
The following operation for sending the image data G stored in 1 to the image data R stored in the memory R43 to the latches 47, 48 and 49 in this order is as described above. When the image data of the first line is color-converted into Y, M, C, and K color signals and stored in the memory R43 and the memory G44, the image data of the second line is received next and the same as the first line. To process. As described above, the image data R
It suffices to process G and B and operate in the same way up to the final m lines. Needless to say, the address setting of the address counters 45 and 46 is performed every line unit by the address AD and LD signals of the control circuit 41.

<Effect> As described in detail above, according to the present invention, even in a recording section having a poor gradation expression, the input image data R , G, B are converted into color data of the L * a * b * color system, which is a substantially uniform scale for human perception of color, and the color data error is diffused based on this color data. ,
Since the three-dimensional lookup table for converting the color data after the error diffusion processing into the Y, M, C, and K recording portion color signals that minimize the color difference is provided, the input image data R,
This has an effect of not deteriorating the color reproducibility and gradation characteristics of the recording portion for G and B.

Further, in the second specific example, R, G, and 8 bits of three bits for three colors, which are input in a frame sequential manner from an external device,
Of the B image signals, a page memory for storing image signals for two colors is provided, and the color-converted Y of 4 bits or less,
Since the color signals of M, C, and K are stored in this page memory, one page of color is unnecessary for the page memory.
The effect is that an inexpensive full-color image processing device can be provided.

<Usage mode> The input image signal is not R, G, B, but color data L *, a *, corresponding to R, G, B.
It may be b *. L * a for the recording unit in the color conversion unit
Any input image signal may be used as long as it can be converted into color data of the * b * color system. Further, in this example, an example in which the color conversion unit converts into the L * a * b * color coordinate system has been described, but the CIE L * u * v * color coordinate system or the tristimulus values XYZ may be used. . In short, any known color coordinate space that quantitatively represents color information may be used. In addition, Y, M,
C and K are not limited to 4 bits. In the first embodiment, the number of bits may be smaller than that of the input image signal,
In the second embodiment, the number of bits of the input image signal may be half or less, that is, if the input image signal is 8 bits, Y, M,
C and K are 1 bit (2 gradations), 2 bits (4 gradations), 3
Bit 8 gradation may be used.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a specific example 1 of an image processing apparatus.

FIG. 2 is a detailed block diagram of error diffusion units 3, 4, and 5.

FIG. 3 is an explanatory diagram showing neighboring pixels and an error distribution rate for a pixel of interest.

FIG. 4 is an operation time chart of the device of the first specific example.

FIG. 5 is an explanatory diagram of a calculation operation.

FIG. 6 is a configuration block diagram (part 1) according to a second specific example of the present invention.

FIG. 7 is a configuration block diagram (part 2) according to a second specific example of the present invention.

FIG. 8 is an explanatory diagram showing a storage arrangement of image data in a memory R43 and a memory G44.

FIG. 9 is an operation time chart (part 1) of the second specific example.

FIG. 10 is an operation time chart of the second specific example (No. 2).

[Description of Codes] 1 control circuit 2 color conversion unit 3 to 5 error diffusion unit 6 YMCK conversion LUT 10 L * conversion unit 11 a * conversion unit 12 b * conversion unit 13 recording unit 14 R memory 15 G memory 16 B memory

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shuichiro Ogata 4-11-11 Shibaura 4-chome, Minato-ku, Tokyo

Claims (6)

[Claims] 1. An image based on the image data is printed by a recording unit which is inferior in gradation expression to the input full-color image data, and the input full-color image data is printed in a color printed by a human. A color conversion unit for converting color data of a predetermined color system that is a uniform scale for perception, and when focusing on each pixel forming the image, for each pixel,
After the error diffusion process, an error diffusion unit that distributes the error value based on the difference between the color data that should originally be printed and the color data that is actually printed by the recording unit so that it is diffused to peripheral pixels at a predetermined distribution ratio. YMCK conversion unit for converting color data of a predetermined color system of yellow to color data for printing of yellow (Y), magenta (M), cyan (C) and black (K), and a color for this printing A full-color image processing apparatus comprising: a recording unit that prints according to data. 2. The full-color image processing device according to claim 1, wherein the error diffusion unit includes a conversion unit for inputting color data actually printed by the recording unit, in addition to the output of the color conversion unit. . 3. The color conversion unit according to claim 1, wherein the full-color image data to be input is L * a * b * color system, L * u * v * color system, and tristimulus value X. , Y, Z color system, and a full-color image processing device for converting into color data of any color system. 4. The color conversion unit according to claim 1, wherein the color conversion unit inputs red (R), green (G), and blue (B).
The full-color image data of the three primary colors of the L * a * b * color system, the L * u * v * color system, and the tristimulus values X, Y, and Z color system. A full-color image processing device characterized by converting to color data of a color system. 5. An image based on the image data is printed by a recording unit which is inferior in gradation expression to the input full color image data, and the input full color image data is converted into an L * a * b * table. Each pixel that is configured by color data of a color system, an L * u * v * color system, and color data of one of the tristimulus value X, Y, and Z color systems, and that constitutes the image. When focusing on,
After the error diffusion process, an error diffusion unit that distributes the error value based on the difference between the color data that should originally be printed and the color data that is actually printed by the recording unit so that it is diffused to peripheral pixels at a predetermined distribution ratio. YMCK conversion unit for converting color data of a predetermined color system of yellow to color data for printing of yellow (Y), magenta (M), cyan (C) and black (K), and a color for this printing A full-color image processing apparatus comprising: a recording unit that prints according to data. 6. The full-color image data to be input according to claim 1, wherein N is a multiple of 8 and each N-bit signal is a combination of three types of color data. 4 of Y, M, C, K of N / 2 bits or less
When printing is performed by combining different types of color data, a memory that stores any two types of color data included in the full color image data, and the full color image data is stored in the Y, M, C, and K 4 A color conversion unit for converting into one kind of color data for printing, the color conversion unit is configured such that, for each of the memories, any two kinds of color data included in the full-color image data are separated by a predetermined unit amount. After being stored in order, the color data for each one pixel and the color data for one pixel of the third type that is subsequently input are collectively received from each memory, and converted into printing color data. The thus-obtained printing color data is connected for each two types, and temporarily stored in the same storage area where the unconverted color data is read from each memory, and all the full-color image data is stored. Conversion process To After the completion, a full-color image processing apparatus characterized by printing in the recording unit reads the print data from each memory.